1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2017 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg 24fb4d8502Sjsg #ifndef __AMDGPU_GART_H__ 25fb4d8502Sjsg #define __AMDGPU_GART_H__ 26fb4d8502Sjsg 27fb4d8502Sjsg #include <linux/types.h> 28fb4d8502Sjsg 29fb4d8502Sjsg /* 30fb4d8502Sjsg * GART structures, functions & helpers 31fb4d8502Sjsg */ 32fb4d8502Sjsg struct amdgpu_device; 33fb4d8502Sjsg struct amdgpu_bo; 34fb4d8502Sjsg 35fb4d8502Sjsg #define AMDGPU_GPU_PAGE_SIZE 4096 36fb4d8502Sjsg #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 37fb4d8502Sjsg #define AMDGPU_GPU_PAGE_SHIFT 12 38fb4d8502Sjsg #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 39fb4d8502Sjsg 40fb4d8502Sjsg #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE) 41fb4d8502Sjsg 42fb4d8502Sjsg struct amdgpu_gart { 43c349dbc7Sjsg struct amdgpu_bo *bo; 44c349dbc7Sjsg /* CPU kmapped address of gart table */ 45fb4d8502Sjsg void *ptr; 46fb4d8502Sjsg unsigned num_gpu_pages; 47fb4d8502Sjsg unsigned num_cpu_pages; 48fb4d8502Sjsg unsigned table_size; 49fb4d8502Sjsg 50fb4d8502Sjsg /* Asic default pte flags */ 51fb4d8502Sjsg uint64_t gart_pte_flags; 52fb4d8502Sjsg }; 53fb4d8502Sjsg 54*f005ef32Sjsg int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 55*f005ef32Sjsg void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 56fb4d8502Sjsg int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 57fb4d8502Sjsg void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 58fb4d8502Sjsg int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 59fb4d8502Sjsg void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 60fb4d8502Sjsg int amdgpu_gart_init(struct amdgpu_device *adev); 615ca02815Sjsg void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev); 621bb76ff1Sjsg void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 63fb4d8502Sjsg int pages); 641bb76ff1Sjsg void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 65fb4d8502Sjsg int pages, dma_addr_t *dma_addr, uint64_t flags, 66fb4d8502Sjsg void *dst); 671bb76ff1Sjsg void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 685ca02815Sjsg int pages, dma_addr_t *dma_addr, uint64_t flags); 695ca02815Sjsg void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev); 70fb4d8502Sjsg #endif 71