xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_encoders.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1fb4d8502Sjsg /*
2fb4d8502Sjsg  * Copyright 2007-8 Advanced Micro Devices, Inc.
3fb4d8502Sjsg  * Copyright 2008 Red Hat Inc.
4fb4d8502Sjsg  *
5fb4d8502Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
6fb4d8502Sjsg  * copy of this software and associated documentation files (the "Software"),
7fb4d8502Sjsg  * to deal in the Software without restriction, including without limitation
8fb4d8502Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9fb4d8502Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
10fb4d8502Sjsg  * Software is furnished to do so, subject to the following conditions:
11fb4d8502Sjsg  *
12fb4d8502Sjsg  * The above copyright notice and this permission notice shall be included in
13fb4d8502Sjsg  * all copies or substantial portions of the Software.
14fb4d8502Sjsg  *
15fb4d8502Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16fb4d8502Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17fb4d8502Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18fb4d8502Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19fb4d8502Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20fb4d8502Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21fb4d8502Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
22fb4d8502Sjsg  *
23fb4d8502Sjsg  * Authors: Dave Airlie
24fb4d8502Sjsg  *          Alex Deucher
25fb4d8502Sjsg  */
26c349dbc7Sjsg 
27fb4d8502Sjsg #include <drm/amdgpu_drm.h>
28fb4d8502Sjsg #include "amdgpu.h"
29fb4d8502Sjsg #include "amdgpu_connectors.h"
30c349dbc7Sjsg #include "amdgpu_display.h"
31fb4d8502Sjsg #include "atom.h"
32fb4d8502Sjsg #include "atombios_encoders.h"
33fb4d8502Sjsg 
34fb4d8502Sjsg void
amdgpu_link_encoder_connector(struct drm_device * dev)35fb4d8502Sjsg amdgpu_link_encoder_connector(struct drm_device *dev)
36fb4d8502Sjsg {
37ad8b1aafSjsg 	struct amdgpu_device *adev = drm_to_adev(dev);
38fb4d8502Sjsg 	struct drm_connector *connector;
39c349dbc7Sjsg 	struct drm_connector_list_iter iter;
40fb4d8502Sjsg 	struct amdgpu_connector *amdgpu_connector;
41fb4d8502Sjsg 	struct drm_encoder *encoder;
42fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder;
43fb4d8502Sjsg 
44c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &iter);
45fb4d8502Sjsg 	/* walk the list and link encoders to connectors */
46c349dbc7Sjsg 	drm_for_each_connector_iter(connector, &iter) {
47fb4d8502Sjsg 		amdgpu_connector = to_amdgpu_connector(connector);
48fb4d8502Sjsg 		list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
49fb4d8502Sjsg 			amdgpu_encoder = to_amdgpu_encoder(encoder);
50fb4d8502Sjsg 			if (amdgpu_encoder->devices & amdgpu_connector->devices) {
51fb4d8502Sjsg 				drm_connector_attach_encoder(connector, encoder);
52fb4d8502Sjsg 				if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
53fb4d8502Sjsg 					amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector);
54fb4d8502Sjsg 					adev->mode_info.bl_encoder = amdgpu_encoder;
55fb4d8502Sjsg 				}
56fb4d8502Sjsg 			}
57fb4d8502Sjsg 		}
58fb4d8502Sjsg 	}
59c349dbc7Sjsg 	drm_connector_list_iter_end(&iter);
60fb4d8502Sjsg }
61fb4d8502Sjsg 
amdgpu_encoder_set_active_device(struct drm_encoder * encoder)62fb4d8502Sjsg void amdgpu_encoder_set_active_device(struct drm_encoder *encoder)
63fb4d8502Sjsg {
64fb4d8502Sjsg 	struct drm_device *dev = encoder->dev;
65fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
66fb4d8502Sjsg 	struct drm_connector *connector;
67c349dbc7Sjsg 	struct drm_connector_list_iter iter;
68fb4d8502Sjsg 
69c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &iter);
70c349dbc7Sjsg 	drm_for_each_connector_iter(connector, &iter) {
71fb4d8502Sjsg 		if (connector->encoder == encoder) {
72fb4d8502Sjsg 			struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
73*f005ef32Sjsg 
74fb4d8502Sjsg 			amdgpu_encoder->active_device = amdgpu_encoder->devices & amdgpu_connector->devices;
75fb4d8502Sjsg 			DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
76fb4d8502Sjsg 				  amdgpu_encoder->active_device, amdgpu_encoder->devices,
77fb4d8502Sjsg 				  amdgpu_connector->devices, encoder->encoder_type);
78fb4d8502Sjsg 		}
79fb4d8502Sjsg 	}
80c349dbc7Sjsg 	drm_connector_list_iter_end(&iter);
81fb4d8502Sjsg }
82fb4d8502Sjsg 
83fb4d8502Sjsg struct drm_connector *
amdgpu_get_connector_for_encoder(struct drm_encoder * encoder)84fb4d8502Sjsg amdgpu_get_connector_for_encoder(struct drm_encoder *encoder)
85fb4d8502Sjsg {
86fb4d8502Sjsg 	struct drm_device *dev = encoder->dev;
87fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
88c349dbc7Sjsg 	struct drm_connector *connector, *found = NULL;
89c349dbc7Sjsg 	struct drm_connector_list_iter iter;
90fb4d8502Sjsg 	struct amdgpu_connector *amdgpu_connector;
91fb4d8502Sjsg 
92c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &iter);
93c349dbc7Sjsg 	drm_for_each_connector_iter(connector, &iter) {
94fb4d8502Sjsg 		amdgpu_connector = to_amdgpu_connector(connector);
95c349dbc7Sjsg 		if (amdgpu_encoder->active_device & amdgpu_connector->devices) {
96c349dbc7Sjsg 			found = connector;
97c349dbc7Sjsg 			break;
98fb4d8502Sjsg 		}
99c349dbc7Sjsg 	}
100c349dbc7Sjsg 	drm_connector_list_iter_end(&iter);
101c349dbc7Sjsg 	return found;
102fb4d8502Sjsg }
103fb4d8502Sjsg 
104fb4d8502Sjsg struct drm_connector *
amdgpu_get_connector_for_encoder_init(struct drm_encoder * encoder)105fb4d8502Sjsg amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder)
106fb4d8502Sjsg {
107fb4d8502Sjsg 	struct drm_device *dev = encoder->dev;
108fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
109c349dbc7Sjsg 	struct drm_connector *connector, *found = NULL;
110c349dbc7Sjsg 	struct drm_connector_list_iter iter;
111fb4d8502Sjsg 	struct amdgpu_connector *amdgpu_connector;
112fb4d8502Sjsg 
113c349dbc7Sjsg 	drm_connector_list_iter_begin(dev, &iter);
114c349dbc7Sjsg 	drm_for_each_connector_iter(connector, &iter) {
115fb4d8502Sjsg 		amdgpu_connector = to_amdgpu_connector(connector);
116c349dbc7Sjsg 		if (amdgpu_encoder->devices & amdgpu_connector->devices) {
117c349dbc7Sjsg 			found = connector;
118c349dbc7Sjsg 			break;
119fb4d8502Sjsg 		}
120c349dbc7Sjsg 	}
121c349dbc7Sjsg 	drm_connector_list_iter_end(&iter);
122c349dbc7Sjsg 	return found;
123fb4d8502Sjsg }
124fb4d8502Sjsg 
amdgpu_get_external_encoder(struct drm_encoder * encoder)125fb4d8502Sjsg struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder)
126fb4d8502Sjsg {
127fb4d8502Sjsg 	struct drm_device *dev = encoder->dev;
128fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
129fb4d8502Sjsg 	struct drm_encoder *other_encoder;
130fb4d8502Sjsg 	struct amdgpu_encoder *other_amdgpu_encoder;
131fb4d8502Sjsg 
132fb4d8502Sjsg 	if (amdgpu_encoder->is_ext_encoder)
133fb4d8502Sjsg 		return NULL;
134fb4d8502Sjsg 
135fb4d8502Sjsg 	list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
136fb4d8502Sjsg 		if (other_encoder == encoder)
137fb4d8502Sjsg 			continue;
138fb4d8502Sjsg 		other_amdgpu_encoder = to_amdgpu_encoder(other_encoder);
139fb4d8502Sjsg 		if (other_amdgpu_encoder->is_ext_encoder &&
140fb4d8502Sjsg 		    (amdgpu_encoder->devices & other_amdgpu_encoder->devices))
141fb4d8502Sjsg 			return other_encoder;
142fb4d8502Sjsg 	}
143fb4d8502Sjsg 	return NULL;
144fb4d8502Sjsg }
145fb4d8502Sjsg 
amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder * encoder)146fb4d8502Sjsg u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
147fb4d8502Sjsg {
148fb4d8502Sjsg 	struct drm_encoder *other_encoder = amdgpu_get_external_encoder(encoder);
149fb4d8502Sjsg 
150fb4d8502Sjsg 	if (other_encoder) {
151fb4d8502Sjsg 		struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder);
152fb4d8502Sjsg 
153fb4d8502Sjsg 		switch (amdgpu_encoder->encoder_id) {
154fb4d8502Sjsg 		case ENCODER_OBJECT_ID_TRAVIS:
155fb4d8502Sjsg 		case ENCODER_OBJECT_ID_NUTMEG:
156fb4d8502Sjsg 			return amdgpu_encoder->encoder_id;
157fb4d8502Sjsg 		default:
158fb4d8502Sjsg 			return ENCODER_OBJECT_ID_NONE;
159fb4d8502Sjsg 		}
160fb4d8502Sjsg 	}
161fb4d8502Sjsg 	return ENCODER_OBJECT_ID_NONE;
162fb4d8502Sjsg }
163fb4d8502Sjsg 
amdgpu_panel_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * adjusted_mode)164fb4d8502Sjsg void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
165fb4d8502Sjsg 			     struct drm_display_mode *adjusted_mode)
166fb4d8502Sjsg {
167fb4d8502Sjsg 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
168fb4d8502Sjsg 	struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
169*f005ef32Sjsg 	unsigned int hblank = native_mode->htotal - native_mode->hdisplay;
170*f005ef32Sjsg 	unsigned int vblank = native_mode->vtotal - native_mode->vdisplay;
171*f005ef32Sjsg 	unsigned int hover = native_mode->hsync_start - native_mode->hdisplay;
172*f005ef32Sjsg 	unsigned int vover = native_mode->vsync_start - native_mode->vdisplay;
173*f005ef32Sjsg 	unsigned int hsync_width = native_mode->hsync_end - native_mode->hsync_start;
174*f005ef32Sjsg 	unsigned int vsync_width = native_mode->vsync_end - native_mode->vsync_start;
175fb4d8502Sjsg 
176fb4d8502Sjsg 	adjusted_mode->clock = native_mode->clock;
177fb4d8502Sjsg 	adjusted_mode->flags = native_mode->flags;
178fb4d8502Sjsg 
179fb4d8502Sjsg 	adjusted_mode->hdisplay = native_mode->hdisplay;
180fb4d8502Sjsg 	adjusted_mode->vdisplay = native_mode->vdisplay;
181fb4d8502Sjsg 
182fb4d8502Sjsg 	adjusted_mode->htotal = native_mode->hdisplay + hblank;
183fb4d8502Sjsg 	adjusted_mode->hsync_start = native_mode->hdisplay + hover;
184fb4d8502Sjsg 	adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
185fb4d8502Sjsg 
186fb4d8502Sjsg 	adjusted_mode->vtotal = native_mode->vdisplay + vblank;
187fb4d8502Sjsg 	adjusted_mode->vsync_start = native_mode->vdisplay + vover;
188fb4d8502Sjsg 	adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
189fb4d8502Sjsg 
190fb4d8502Sjsg 	drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
191fb4d8502Sjsg 
192fb4d8502Sjsg 	adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
193fb4d8502Sjsg 	adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
194fb4d8502Sjsg 
195fb4d8502Sjsg 	adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
196fb4d8502Sjsg 	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
197fb4d8502Sjsg 	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
198fb4d8502Sjsg 
199fb4d8502Sjsg 	adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
200fb4d8502Sjsg 	adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
201fb4d8502Sjsg 	adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
202fb4d8502Sjsg 
203fb4d8502Sjsg }
204fb4d8502Sjsg 
amdgpu_dig_monitor_is_duallink(struct drm_encoder * encoder,u32 pixel_clock)205fb4d8502Sjsg bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
206fb4d8502Sjsg 				    u32 pixel_clock)
207fb4d8502Sjsg {
208fb4d8502Sjsg 	struct drm_connector *connector;
209fb4d8502Sjsg 	struct amdgpu_connector *amdgpu_connector;
210fb4d8502Sjsg 	struct amdgpu_connector_atom_dig *dig_connector;
211fb4d8502Sjsg 
212fb4d8502Sjsg 	connector = amdgpu_get_connector_for_encoder(encoder);
213fb4d8502Sjsg 	/* if we don't have an active device yet, just use one of
214fb4d8502Sjsg 	 * the connectors tied to the encoder.
215fb4d8502Sjsg 	 */
216fb4d8502Sjsg 	if (!connector)
217fb4d8502Sjsg 		connector = amdgpu_get_connector_for_encoder_init(encoder);
218fb4d8502Sjsg 	amdgpu_connector = to_amdgpu_connector(connector);
219fb4d8502Sjsg 
220fb4d8502Sjsg 	switch (connector->connector_type) {
221fb4d8502Sjsg 	case DRM_MODE_CONNECTOR_DVII:
222fb4d8502Sjsg 	case DRM_MODE_CONNECTOR_HDMIB:
223fb4d8502Sjsg 		if (amdgpu_connector->use_digital) {
224fb4d8502Sjsg 			/* HDMI 1.3 supports up to 340 Mhz over single link */
2251bb76ff1Sjsg 			if (connector->display_info.is_hdmi) {
226fb4d8502Sjsg 				if (pixel_clock > 340000)
227fb4d8502Sjsg 					return true;
228fb4d8502Sjsg 				else
229fb4d8502Sjsg 					return false;
230fb4d8502Sjsg 			} else {
231fb4d8502Sjsg 				if (pixel_clock > 165000)
232fb4d8502Sjsg 					return true;
233fb4d8502Sjsg 				else
234fb4d8502Sjsg 					return false;
235fb4d8502Sjsg 			}
236fb4d8502Sjsg 		} else
237fb4d8502Sjsg 			return false;
238fb4d8502Sjsg 	case DRM_MODE_CONNECTOR_DVID:
239fb4d8502Sjsg 	case DRM_MODE_CONNECTOR_HDMIA:
240fb4d8502Sjsg 	case DRM_MODE_CONNECTOR_DisplayPort:
241fb4d8502Sjsg 		dig_connector = amdgpu_connector->con_priv;
242fb4d8502Sjsg 		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
243fb4d8502Sjsg 		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
244fb4d8502Sjsg 			return false;
245fb4d8502Sjsg 		else {
246fb4d8502Sjsg 			/* HDMI 1.3 supports up to 340 Mhz over single link */
2471bb76ff1Sjsg 			if (connector->display_info.is_hdmi) {
248fb4d8502Sjsg 				if (pixel_clock > 340000)
249fb4d8502Sjsg 					return true;
250fb4d8502Sjsg 				else
251fb4d8502Sjsg 					return false;
252fb4d8502Sjsg 			} else {
253fb4d8502Sjsg 				if (pixel_clock > 165000)
254fb4d8502Sjsg 					return true;
255fb4d8502Sjsg 				else
256fb4d8502Sjsg 					return false;
257fb4d8502Sjsg 			}
258fb4d8502Sjsg 		}
259fb4d8502Sjsg 	default:
260fb4d8502Sjsg 		return false;
261fb4d8502Sjsg 	}
262fb4d8502Sjsg }
263