1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3fb4d8502Sjsg * All Rights Reserved. 4fb4d8502Sjsg * 5fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 6fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 7fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 8fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 10fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 11fb4d8502Sjsg * 12fb4d8502Sjsg * The above copyright notice and this permission notice (including the next 13fb4d8502Sjsg * paragraph) shall be included in all copies or substantial portions of the 14fb4d8502Sjsg * Software. 15fb4d8502Sjsg * 16fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19fb4d8502Sjsg * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 23fb4d8502Sjsg */ 24fb4d8502Sjsg 25fb4d8502Sjsg #include <drm/amdgpu_drm.h> 26c349dbc7Sjsg #include <drm/drm_drv.h> 27f005ef32Sjsg #include <drm/drm_fbdev_generic.h> 28fb4d8502Sjsg #include <drm/drm_gem.h> 29ad8b1aafSjsg #include <drm/drm_managed.h> 30fb4d8502Sjsg #include <drm/drm_pciids.h> 31c349dbc7Sjsg #include <drm/drm_probe_helper.h> 32f005ef32Sjsg #include <drm/drm_vblank.h> 33f005ef32Sjsg 341bb76ff1Sjsg #include <linux/cc_platform.h> 351bb76ff1Sjsg #include <linux/dynamic_debug.h> 36f005ef32Sjsg #include <linux/module.h> 37f005ef32Sjsg #include <linux/mmu_notifier.h> 38f005ef32Sjsg #include <linux/pm_runtime.h> 39f005ef32Sjsg #include <linux/suspend.h> 40f005ef32Sjsg #include <linux/vga_switcheroo.h> 41fb4d8502Sjsg 42fb4d8502Sjsg #include "amdgpu.h" 43fb4d8502Sjsg #include "amdgpu_amdkfd.h" 44f005ef32Sjsg #include "amdgpu_dma_buf.h" 45f005ef32Sjsg #include "amdgpu_drv.h" 46f005ef32Sjsg #include "amdgpu_fdinfo.h" 47f005ef32Sjsg #include "amdgpu_irq.h" 48f005ef32Sjsg #include "amdgpu_psp.h" 49c349dbc7Sjsg #include "amdgpu_ras.h" 505ca02815Sjsg #include "amdgpu_reset.h" 51f005ef32Sjsg #include "amdgpu_sched.h" 52f005ef32Sjsg #include "amdgpu_xgmi.h" 53f005ef32Sjsg #include "../amdxcp/amdgpu_xcp_drv.h" 54c349dbc7Sjsg 55fb4d8502Sjsg /* 56fb4d8502Sjsg * KMS wrapper. 57fb4d8502Sjsg * - 3.0.0 - initial driver 58fb4d8502Sjsg * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 59fb4d8502Sjsg * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 60fb4d8502Sjsg * at the end of IBs. 61fb4d8502Sjsg * - 3.3.0 - Add VM support for UVD on supported hardware. 62fb4d8502Sjsg * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 63fb4d8502Sjsg * - 3.5.0 - Add support for new UVD_NO_OP register. 64fb4d8502Sjsg * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 65fb4d8502Sjsg * - 3.7.0 - Add support for VCE clock list packet 66fb4d8502Sjsg * - 3.8.0 - Add support raster config init in the kernel 67fb4d8502Sjsg * - 3.9.0 - Add support for memory query info about VRAM and GTT. 68fb4d8502Sjsg * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 69fb4d8502Sjsg * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 70fb4d8502Sjsg * - 3.12.0 - Add query for double offchip LDS buffers 71fb4d8502Sjsg * - 3.13.0 - Add PRT support 72fb4d8502Sjsg * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 73fb4d8502Sjsg * - 3.15.0 - Export more gpu info for gfx9 74fb4d8502Sjsg * - 3.16.0 - Add reserved vmid support 75fb4d8502Sjsg * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 76fb4d8502Sjsg * - 3.18.0 - Export gpu always on cu bitmap 77fb4d8502Sjsg * - 3.19.0 - Add support for UVD MJPEG decode 78fb4d8502Sjsg * - 3.20.0 - Add support for local BOs 79fb4d8502Sjsg * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 80fb4d8502Sjsg * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 81fb4d8502Sjsg * - 3.23.0 - Add query for VRAM lost counter 82fb4d8502Sjsg * - 3.24.0 - Add high priority compute support for gfx9 83fb4d8502Sjsg * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 84fb4d8502Sjsg * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 851bb76ff1Sjsg * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 86c349dbc7Sjsg * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 87c349dbc7Sjsg * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 88c349dbc7Sjsg * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 89c349dbc7Sjsg * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 90c349dbc7Sjsg * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 91c349dbc7Sjsg * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 92c349dbc7Sjsg * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 93c349dbc7Sjsg * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 94c349dbc7Sjsg * - 3.36.0 - Allow reading more status registers on si/cik 95c349dbc7Sjsg * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 96ad8b1aafSjsg * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 97ad8b1aafSjsg * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 98ad8b1aafSjsg * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 995ca02815Sjsg * - 3.41.0 - Add video codec query 1005ca02815Sjsg * - 3.42.0 - Add 16bpc fixed point display support 1011bb76ff1Sjsg * - 3.43.0 - Add device hot plug/unplug support 1021bb76ff1Sjsg * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 1031bb76ff1Sjsg * - 3.45.0 - Add context ioctl stable pstate interface 1041bb76ff1Sjsg * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 1051bb76ff1Sjsg * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 1061bb76ff1Sjsg * - 3.48.0 - Add IP discovery version info to HW INFO 107f005ef32Sjsg * - 3.49.0 - Add gang submit into CS IOCTL 108f005ef32Sjsg * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock 109f005ef32Sjsg * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock 110f005ef32Sjsg * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl 111f005ef32Sjsg * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields: 112f005ef32Sjsg * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size, 113f005ef32Sjsg * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi 114f005ef32Sjsg * 3.53.0 - Support for GFX11 CP GFX shadowing 115f005ef32Sjsg * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support 116fb4d8502Sjsg */ 117fb4d8502Sjsg #define KMS_DRIVER_MAJOR 3 118f005ef32Sjsg #define KMS_DRIVER_MINOR 54 119fb4d8502Sjsg #define KMS_DRIVER_PATCHLEVEL 0 120fb4d8502Sjsg 121f005ef32Sjsg unsigned int amdgpu_vram_limit = UINT_MAX; 1225ca02815Sjsg int amdgpu_vis_vram_limit; 123fb4d8502Sjsg int amdgpu_gart_size = -1; /* auto */ 124fb4d8502Sjsg int amdgpu_gtt_size = -1; /* auto */ 125fb4d8502Sjsg int amdgpu_moverate = -1; /* auto */ 126fb4d8502Sjsg int amdgpu_audio = -1; 1275ca02815Sjsg int amdgpu_disp_priority; 1285ca02815Sjsg int amdgpu_hw_i2c; 129fb4d8502Sjsg int amdgpu_pcie_gen2 = -1; 130fb4d8502Sjsg int amdgpu_msi = -1; 131c349dbc7Sjsg char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 132fb4d8502Sjsg int amdgpu_dpm = -1; 133fb4d8502Sjsg int amdgpu_fw_load_type = -1; 134fb4d8502Sjsg int amdgpu_aspm = -1; 135fb4d8502Sjsg int amdgpu_runtime_pm = -1; 136fb4d8502Sjsg uint amdgpu_ip_block_mask = 0xffffffff; 137fb4d8502Sjsg int amdgpu_bapm = -1; 1385ca02815Sjsg int amdgpu_deep_color; 139fb4d8502Sjsg int amdgpu_vm_size = -1; 140fb4d8502Sjsg int amdgpu_vm_fragment_size = -1; 141fb4d8502Sjsg int amdgpu_vm_block_size = -1; 1425ca02815Sjsg int amdgpu_vm_fault_stop; 1435ca02815Sjsg int amdgpu_vm_debug; 144fb4d8502Sjsg int amdgpu_vm_update_mode = -1; 1455ca02815Sjsg int amdgpu_exp_hw_support; 146fb4d8502Sjsg int amdgpu_dc = -1; 147fb4d8502Sjsg int amdgpu_sched_jobs = 32; 148fb4d8502Sjsg int amdgpu_sched_hw_submission = 2; 1495ca02815Sjsg uint amdgpu_pcie_gen_cap; 1505ca02815Sjsg uint amdgpu_pcie_lane_cap; 1511bb76ff1Sjsg u64 amdgpu_cg_mask = 0xffffffffffffffff; 152fb4d8502Sjsg uint amdgpu_pg_mask = 0xffffffff; 153fb4d8502Sjsg uint amdgpu_sdma_phase_quantum = 32; 154f005ef32Sjsg char *amdgpu_disable_cu; 155f005ef32Sjsg char *amdgpu_virtual_display; 156f005ef32Sjsg bool enforce_isolation; 1575ca02815Sjsg /* 1585ca02815Sjsg * OverDrive(bit 14) disabled by default 1595ca02815Sjsg * GFX DCS(bit 19) disabled by default 1605ca02815Sjsg */ 1615ca02815Sjsg uint amdgpu_pp_feature_mask = 0xfff7bfff; 1625ca02815Sjsg uint amdgpu_force_long_training; 163fb4d8502Sjsg int amdgpu_lbpw = -1; 164fb4d8502Sjsg int amdgpu_compute_multipipe = -1; 165fb4d8502Sjsg int amdgpu_gpu_recovery = -1; /* auto */ 1665ca02815Sjsg int amdgpu_emu_mode; 1675ca02815Sjsg uint amdgpu_smu_memory_pool_size; 1685ca02815Sjsg int amdgpu_smu_pptable_id = -1; 1695ca02815Sjsg /* 1705ca02815Sjsg * FBC (bit 0) disabled by default 1715ca02815Sjsg * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 1725ca02815Sjsg * - With this, for multiple monitors in sync(e.g. with the same model), 1735ca02815Sjsg * mclk switching will be allowed. And the mclk will be not foced to the 1745ca02815Sjsg * highest. That helps saving some idle power. 1755ca02815Sjsg * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 1765ca02815Sjsg * PSR (bit 3) disabled by default 1775ca02815Sjsg * EDP NO POWER SEQUENCING (bit 4) disabled by default 1785ca02815Sjsg */ 1795ca02815Sjsg uint amdgpu_dc_feature_mask = 2; 1805ca02815Sjsg uint amdgpu_dc_debug_mask; 1811bb76ff1Sjsg uint amdgpu_dc_visual_confirm; 182c349dbc7Sjsg int amdgpu_async_gfx_ring = 1; 183f005ef32Sjsg int amdgpu_mcbp = -1; 184c349dbc7Sjsg int amdgpu_discovery = -1; 1855ca02815Sjsg int amdgpu_mes; 1861bb76ff1Sjsg int amdgpu_mes_kiq; 187ad8b1aafSjsg int amdgpu_noretry = -1; 188c349dbc7Sjsg int amdgpu_force_asic_type = -1; 1895ca02815Sjsg int amdgpu_tmz = -1; /* auto */ 190ad8b1aafSjsg int amdgpu_reset_method = -1; /* auto */ 191ad8b1aafSjsg int amdgpu_num_kcq = -1; 1925ca02815Sjsg int amdgpu_smartshift_bias; 1931bb76ff1Sjsg int amdgpu_use_xgmi_p2p = 1; 1941bb76ff1Sjsg int amdgpu_vcnfw_log; 195676a087aSjsg int amdgpu_sg_display = -1; /* auto */ 196f005ef32Sjsg int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE; 1975ca02815Sjsg 1985ca02815Sjsg static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 199c349dbc7Sjsg 2001bb76ff1Sjsg DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 2011bb76ff1Sjsg "DRM_UT_CORE", 2021bb76ff1Sjsg "DRM_UT_DRIVER", 2031bb76ff1Sjsg "DRM_UT_KMS", 2041bb76ff1Sjsg "DRM_UT_PRIME", 2051bb76ff1Sjsg "DRM_UT_ATOMIC", 2061bb76ff1Sjsg "DRM_UT_VBL", 2071bb76ff1Sjsg "DRM_UT_STATE", 2081bb76ff1Sjsg "DRM_UT_LEASE", 2091bb76ff1Sjsg "DRM_UT_DP", 2101bb76ff1Sjsg "DRM_UT_DRMRES"); 2111bb76ff1Sjsg 212c349dbc7Sjsg struct amdgpu_mgpu_info mgpu_info = { 213c349dbc7Sjsg .mutex = RWLOCK_INITIALIZER("mgpu_info"), 2145ca02815Sjsg .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 2155ca02815Sjsg mgpu_info.delayed_reset_work, 2165ca02815Sjsg amdgpu_drv_delayed_reset_work_handler, 0), 217c349dbc7Sjsg }; 218c349dbc7Sjsg int amdgpu_ras_enable = -1; 219c349dbc7Sjsg uint amdgpu_ras_mask = 0xffffffff; 220ad8b1aafSjsg int amdgpu_bad_page_threshold = -1; 2215ca02815Sjsg struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 2225ca02815Sjsg .timeout_fatal_disable = false, 2235ca02815Sjsg .period = 0x0, /* default to 0x0 (timeout disable) */ 2245ca02815Sjsg }; 225fb4d8502Sjsg 226fb4d8502Sjsg /** 227fb4d8502Sjsg * DOC: vramlimit (int) 228fb4d8502Sjsg * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 229fb4d8502Sjsg */ 230fb4d8502Sjsg MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 231fb4d8502Sjsg module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 232fb4d8502Sjsg 233fb4d8502Sjsg /** 234fb4d8502Sjsg * DOC: vis_vramlimit (int) 235fb4d8502Sjsg * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 236fb4d8502Sjsg */ 237fb4d8502Sjsg MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 238fb4d8502Sjsg module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 239fb4d8502Sjsg 240fb4d8502Sjsg /** 241fb4d8502Sjsg * DOC: gartsize (uint) 242f005ef32Sjsg * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing. 243f005ef32Sjsg * The default is -1 (The size depends on asic). 244fb4d8502Sjsg */ 245f005ef32Sjsg MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)"); 246fb4d8502Sjsg module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 247fb4d8502Sjsg 248fb4d8502Sjsg /** 249fb4d8502Sjsg * DOC: gttsize (int) 250f005ef32Sjsg * Restrict the size of GTT domain (for userspace use) in MiB for testing. 251f005ef32Sjsg * The default is -1 (Use 1/2 RAM, minimum value is 3GB). 252fb4d8502Sjsg */ 253f005ef32Sjsg MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)"); 254fb4d8502Sjsg module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 255fb4d8502Sjsg 256fb4d8502Sjsg /** 257fb4d8502Sjsg * DOC: moverate (int) 258fb4d8502Sjsg * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 259fb4d8502Sjsg */ 260fb4d8502Sjsg MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 261fb4d8502Sjsg module_param_named(moverate, amdgpu_moverate, int, 0600); 262fb4d8502Sjsg 263fb4d8502Sjsg /** 264fb4d8502Sjsg * DOC: audio (int) 265fb4d8502Sjsg * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 266fb4d8502Sjsg */ 267fb4d8502Sjsg MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 268fb4d8502Sjsg module_param_named(audio, amdgpu_audio, int, 0444); 269fb4d8502Sjsg 270fb4d8502Sjsg /** 271fb4d8502Sjsg * DOC: disp_priority (int) 272fb4d8502Sjsg * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 273fb4d8502Sjsg */ 274fb4d8502Sjsg MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 275fb4d8502Sjsg module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 276fb4d8502Sjsg 277fb4d8502Sjsg /** 278fb4d8502Sjsg * DOC: hw_i2c (int) 279fb4d8502Sjsg * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 280fb4d8502Sjsg */ 281fb4d8502Sjsg MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 282fb4d8502Sjsg module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 283fb4d8502Sjsg 284fb4d8502Sjsg /** 285fb4d8502Sjsg * DOC: pcie_gen2 (int) 286fb4d8502Sjsg * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 287fb4d8502Sjsg */ 288fb4d8502Sjsg MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 289fb4d8502Sjsg module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 290fb4d8502Sjsg 291fb4d8502Sjsg /** 292fb4d8502Sjsg * DOC: msi (int) 293fb4d8502Sjsg * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 294fb4d8502Sjsg */ 295fb4d8502Sjsg MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 296fb4d8502Sjsg module_param_named(msi, amdgpu_msi, int, 0444); 297fb4d8502Sjsg 298fb4d8502Sjsg /** 299c349dbc7Sjsg * DOC: lockup_timeout (string) 300c349dbc7Sjsg * Set GPU scheduler timeout value in ms. 301c349dbc7Sjsg * 302c349dbc7Sjsg * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 303c349dbc7Sjsg * multiple values specified. 0 and negative values are invalidated. They will be adjusted 304c349dbc7Sjsg * to the default timeout. 305c349dbc7Sjsg * 306c349dbc7Sjsg * - With one value specified, the setting will apply to all non-compute jobs. 307c349dbc7Sjsg * - With multiple values specified, the first one will be for GFX. 308c349dbc7Sjsg * The second one is for Compute. The third and fourth ones are 309c349dbc7Sjsg * for SDMA and Video. 310c349dbc7Sjsg * 311c349dbc7Sjsg * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 3125ca02815Sjsg * jobs is 10000. The timeout for compute is 60000. 313fb4d8502Sjsg */ 3145ca02815Sjsg MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 315f005ef32Sjsg "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 316c349dbc7Sjsg "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 317c349dbc7Sjsg module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 318fb4d8502Sjsg 319fb4d8502Sjsg /** 320fb4d8502Sjsg * DOC: dpm (int) 321c349dbc7Sjsg * Override for dynamic power management setting 3225ca02815Sjsg * (0 = disable, 1 = enable) 323c349dbc7Sjsg * The default is -1 (auto). 324fb4d8502Sjsg */ 325fb4d8502Sjsg MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 326fb4d8502Sjsg module_param_named(dpm, amdgpu_dpm, int, 0444); 327fb4d8502Sjsg 328fb4d8502Sjsg /** 329fb4d8502Sjsg * DOC: fw_load_type (int) 3301bb76ff1Sjsg * Set different firmware loading type for debugging, if supported. 3311bb76ff1Sjsg * Set to 0 to force direct loading if supported by the ASIC. Set 3321bb76ff1Sjsg * to -1 to select the default loading mode for the ASIC, as defined 3331bb76ff1Sjsg * by the driver. The default is -1 (auto). 334fb4d8502Sjsg */ 3351bb76ff1Sjsg MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 336fb4d8502Sjsg module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 337fb4d8502Sjsg 338fb4d8502Sjsg /** 339fb4d8502Sjsg * DOC: aspm (int) 340fb4d8502Sjsg * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 341fb4d8502Sjsg */ 342fb4d8502Sjsg MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 343fb4d8502Sjsg module_param_named(aspm, amdgpu_aspm, int, 0444); 344fb4d8502Sjsg 345fb4d8502Sjsg /** 346fb4d8502Sjsg * DOC: runpm (int) 3471bb76ff1Sjsg * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 3481bb76ff1Sjsg * the dGPUs when they are idle if supported. The default is -1 (auto enable). 3491bb76ff1Sjsg * Setting the value to 0 disables this functionality. 350f005ef32Sjsg * Setting the value to -2 is auto enabled with power down when displays are attached. 351fb4d8502Sjsg */ 352f005ef32Sjsg MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = autowith displays)"); 353fb4d8502Sjsg module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 354fb4d8502Sjsg 355fb4d8502Sjsg /** 356fb4d8502Sjsg * DOC: ip_block_mask (uint) 357fb4d8502Sjsg * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 358fb4d8502Sjsg * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 359fb4d8502Sjsg * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 360fb4d8502Sjsg * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 361fb4d8502Sjsg */ 362fb4d8502Sjsg MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 363fb4d8502Sjsg module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 364fb4d8502Sjsg 365fb4d8502Sjsg /** 366fb4d8502Sjsg * DOC: bapm (int) 367fb4d8502Sjsg * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 368fb4d8502Sjsg * The default -1 (auto, enabled) 369fb4d8502Sjsg */ 370fb4d8502Sjsg MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 371fb4d8502Sjsg module_param_named(bapm, amdgpu_bapm, int, 0444); 372fb4d8502Sjsg 373fb4d8502Sjsg /** 374fb4d8502Sjsg * DOC: deep_color (int) 375fb4d8502Sjsg * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 376fb4d8502Sjsg */ 377fb4d8502Sjsg MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 378fb4d8502Sjsg module_param_named(deep_color, amdgpu_deep_color, int, 0444); 379fb4d8502Sjsg 380fb4d8502Sjsg /** 381fb4d8502Sjsg * DOC: vm_size (int) 382fb4d8502Sjsg * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 383fb4d8502Sjsg */ 384fb4d8502Sjsg MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 385fb4d8502Sjsg module_param_named(vm_size, amdgpu_vm_size, int, 0444); 386fb4d8502Sjsg 387fb4d8502Sjsg /** 388fb4d8502Sjsg * DOC: vm_fragment_size (int) 389fb4d8502Sjsg * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 390fb4d8502Sjsg */ 391fb4d8502Sjsg MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 392fb4d8502Sjsg module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 393fb4d8502Sjsg 394fb4d8502Sjsg /** 395fb4d8502Sjsg * DOC: vm_block_size (int) 396fb4d8502Sjsg * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 397fb4d8502Sjsg */ 398fb4d8502Sjsg MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 399fb4d8502Sjsg module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 400fb4d8502Sjsg 401fb4d8502Sjsg /** 402fb4d8502Sjsg * DOC: vm_fault_stop (int) 403fb4d8502Sjsg * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 404fb4d8502Sjsg */ 405fb4d8502Sjsg MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 406fb4d8502Sjsg module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 407fb4d8502Sjsg 408fb4d8502Sjsg /** 409fb4d8502Sjsg * DOC: vm_debug (int) 410fb4d8502Sjsg * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 411fb4d8502Sjsg */ 412fb4d8502Sjsg MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 413fb4d8502Sjsg module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 414fb4d8502Sjsg 415fb4d8502Sjsg /** 416fb4d8502Sjsg * DOC: vm_update_mode (int) 417fb4d8502Sjsg * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 418fb4d8502Sjsg * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 419fb4d8502Sjsg */ 420fb4d8502Sjsg MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 421fb4d8502Sjsg module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 422fb4d8502Sjsg 423fb4d8502Sjsg /** 424fb4d8502Sjsg * DOC: exp_hw_support (int) 425fb4d8502Sjsg * Enable experimental hw support (1 = enable). The default is 0 (disabled). 426fb4d8502Sjsg */ 427fb4d8502Sjsg MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 428fb4d8502Sjsg module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 429fb4d8502Sjsg 430fb4d8502Sjsg /** 431fb4d8502Sjsg * DOC: dc (int) 432fb4d8502Sjsg * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 433fb4d8502Sjsg */ 434fb4d8502Sjsg MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 435fb4d8502Sjsg module_param_named(dc, amdgpu_dc, int, 0444); 436fb4d8502Sjsg 437fb4d8502Sjsg /** 438fb4d8502Sjsg * DOC: sched_jobs (int) 439fb4d8502Sjsg * Override the max number of jobs supported in the sw queue. The default is 32. 440fb4d8502Sjsg */ 441fb4d8502Sjsg MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 442fb4d8502Sjsg module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 443fb4d8502Sjsg 444fb4d8502Sjsg /** 445fb4d8502Sjsg * DOC: sched_hw_submission (int) 446fb4d8502Sjsg * Override the max number of HW submissions. The default is 2. 447fb4d8502Sjsg */ 448fb4d8502Sjsg MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 449fb4d8502Sjsg module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 450fb4d8502Sjsg 451fb4d8502Sjsg /** 452ad8b1aafSjsg * DOC: ppfeaturemask (hexint) 453fb4d8502Sjsg * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 454fb4d8502Sjsg * The default is the current set of stable power features. 455fb4d8502Sjsg */ 456fb4d8502Sjsg MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 457ad8b1aafSjsg module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 458fb4d8502Sjsg 459fb4d8502Sjsg /** 460c349dbc7Sjsg * DOC: forcelongtraining (uint) 461c349dbc7Sjsg * Force long memory training in resume. 462c349dbc7Sjsg * The default is zero, indicates short training in resume. 463c349dbc7Sjsg */ 464c349dbc7Sjsg MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 465c349dbc7Sjsg module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 466c349dbc7Sjsg 467c349dbc7Sjsg /** 468fb4d8502Sjsg * DOC: pcie_gen_cap (uint) 469fb4d8502Sjsg * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 470fb4d8502Sjsg * The default is 0 (automatic for each asic). 471fb4d8502Sjsg */ 472fb4d8502Sjsg MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 473fb4d8502Sjsg module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 474fb4d8502Sjsg 475fb4d8502Sjsg /** 476fb4d8502Sjsg * DOC: pcie_lane_cap (uint) 477fb4d8502Sjsg * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 478fb4d8502Sjsg * The default is 0 (automatic for each asic). 479fb4d8502Sjsg */ 480fb4d8502Sjsg MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 481fb4d8502Sjsg module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 482fb4d8502Sjsg 483fb4d8502Sjsg /** 4841bb76ff1Sjsg * DOC: cg_mask (ullong) 485fb4d8502Sjsg * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 4861bb76ff1Sjsg * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 487fb4d8502Sjsg */ 488fb4d8502Sjsg MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 4891bb76ff1Sjsg module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 490fb4d8502Sjsg 491fb4d8502Sjsg /** 492fb4d8502Sjsg * DOC: pg_mask (uint) 493fb4d8502Sjsg * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 494fb4d8502Sjsg * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 495fb4d8502Sjsg */ 496fb4d8502Sjsg MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 497fb4d8502Sjsg module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 498fb4d8502Sjsg 499fb4d8502Sjsg /** 500fb4d8502Sjsg * DOC: sdma_phase_quantum (uint) 501fb4d8502Sjsg * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 502fb4d8502Sjsg */ 503fb4d8502Sjsg MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 504fb4d8502Sjsg module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 505fb4d8502Sjsg 506fb4d8502Sjsg /** 507fb4d8502Sjsg * DOC: disable_cu (charp) 508fb4d8502Sjsg * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 509fb4d8502Sjsg */ 510fb4d8502Sjsg MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 511fb4d8502Sjsg module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 512fb4d8502Sjsg 513fb4d8502Sjsg /** 514fb4d8502Sjsg * DOC: virtual_display (charp) 515fb4d8502Sjsg * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 516fb4d8502Sjsg * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 517fb4d8502Sjsg * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 518fb4d8502Sjsg * device at 26:00.0. The default is NULL. 519fb4d8502Sjsg */ 520fb4d8502Sjsg MODULE_PARM_DESC(virtual_display, 521fb4d8502Sjsg "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 522fb4d8502Sjsg module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 523fb4d8502Sjsg 524fb4d8502Sjsg /** 525fb4d8502Sjsg * DOC: lbpw (int) 526fb4d8502Sjsg * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 527fb4d8502Sjsg */ 528fb4d8502Sjsg MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 529fb4d8502Sjsg module_param_named(lbpw, amdgpu_lbpw, int, 0444); 530fb4d8502Sjsg 531fb4d8502Sjsg MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 532fb4d8502Sjsg module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 533fb4d8502Sjsg 534fb4d8502Sjsg /** 535fb4d8502Sjsg * DOC: gpu_recovery (int) 536fb4d8502Sjsg * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 537fb4d8502Sjsg */ 538f005ef32Sjsg MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 539fb4d8502Sjsg module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 540fb4d8502Sjsg 541fb4d8502Sjsg /** 542fb4d8502Sjsg * DOC: emu_mode (int) 543fb4d8502Sjsg * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 544fb4d8502Sjsg */ 545fb4d8502Sjsg MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 546fb4d8502Sjsg module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 547fb4d8502Sjsg 548fb4d8502Sjsg /** 549c349dbc7Sjsg * DOC: ras_enable (int) 550c349dbc7Sjsg * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 551c349dbc7Sjsg */ 552c349dbc7Sjsg MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 553c349dbc7Sjsg module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 554c349dbc7Sjsg 555c349dbc7Sjsg /** 556c349dbc7Sjsg * DOC: ras_mask (uint) 557c349dbc7Sjsg * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 558c349dbc7Sjsg * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 559c349dbc7Sjsg */ 560c349dbc7Sjsg MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 561c349dbc7Sjsg module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 562c349dbc7Sjsg 563c349dbc7Sjsg /** 5645ca02815Sjsg * DOC: timeout_fatal_disable (bool) 5655ca02815Sjsg * Disable Watchdog timeout fatal error event 5665ca02815Sjsg */ 5675ca02815Sjsg MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 5685ca02815Sjsg module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 5695ca02815Sjsg 5705ca02815Sjsg /** 5715ca02815Sjsg * DOC: timeout_period (uint) 5725ca02815Sjsg * Modify the watchdog timeout max_cycles as (1 << period) 5735ca02815Sjsg */ 5745ca02815Sjsg MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 5755ca02815Sjsg module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 5765ca02815Sjsg 5775ca02815Sjsg /** 578fb4d8502Sjsg * DOC: si_support (int) 579fb4d8502Sjsg * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 580fb4d8502Sjsg * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 581fb4d8502Sjsg * otherwise using amdgpu driver. 582fb4d8502Sjsg */ 583fb4d8502Sjsg #ifdef CONFIG_DRM_AMDGPU_SI 584fb4d8502Sjsg 585f005ef32Sjsg #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 586fb4d8502Sjsg int amdgpu_si_support = 0; 587fb4d8502Sjsg MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 588fb4d8502Sjsg #else 589fb4d8502Sjsg int amdgpu_si_support = 1; 590fb4d8502Sjsg MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 591fb4d8502Sjsg #endif 592fb4d8502Sjsg 593fb4d8502Sjsg module_param_named(si_support, amdgpu_si_support, int, 0444); 594fb4d8502Sjsg #endif 595fb4d8502Sjsg 596fb4d8502Sjsg /** 597fb4d8502Sjsg * DOC: cik_support (int) 598fb4d8502Sjsg * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 599fb4d8502Sjsg * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 600fb4d8502Sjsg * otherwise using amdgpu driver. 601fb4d8502Sjsg */ 602fb4d8502Sjsg #ifdef CONFIG_DRM_AMDGPU_CIK 603fb4d8502Sjsg 604f005ef32Sjsg #if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) 605fb4d8502Sjsg int amdgpu_cik_support = 0; 606fb4d8502Sjsg MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 607fb4d8502Sjsg #else 608fb4d8502Sjsg int amdgpu_cik_support = 1; 609fb4d8502Sjsg MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 610fb4d8502Sjsg #endif 611fb4d8502Sjsg 612fb4d8502Sjsg module_param_named(cik_support, amdgpu_cik_support, int, 0444); 613fb4d8502Sjsg #endif 614fb4d8502Sjsg 615fb4d8502Sjsg /** 616fb4d8502Sjsg * DOC: smu_memory_pool_size (uint) 617fb4d8502Sjsg * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 618fb4d8502Sjsg * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 619fb4d8502Sjsg */ 620fb4d8502Sjsg MODULE_PARM_DESC(smu_memory_pool_size, 621f005ef32Sjsg "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 622fb4d8502Sjsg module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 623fb4d8502Sjsg 624c349dbc7Sjsg /** 625c349dbc7Sjsg * DOC: async_gfx_ring (int) 626c349dbc7Sjsg * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 627c349dbc7Sjsg */ 628c349dbc7Sjsg MODULE_PARM_DESC(async_gfx_ring, 629c349dbc7Sjsg "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 630c349dbc7Sjsg module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 631c349dbc7Sjsg 632c349dbc7Sjsg /** 633c349dbc7Sjsg * DOC: mcbp (int) 634f005ef32Sjsg * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default)) 635c349dbc7Sjsg */ 636c349dbc7Sjsg MODULE_PARM_DESC(mcbp, 637f005ef32Sjsg "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)"); 638c349dbc7Sjsg module_param_named(mcbp, amdgpu_mcbp, int, 0444); 639c349dbc7Sjsg 640c349dbc7Sjsg /** 641c349dbc7Sjsg * DOC: discovery (int) 642c349dbc7Sjsg * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 6431bb76ff1Sjsg * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 644c349dbc7Sjsg */ 645c349dbc7Sjsg MODULE_PARM_DESC(discovery, 646c349dbc7Sjsg "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 647c349dbc7Sjsg module_param_named(discovery, amdgpu_discovery, int, 0444); 648c349dbc7Sjsg 649c349dbc7Sjsg /** 650c349dbc7Sjsg * DOC: mes (int) 651c349dbc7Sjsg * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 652c349dbc7Sjsg * (0 = disabled (default), 1 = enabled) 653c349dbc7Sjsg */ 654c349dbc7Sjsg MODULE_PARM_DESC(mes, 655c349dbc7Sjsg "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 656c349dbc7Sjsg module_param_named(mes, amdgpu_mes, int, 0444); 657c349dbc7Sjsg 658ad8b1aafSjsg /** 6591bb76ff1Sjsg * DOC: mes_kiq (int) 6601bb76ff1Sjsg * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 6611bb76ff1Sjsg * (0 = disabled (default), 1 = enabled) 6621bb76ff1Sjsg */ 6631bb76ff1Sjsg MODULE_PARM_DESC(mes_kiq, 6641bb76ff1Sjsg "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 6651bb76ff1Sjsg module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 6661bb76ff1Sjsg 6671bb76ff1Sjsg /** 668ad8b1aafSjsg * DOC: noretry (int) 6695ca02815Sjsg * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 6705ca02815Sjsg * do not support per-process XNACK this also disables retry page faults. 671ad8b1aafSjsg * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 672ad8b1aafSjsg */ 673c349dbc7Sjsg MODULE_PARM_DESC(noretry, 674ad8b1aafSjsg "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 675c349dbc7Sjsg module_param_named(noretry, amdgpu_noretry, int, 0644); 676c349dbc7Sjsg 677c349dbc7Sjsg /** 678c349dbc7Sjsg * DOC: force_asic_type (int) 679c349dbc7Sjsg * A non negative value used to specify the asic type for all supported GPUs. 680c349dbc7Sjsg */ 681c349dbc7Sjsg MODULE_PARM_DESC(force_asic_type, 682c349dbc7Sjsg "A non negative value used to specify the asic type for all supported GPUs"); 683c349dbc7Sjsg module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 684c349dbc7Sjsg 6851bb76ff1Sjsg /** 6861bb76ff1Sjsg * DOC: use_xgmi_p2p (int) 6871bb76ff1Sjsg * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 6881bb76ff1Sjsg */ 6891bb76ff1Sjsg MODULE_PARM_DESC(use_xgmi_p2p, 6901bb76ff1Sjsg "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 6911bb76ff1Sjsg module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 692c349dbc7Sjsg 693c349dbc7Sjsg 694c349dbc7Sjsg #ifdef CONFIG_HSA_AMD 695c349dbc7Sjsg /** 696c349dbc7Sjsg * DOC: sched_policy (int) 697c349dbc7Sjsg * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 698c349dbc7Sjsg * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 699c349dbc7Sjsg * assigns queues to HQDs. 700c349dbc7Sjsg */ 701c349dbc7Sjsg int sched_policy = KFD_SCHED_POLICY_HWS; 702c349dbc7Sjsg module_param(sched_policy, int, 0444); 703c349dbc7Sjsg MODULE_PARM_DESC(sched_policy, 704c349dbc7Sjsg "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 705c349dbc7Sjsg 706c349dbc7Sjsg /** 707c349dbc7Sjsg * DOC: hws_max_conc_proc (int) 708c349dbc7Sjsg * Maximum number of processes that HWS can schedule concurrently. The maximum is the 709c349dbc7Sjsg * number of VMIDs assigned to the HWS, which is also the default. 710c349dbc7Sjsg */ 711bc521b2dSjsg int hws_max_conc_proc = -1; 712c349dbc7Sjsg module_param(hws_max_conc_proc, int, 0444); 713c349dbc7Sjsg MODULE_PARM_DESC(hws_max_conc_proc, 714c349dbc7Sjsg "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 715c349dbc7Sjsg 716c349dbc7Sjsg /** 717c349dbc7Sjsg * DOC: cwsr_enable (int) 718c349dbc7Sjsg * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 719c349dbc7Sjsg * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 720c349dbc7Sjsg * disables it. 721c349dbc7Sjsg */ 722c349dbc7Sjsg int cwsr_enable = 1; 723c349dbc7Sjsg module_param(cwsr_enable, int, 0444); 724c349dbc7Sjsg MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 725c349dbc7Sjsg 726c349dbc7Sjsg /** 727c349dbc7Sjsg * DOC: max_num_of_queues_per_device (int) 728c349dbc7Sjsg * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 729c349dbc7Sjsg * is 4096. 730c349dbc7Sjsg */ 731c349dbc7Sjsg int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 732c349dbc7Sjsg module_param(max_num_of_queues_per_device, int, 0444); 733c349dbc7Sjsg MODULE_PARM_DESC(max_num_of_queues_per_device, 734c349dbc7Sjsg "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 735c349dbc7Sjsg 736c349dbc7Sjsg /** 737c349dbc7Sjsg * DOC: send_sigterm (int) 738c349dbc7Sjsg * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 739c349dbc7Sjsg * but just print errors on dmesg. Setting 1 enables sending sigterm. 740c349dbc7Sjsg */ 741c349dbc7Sjsg int send_sigterm; 742c349dbc7Sjsg module_param(send_sigterm, int, 0444); 743c349dbc7Sjsg MODULE_PARM_DESC(send_sigterm, 744c349dbc7Sjsg "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 745c349dbc7Sjsg 746c349dbc7Sjsg /** 747c349dbc7Sjsg * DOC: debug_largebar (int) 748c349dbc7Sjsg * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 749c349dbc7Sjsg * system. This limits the VRAM size reported to ROCm applications to the visible 750c349dbc7Sjsg * size, usually 256MB. 751c349dbc7Sjsg * Default value is 0, diabled. 752c349dbc7Sjsg */ 753c349dbc7Sjsg int debug_largebar; 754c349dbc7Sjsg module_param(debug_largebar, int, 0444); 755c349dbc7Sjsg MODULE_PARM_DESC(debug_largebar, 756c349dbc7Sjsg "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 757c349dbc7Sjsg 758c349dbc7Sjsg /** 759c349dbc7Sjsg * DOC: halt_if_hws_hang (int) 760c349dbc7Sjsg * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 761c349dbc7Sjsg * Setting 1 enables halt on hang. 762c349dbc7Sjsg */ 763c349dbc7Sjsg int halt_if_hws_hang; 764c349dbc7Sjsg module_param(halt_if_hws_hang, int, 0644); 765c349dbc7Sjsg MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 766c349dbc7Sjsg 767c349dbc7Sjsg /** 768c349dbc7Sjsg * DOC: hws_gws_support(bool) 769ad8b1aafSjsg * Assume that HWS supports GWS barriers regardless of what firmware version 770ad8b1aafSjsg * check says. Default value: false (rely on MEC2 firmware version check). 771c349dbc7Sjsg */ 772c349dbc7Sjsg bool hws_gws_support; 773c349dbc7Sjsg module_param(hws_gws_support, bool, 0444); 774ad8b1aafSjsg MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 775c349dbc7Sjsg 776c349dbc7Sjsg /** 777c349dbc7Sjsg * DOC: queue_preemption_timeout_ms (int) 778c349dbc7Sjsg * queue preemption timeout in ms (1 = Minimum, 9000 = default) 779c349dbc7Sjsg */ 780c349dbc7Sjsg int queue_preemption_timeout_ms = 9000; 781c349dbc7Sjsg module_param(queue_preemption_timeout_ms, int, 0644); 782c349dbc7Sjsg MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 783ad8b1aafSjsg 784ad8b1aafSjsg /** 785ad8b1aafSjsg * DOC: debug_evictions(bool) 786ad8b1aafSjsg * Enable extra debug messages to help determine the cause of evictions 787ad8b1aafSjsg */ 788ad8b1aafSjsg bool debug_evictions; 789ad8b1aafSjsg module_param(debug_evictions, bool, 0644); 790ad8b1aafSjsg MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 791ad8b1aafSjsg 792ad8b1aafSjsg /** 793ad8b1aafSjsg * DOC: no_system_mem_limit(bool) 794ad8b1aafSjsg * Disable system memory limit, to support multiple process shared memory 795ad8b1aafSjsg */ 796ad8b1aafSjsg bool no_system_mem_limit; 797ad8b1aafSjsg module_param(no_system_mem_limit, bool, 0644); 798ad8b1aafSjsg MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 799ad8b1aafSjsg 8005ca02815Sjsg /** 8015ca02815Sjsg * DOC: no_queue_eviction_on_vm_fault (int) 8025ca02815Sjsg * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 8035ca02815Sjsg */ 804f005ef32Sjsg int amdgpu_no_queue_eviction_on_vm_fault; 8055ca02815Sjsg MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 8065ca02815Sjsg module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 807c349dbc7Sjsg #endif 808c349dbc7Sjsg 809c349dbc7Sjsg /** 810f005ef32Sjsg * DOC: mtype_local (int) 811f005ef32Sjsg */ 812f005ef32Sjsg int amdgpu_mtype_local; 813f005ef32Sjsg MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); 814f005ef32Sjsg module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); 815f005ef32Sjsg 816f005ef32Sjsg /** 8171bb76ff1Sjsg * DOC: pcie_p2p (bool) 8181bb76ff1Sjsg * Enable PCIe P2P (requires large-BAR). Default value: true (on) 8191bb76ff1Sjsg */ 8201bb76ff1Sjsg #ifdef CONFIG_HSA_AMD_P2P 8211bb76ff1Sjsg bool pcie_p2p = true; 8221bb76ff1Sjsg module_param(pcie_p2p, bool, 0444); 8231bb76ff1Sjsg MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 8241bb76ff1Sjsg #endif 8251bb76ff1Sjsg 8261bb76ff1Sjsg /** 827c349dbc7Sjsg * DOC: dcfeaturemask (uint) 828c349dbc7Sjsg * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 829c349dbc7Sjsg * The default is the current set of stable display features. 830c349dbc7Sjsg */ 831c349dbc7Sjsg MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 832c349dbc7Sjsg module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 833c349dbc7Sjsg 834c349dbc7Sjsg /** 835ad8b1aafSjsg * DOC: dcdebugmask (uint) 836ad8b1aafSjsg * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 837ad8b1aafSjsg */ 838ad8b1aafSjsg MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 839ad8b1aafSjsg module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 840ad8b1aafSjsg 8411bb76ff1Sjsg MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 8421bb76ff1Sjsg module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 8431bb76ff1Sjsg 844ad8b1aafSjsg /** 845c349dbc7Sjsg * DOC: abmlevel (uint) 846c349dbc7Sjsg * Override the default ABM (Adaptive Backlight Management) level used for DC 847c349dbc7Sjsg * enabled hardware. Requires DMCU to be supported and loaded. 848c349dbc7Sjsg * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 849c349dbc7Sjsg * default. Values 1-4 control the maximum allowable brightness reduction via 850c349dbc7Sjsg * the ABM algorithm, with 1 being the least reduction and 4 being the most 851c349dbc7Sjsg * reduction. 852c349dbc7Sjsg * 853c349dbc7Sjsg * Defaults to 0, or disabled. Userspace can still override this level later 854c349dbc7Sjsg * after boot. 855c349dbc7Sjsg */ 8565ca02815Sjsg uint amdgpu_dm_abm_level; 857c349dbc7Sjsg MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 858c349dbc7Sjsg module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 859c349dbc7Sjsg 860ad8b1aafSjsg int amdgpu_backlight = -1; 861ad8b1aafSjsg MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 862ad8b1aafSjsg module_param_named(backlight, amdgpu_backlight, bint, 0444); 863ad8b1aafSjsg 864ad8b1aafSjsg /** 865ad8b1aafSjsg * DOC: tmz (int) 866ad8b1aafSjsg * Trusted Memory Zone (TMZ) is a method to protect data being written 867ad8b1aafSjsg * to or read from memory. 868ad8b1aafSjsg * 869ad8b1aafSjsg * The default value: 0 (off). TODO: change to auto till it is completed. 870ad8b1aafSjsg */ 8715ca02815Sjsg MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 872ad8b1aafSjsg module_param_named(tmz, amdgpu_tmz, int, 0444); 873ad8b1aafSjsg 874ad8b1aafSjsg /** 8755ca02815Sjsg * DOC: reset_method (int) 8761bb76ff1Sjsg * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 8775ca02815Sjsg */ 8781bb76ff1Sjsg MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 879ad8b1aafSjsg module_param_named(reset_method, amdgpu_reset_method, int, 0444); 880ad8b1aafSjsg 881ad8b1aafSjsg /** 8825ca02815Sjsg * DOC: bad_page_threshold (int) Bad page threshold is specifies the 8835ca02815Sjsg * threshold value of faulty pages detected by RAS ECC, which may 8845ca02815Sjsg * result in the GPU entering bad status when the number of total 8855ca02815Sjsg * faulty pages by ECC exceeds the threshold value. 886ad8b1aafSjsg */ 887f005ef32Sjsg MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)"); 888ad8b1aafSjsg module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 889ad8b1aafSjsg 890ad8b1aafSjsg MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 891ad8b1aafSjsg module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 892ad8b1aafSjsg 8935ca02815Sjsg /** 8941bb76ff1Sjsg * DOC: vcnfw_log (int) 8951bb76ff1Sjsg * Enable vcnfw log output for debugging, the default is disabled. 8961bb76ff1Sjsg */ 8971bb76ff1Sjsg MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 8981bb76ff1Sjsg module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 8991bb76ff1Sjsg 9001bb76ff1Sjsg /** 901676a087aSjsg * DOC: sg_display (int) 902676a087aSjsg * Disable S/G (scatter/gather) display (i.e., display from system memory). 903676a087aSjsg * This option is only relevant on APUs. Set this option to 0 to disable 904676a087aSjsg * S/G display if you experience flickering or other issues under memory 905676a087aSjsg * pressure and report the issue. 906676a087aSjsg */ 907676a087aSjsg MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 908676a087aSjsg module_param_named(sg_display, amdgpu_sg_display, int, 0444); 909676a087aSjsg 910676a087aSjsg /** 9115ca02815Sjsg * DOC: smu_pptable_id (int) 9125ca02815Sjsg * Used to override pptable id. id = 0 use VBIOS pptable. 9135ca02815Sjsg * id > 0 use the soft pptable with specicfied id. 9145ca02815Sjsg */ 9155ca02815Sjsg MODULE_PARM_DESC(smu_pptable_id, 9165ca02815Sjsg "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 9175ca02815Sjsg module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 9185ca02815Sjsg 919f005ef32Sjsg /** 920f005ef32Sjsg * DOC: partition_mode (int) 921f005ef32Sjsg * Used to override the default SPX mode. 922f005ef32Sjsg */ 923f005ef32Sjsg MODULE_PARM_DESC( 924f005ef32Sjsg user_partt_mode, 925f005ef32Sjsg "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \ 926f005ef32Sjsg 0 = AMDGPU_SPX_PARTITION_MODE, \ 927f005ef32Sjsg 1 = AMDGPU_DPX_PARTITION_MODE, \ 928f005ef32Sjsg 2 = AMDGPU_TPX_PARTITION_MODE, \ 929f005ef32Sjsg 3 = AMDGPU_QPX_PARTITION_MODE, \ 930f005ef32Sjsg 4 = AMDGPU_CPX_PARTITION_MODE)"); 931f005ef32Sjsg module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444); 932f005ef32Sjsg 933f005ef32Sjsg 934f005ef32Sjsg /** 935f005ef32Sjsg * DOC: enforce_isolation (bool) 936f005ef32Sjsg * enforce process isolation between graphics and compute via using the same reserved vmid. 937f005ef32Sjsg */ 938f005ef32Sjsg module_param(enforce_isolation, bool, 0444); 939f005ef32Sjsg MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on"); 940f005ef32Sjsg 941875dd937Sjsg /* These devices are not supported by amdgpu. 942875dd937Sjsg * They are supported by the mach64, r128, radeon drivers 943875dd937Sjsg */ 944875dd937Sjsg static const u16 amdgpu_unsupported_pciidlist[] = { 945875dd937Sjsg /* mach64 */ 946875dd937Sjsg 0x4354, 947875dd937Sjsg 0x4358, 948875dd937Sjsg 0x4554, 949875dd937Sjsg 0x4742, 950875dd937Sjsg 0x4744, 951875dd937Sjsg 0x4749, 952875dd937Sjsg 0x474C, 953875dd937Sjsg 0x474D, 954875dd937Sjsg 0x474E, 955875dd937Sjsg 0x474F, 956875dd937Sjsg 0x4750, 957875dd937Sjsg 0x4751, 958875dd937Sjsg 0x4752, 959875dd937Sjsg 0x4753, 960875dd937Sjsg 0x4754, 961875dd937Sjsg 0x4755, 962875dd937Sjsg 0x4756, 963875dd937Sjsg 0x4757, 964875dd937Sjsg 0x4758, 965875dd937Sjsg 0x4759, 966875dd937Sjsg 0x475A, 967875dd937Sjsg 0x4C42, 968875dd937Sjsg 0x4C44, 969875dd937Sjsg 0x4C47, 970875dd937Sjsg 0x4C49, 971875dd937Sjsg 0x4C4D, 972875dd937Sjsg 0x4C4E, 973875dd937Sjsg 0x4C50, 974875dd937Sjsg 0x4C51, 975875dd937Sjsg 0x4C52, 976875dd937Sjsg 0x4C53, 977875dd937Sjsg 0x5654, 978875dd937Sjsg 0x5655, 979875dd937Sjsg 0x5656, 980875dd937Sjsg /* r128 */ 981875dd937Sjsg 0x4c45, 982875dd937Sjsg 0x4c46, 983875dd937Sjsg 0x4d46, 984875dd937Sjsg 0x4d4c, 985875dd937Sjsg 0x5041, 986875dd937Sjsg 0x5042, 987875dd937Sjsg 0x5043, 988875dd937Sjsg 0x5044, 989875dd937Sjsg 0x5045, 990875dd937Sjsg 0x5046, 991875dd937Sjsg 0x5047, 992875dd937Sjsg 0x5048, 993875dd937Sjsg 0x5049, 994875dd937Sjsg 0x504A, 995875dd937Sjsg 0x504B, 996875dd937Sjsg 0x504C, 997875dd937Sjsg 0x504D, 998875dd937Sjsg 0x504E, 999875dd937Sjsg 0x504F, 1000875dd937Sjsg 0x5050, 1001875dd937Sjsg 0x5051, 1002875dd937Sjsg 0x5052, 1003875dd937Sjsg 0x5053, 1004875dd937Sjsg 0x5054, 1005875dd937Sjsg 0x5055, 1006875dd937Sjsg 0x5056, 1007875dd937Sjsg 0x5057, 1008875dd937Sjsg 0x5058, 1009875dd937Sjsg 0x5245, 1010875dd937Sjsg 0x5246, 1011875dd937Sjsg 0x5247, 1012875dd937Sjsg 0x524b, 1013875dd937Sjsg 0x524c, 1014875dd937Sjsg 0x534d, 1015875dd937Sjsg 0x5446, 1016875dd937Sjsg 0x544C, 1017875dd937Sjsg 0x5452, 1018875dd937Sjsg /* radeon */ 1019875dd937Sjsg 0x3150, 1020875dd937Sjsg 0x3151, 1021875dd937Sjsg 0x3152, 1022875dd937Sjsg 0x3154, 1023875dd937Sjsg 0x3155, 1024875dd937Sjsg 0x3E50, 1025875dd937Sjsg 0x3E54, 1026875dd937Sjsg 0x4136, 1027875dd937Sjsg 0x4137, 1028875dd937Sjsg 0x4144, 1029875dd937Sjsg 0x4145, 1030875dd937Sjsg 0x4146, 1031875dd937Sjsg 0x4147, 1032875dd937Sjsg 0x4148, 1033875dd937Sjsg 0x4149, 1034875dd937Sjsg 0x414A, 1035875dd937Sjsg 0x414B, 1036875dd937Sjsg 0x4150, 1037875dd937Sjsg 0x4151, 1038875dd937Sjsg 0x4152, 1039875dd937Sjsg 0x4153, 1040875dd937Sjsg 0x4154, 1041875dd937Sjsg 0x4155, 1042875dd937Sjsg 0x4156, 1043875dd937Sjsg 0x4237, 1044875dd937Sjsg 0x4242, 1045875dd937Sjsg 0x4336, 1046875dd937Sjsg 0x4337, 1047875dd937Sjsg 0x4437, 1048875dd937Sjsg 0x4966, 1049875dd937Sjsg 0x4967, 1050875dd937Sjsg 0x4A48, 1051875dd937Sjsg 0x4A49, 1052875dd937Sjsg 0x4A4A, 1053875dd937Sjsg 0x4A4B, 1054875dd937Sjsg 0x4A4C, 1055875dd937Sjsg 0x4A4D, 1056875dd937Sjsg 0x4A4E, 1057875dd937Sjsg 0x4A4F, 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1458875dd937Sjsg 0x9552, 1459875dd937Sjsg 0x9553, 1460875dd937Sjsg 0x9555, 1461875dd937Sjsg 0x9557, 1462875dd937Sjsg 0x955f, 1463875dd937Sjsg 0x9580, 1464875dd937Sjsg 0x9581, 1465875dd937Sjsg 0x9583, 1466875dd937Sjsg 0x9586, 1467875dd937Sjsg 0x9587, 1468875dd937Sjsg 0x9588, 1469875dd937Sjsg 0x9589, 1470875dd937Sjsg 0x958A, 1471875dd937Sjsg 0x958B, 1472875dd937Sjsg 0x958C, 1473875dd937Sjsg 0x958D, 1474875dd937Sjsg 0x958E, 1475875dd937Sjsg 0x958F, 1476875dd937Sjsg 0x9590, 1477875dd937Sjsg 0x9591, 1478875dd937Sjsg 0x9593, 1479875dd937Sjsg 0x9595, 1480875dd937Sjsg 0x9596, 1481875dd937Sjsg 0x9597, 1482875dd937Sjsg 0x9598, 1483875dd937Sjsg 0x9599, 1484875dd937Sjsg 0x959B, 1485875dd937Sjsg 0x95C0, 1486875dd937Sjsg 0x95C2, 1487875dd937Sjsg 0x95C4, 1488875dd937Sjsg 0x95C5, 1489875dd937Sjsg 0x95C6, 1490875dd937Sjsg 0x95C7, 1491875dd937Sjsg 0x95C9, 1492875dd937Sjsg 0x95CC, 1493875dd937Sjsg 0x95CD, 1494875dd937Sjsg 0x95CE, 1495875dd937Sjsg 0x95CF, 1496875dd937Sjsg 0x9610, 1497875dd937Sjsg 0x9611, 1498875dd937Sjsg 0x9612, 1499875dd937Sjsg 0x9613, 1500875dd937Sjsg 0x9614, 1501875dd937Sjsg 0x9615, 1502875dd937Sjsg 0x9616, 1503875dd937Sjsg 0x9640, 1504875dd937Sjsg 0x9641, 1505875dd937Sjsg 0x9642, 1506875dd937Sjsg 0x9643, 1507875dd937Sjsg 0x9644, 1508875dd937Sjsg 0x9645, 1509875dd937Sjsg 0x9647, 1510875dd937Sjsg 0x9648, 1511875dd937Sjsg 0x9649, 1512875dd937Sjsg 0x964a, 1513875dd937Sjsg 0x964b, 1514875dd937Sjsg 0x964c, 1515875dd937Sjsg 0x964e, 1516875dd937Sjsg 0x964f, 1517875dd937Sjsg 0x9710, 1518875dd937Sjsg 0x9711, 1519875dd937Sjsg 0x9712, 1520875dd937Sjsg 0x9713, 1521875dd937Sjsg 0x9714, 1522875dd937Sjsg 0x9715, 1523875dd937Sjsg 0x9802, 1524875dd937Sjsg 0x9803, 1525875dd937Sjsg 0x9804, 1526875dd937Sjsg 0x9805, 1527875dd937Sjsg 0x9806, 1528875dd937Sjsg 0x9807, 1529875dd937Sjsg 0x9808, 1530875dd937Sjsg 0x9809, 1531875dd937Sjsg 0x980A, 1532875dd937Sjsg 0x9900, 1533875dd937Sjsg 0x9901, 1534875dd937Sjsg 0x9903, 1535875dd937Sjsg 0x9904, 1536875dd937Sjsg 0x9905, 1537875dd937Sjsg 0x9906, 1538875dd937Sjsg 0x9907, 1539875dd937Sjsg 0x9908, 1540875dd937Sjsg 0x9909, 1541875dd937Sjsg 0x990A, 1542875dd937Sjsg 0x990B, 1543875dd937Sjsg 0x990C, 1544875dd937Sjsg 0x990D, 1545875dd937Sjsg 0x990E, 1546875dd937Sjsg 0x990F, 1547875dd937Sjsg 0x9910, 1548875dd937Sjsg 0x9913, 1549875dd937Sjsg 0x9917, 1550875dd937Sjsg 0x9918, 1551875dd937Sjsg 0x9919, 1552875dd937Sjsg 0x9990, 1553875dd937Sjsg 0x9991, 1554875dd937Sjsg 0x9992, 1555875dd937Sjsg 0x9993, 1556875dd937Sjsg 0x9994, 1557875dd937Sjsg 0x9995, 1558875dd937Sjsg 0x9996, 1559875dd937Sjsg 0x9997, 1560875dd937Sjsg 0x9998, 1561875dd937Sjsg 0x9999, 1562875dd937Sjsg 0x999A, 1563875dd937Sjsg 0x999B, 1564875dd937Sjsg 0x999C, 1565875dd937Sjsg 0x999D, 1566875dd937Sjsg 0x99A0, 1567875dd937Sjsg 0x99A2, 1568875dd937Sjsg 0x99A4, 1569dcca3d91Sjsg /* radeon secondary ids */ 1570dcca3d91Sjsg 0x3171, 1571dcca3d91Sjsg 0x3e70, 1572dcca3d91Sjsg 0x4164, 1573dcca3d91Sjsg 0x4165, 1574dcca3d91Sjsg 0x4166, 1575dcca3d91Sjsg 0x4168, 1576dcca3d91Sjsg 0x4170, 1577dcca3d91Sjsg 0x4171, 1578dcca3d91Sjsg 0x4172, 1579dcca3d91Sjsg 0x4173, 1580dcca3d91Sjsg 0x496e, 1581dcca3d91Sjsg 0x4a69, 1582dcca3d91Sjsg 0x4a6a, 1583dcca3d91Sjsg 0x4a6b, 1584dcca3d91Sjsg 0x4a70, 1585dcca3d91Sjsg 0x4a74, 1586dcca3d91Sjsg 0x4b69, 1587dcca3d91Sjsg 0x4b6b, 1588dcca3d91Sjsg 0x4b6c, 1589dcca3d91Sjsg 0x4c6e, 1590dcca3d91Sjsg 0x4e64, 1591dcca3d91Sjsg 0x4e65, 1592dcca3d91Sjsg 0x4e66, 1593dcca3d91Sjsg 0x4e67, 1594dcca3d91Sjsg 0x4e68, 1595dcca3d91Sjsg 0x4e69, 1596dcca3d91Sjsg 0x4e6a, 1597dcca3d91Sjsg 0x4e71, 1598dcca3d91Sjsg 0x4f73, 1599dcca3d91Sjsg 0x5569, 1600dcca3d91Sjsg 0x556b, 1601dcca3d91Sjsg 0x556d, 1602dcca3d91Sjsg 0x556f, 1603dcca3d91Sjsg 0x5571, 1604dcca3d91Sjsg 0x5854, 1605dcca3d91Sjsg 0x5874, 1606dcca3d91Sjsg 0x5940, 1607dcca3d91Sjsg 0x5941, 1608a0e92bc7Sjsg 0x5b70, 1609dcca3d91Sjsg 0x5b72, 1610dcca3d91Sjsg 0x5b73, 1611dcca3d91Sjsg 0x5b74, 1612dcca3d91Sjsg 0x5b75, 1613dcca3d91Sjsg 0x5d44, 1614dcca3d91Sjsg 0x5d45, 1615dcca3d91Sjsg 0x5d6d, 1616dcca3d91Sjsg 0x5d6f, 1617dcca3d91Sjsg 0x5d72, 1618dcca3d91Sjsg 0x5d77, 1619dcca3d91Sjsg 0x5e6b, 1620dcca3d91Sjsg 0x5e6d, 1621dcca3d91Sjsg 0x7120, 1622dcca3d91Sjsg 0x7124, 1623dcca3d91Sjsg 0x7129, 1624dcca3d91Sjsg 0x712e, 1625dcca3d91Sjsg 0x712f, 1626dcca3d91Sjsg 0x7162, 1627dcca3d91Sjsg 0x7163, 1628dcca3d91Sjsg 0x7166, 1629dcca3d91Sjsg 0x7167, 1630dcca3d91Sjsg 0x7172, 1631dcca3d91Sjsg 0x7173, 1632dcca3d91Sjsg 0x71a0, 1633dcca3d91Sjsg 0x71a1, 1634dcca3d91Sjsg 0x71a3, 1635dcca3d91Sjsg 0x71a7, 1636dcca3d91Sjsg 0x71bb, 1637dcca3d91Sjsg 0x71e0, 1638dcca3d91Sjsg 0x71e1, 1639dcca3d91Sjsg 0x71e2, 1640dcca3d91Sjsg 0x71e6, 1641dcca3d91Sjsg 0x71e7, 1642dcca3d91Sjsg 0x71f2, 1643dcca3d91Sjsg 0x7269, 1644dcca3d91Sjsg 0x726b, 1645dcca3d91Sjsg 0x726e, 1646dcca3d91Sjsg 0x72a0, 1647dcca3d91Sjsg 0x72a8, 1648dcca3d91Sjsg 0x72b1, 1649dcca3d91Sjsg 0x72b3, 1650dcca3d91Sjsg 0x793f, 1651875dd937Sjsg }; 1652875dd937Sjsg 16531bb76ff1Sjsg static const struct pci_device_id pciidlist[] = { 1654fb4d8502Sjsg #ifdef CONFIG_DRM_AMDGPU_SI 1655fb4d8502Sjsg {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1656fb4d8502Sjsg {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1657fb4d8502Sjsg {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1658fb4d8502Sjsg {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1659fb4d8502Sjsg {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1660fb4d8502Sjsg {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1661fb4d8502Sjsg {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1662fb4d8502Sjsg {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1663fb4d8502Sjsg {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1664fb4d8502Sjsg {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1665fb4d8502Sjsg {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666fb4d8502Sjsg {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667fb4d8502Sjsg {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668fb4d8502Sjsg {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1669fb4d8502Sjsg {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1670fb4d8502Sjsg {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1671fb4d8502Sjsg {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1672fb4d8502Sjsg {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1673fb4d8502Sjsg {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1674fb4d8502Sjsg {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1675fb4d8502Sjsg {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1676fb4d8502Sjsg {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1677fb4d8502Sjsg {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1678fb4d8502Sjsg {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1679fb4d8502Sjsg {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1680fb4d8502Sjsg {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1681fb4d8502Sjsg {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1682fb4d8502Sjsg {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1683fb4d8502Sjsg {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1684fb4d8502Sjsg {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1685fb4d8502Sjsg {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1686fb4d8502Sjsg {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1687fb4d8502Sjsg {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1688fb4d8502Sjsg {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1689fb4d8502Sjsg {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1690fb4d8502Sjsg {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1691fb4d8502Sjsg {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1692fb4d8502Sjsg {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1693fb4d8502Sjsg {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694fb4d8502Sjsg {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695fb4d8502Sjsg {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696fb4d8502Sjsg {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1697fb4d8502Sjsg {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1698fb4d8502Sjsg {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1699fb4d8502Sjsg {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1700fb4d8502Sjsg {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1701fb4d8502Sjsg {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1702fb4d8502Sjsg {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1703fb4d8502Sjsg {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1704fb4d8502Sjsg {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1705fb4d8502Sjsg {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1706fb4d8502Sjsg {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1707fb4d8502Sjsg {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1708fb4d8502Sjsg {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1709fb4d8502Sjsg {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1710fb4d8502Sjsg {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711fb4d8502Sjsg {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712fb4d8502Sjsg {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713fb4d8502Sjsg {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714fb4d8502Sjsg {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1715fb4d8502Sjsg {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1716fb4d8502Sjsg {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717fb4d8502Sjsg {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718fb4d8502Sjsg {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1719fb4d8502Sjsg {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720fb4d8502Sjsg {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721fb4d8502Sjsg {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1722fb4d8502Sjsg {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1723fb4d8502Sjsg {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1724fb4d8502Sjsg {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1725fb4d8502Sjsg {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1726fb4d8502Sjsg {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1727fb4d8502Sjsg #endif 1728fb4d8502Sjsg #ifdef CONFIG_DRM_AMDGPU_CIK 1729fb4d8502Sjsg /* Kaveri */ 1730fb4d8502Sjsg {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1731fb4d8502Sjsg {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1732fb4d8502Sjsg {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1733fb4d8502Sjsg {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1734fb4d8502Sjsg {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1735fb4d8502Sjsg {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1736fb4d8502Sjsg {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1737fb4d8502Sjsg {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738fb4d8502Sjsg {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739fb4d8502Sjsg {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740fb4d8502Sjsg {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1741fb4d8502Sjsg {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1742fb4d8502Sjsg {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743fb4d8502Sjsg {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744fb4d8502Sjsg {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745fb4d8502Sjsg {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746fb4d8502Sjsg {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1747fb4d8502Sjsg {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1748fb4d8502Sjsg {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749fb4d8502Sjsg {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1750fb4d8502Sjsg {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1751fb4d8502Sjsg {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752fb4d8502Sjsg /* Bonaire */ 1753fb4d8502Sjsg {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1754fb4d8502Sjsg {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1755fb4d8502Sjsg {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1756fb4d8502Sjsg {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1757fb4d8502Sjsg {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1758fb4d8502Sjsg {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1759fb4d8502Sjsg {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1760fb4d8502Sjsg {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1761fb4d8502Sjsg {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1762fb4d8502Sjsg {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1763fb4d8502Sjsg {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1764fb4d8502Sjsg /* Hawaii */ 1765fb4d8502Sjsg {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1766fb4d8502Sjsg {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1767fb4d8502Sjsg {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1768fb4d8502Sjsg {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1769fb4d8502Sjsg {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1770fb4d8502Sjsg {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1771fb4d8502Sjsg {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1772fb4d8502Sjsg {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1773fb4d8502Sjsg {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1774fb4d8502Sjsg {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1775fb4d8502Sjsg {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776fb4d8502Sjsg {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777fb4d8502Sjsg /* Kabini */ 1778fb4d8502Sjsg {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1779fb4d8502Sjsg {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1780fb4d8502Sjsg {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1781fb4d8502Sjsg {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1782fb4d8502Sjsg {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1783fb4d8502Sjsg {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1784fb4d8502Sjsg {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1785fb4d8502Sjsg {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1786fb4d8502Sjsg {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1787fb4d8502Sjsg {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1788fb4d8502Sjsg {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1789fb4d8502Sjsg {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790fb4d8502Sjsg {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1791fb4d8502Sjsg {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1792fb4d8502Sjsg {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793fb4d8502Sjsg {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1794fb4d8502Sjsg /* mullins */ 1795fb4d8502Sjsg {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1796fb4d8502Sjsg {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1797fb4d8502Sjsg {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1798fb4d8502Sjsg {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1799fb4d8502Sjsg {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1800fb4d8502Sjsg {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1801fb4d8502Sjsg {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1802fb4d8502Sjsg {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1803fb4d8502Sjsg {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1804fb4d8502Sjsg {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1805fb4d8502Sjsg {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806fb4d8502Sjsg {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807fb4d8502Sjsg {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808fb4d8502Sjsg {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809fb4d8502Sjsg {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810fb4d8502Sjsg {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811fb4d8502Sjsg #endif 1812fb4d8502Sjsg /* topaz */ 1813fb4d8502Sjsg {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1814fb4d8502Sjsg {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1815fb4d8502Sjsg {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1816fb4d8502Sjsg {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1817fb4d8502Sjsg {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1818fb4d8502Sjsg /* tonga */ 1819fb4d8502Sjsg {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1820fb4d8502Sjsg {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1821fb4d8502Sjsg {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1822fb4d8502Sjsg {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1823fb4d8502Sjsg {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1824fb4d8502Sjsg {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1825fb4d8502Sjsg {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1826fb4d8502Sjsg {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1827fb4d8502Sjsg {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1828fb4d8502Sjsg /* fiji */ 1829fb4d8502Sjsg {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1830fb4d8502Sjsg {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1831fb4d8502Sjsg /* carrizo */ 1832fb4d8502Sjsg {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1833fb4d8502Sjsg {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1834fb4d8502Sjsg {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1835fb4d8502Sjsg {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1836fb4d8502Sjsg {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1837fb4d8502Sjsg /* stoney */ 1838fb4d8502Sjsg {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1839fb4d8502Sjsg /* Polaris11 */ 1840fb4d8502Sjsg {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1841fb4d8502Sjsg {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1842fb4d8502Sjsg {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1843fb4d8502Sjsg {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1844fb4d8502Sjsg {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1845fb4d8502Sjsg {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1846fb4d8502Sjsg {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1847fb4d8502Sjsg {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1848fb4d8502Sjsg {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1849fb4d8502Sjsg /* Polaris10 */ 1850fb4d8502Sjsg {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1851fb4d8502Sjsg {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1852fb4d8502Sjsg {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1853fb4d8502Sjsg {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1854fb4d8502Sjsg {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1855fb4d8502Sjsg {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1856fb4d8502Sjsg {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1857fb4d8502Sjsg {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1858fb4d8502Sjsg {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1859fb4d8502Sjsg {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1860fb4d8502Sjsg {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861fb4d8502Sjsg {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862fb4d8502Sjsg {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863fb4d8502Sjsg /* Polaris12 */ 1864fb4d8502Sjsg {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1865fb4d8502Sjsg {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1866fb4d8502Sjsg {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1867fb4d8502Sjsg {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1868fb4d8502Sjsg {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1869fb4d8502Sjsg {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1870fb4d8502Sjsg {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1871fb4d8502Sjsg {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1872fb4d8502Sjsg /* VEGAM */ 1873fb4d8502Sjsg {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1874fb4d8502Sjsg {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1875fb4d8502Sjsg {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1876fb4d8502Sjsg /* Vega 10 */ 1877fb4d8502Sjsg {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1878fb4d8502Sjsg {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1879fb4d8502Sjsg {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1880fb4d8502Sjsg {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1881fb4d8502Sjsg {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1882fb4d8502Sjsg {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1883fb4d8502Sjsg {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1884fb4d8502Sjsg {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1885fb4d8502Sjsg {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1886fb4d8502Sjsg {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1887fb4d8502Sjsg {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888fb4d8502Sjsg {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889fb4d8502Sjsg {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890fb4d8502Sjsg {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891fb4d8502Sjsg {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892fb4d8502Sjsg /* Vega 12 */ 1893fb4d8502Sjsg {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1894fb4d8502Sjsg {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1895fb4d8502Sjsg {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1896fb4d8502Sjsg {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1897fb4d8502Sjsg {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1898fb4d8502Sjsg /* Vega 20 */ 1899c349dbc7Sjsg {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1900c349dbc7Sjsg {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1901c349dbc7Sjsg {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1902c349dbc7Sjsg {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1903c349dbc7Sjsg {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1904c349dbc7Sjsg {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1905c349dbc7Sjsg {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1906fb4d8502Sjsg /* Raven */ 1907fb4d8502Sjsg {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 19083ee1c80bSjsg {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1909c349dbc7Sjsg /* Arcturus */ 1910ad8b1aafSjsg {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1911ad8b1aafSjsg {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1912ad8b1aafSjsg {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1913ad8b1aafSjsg {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1914c349dbc7Sjsg /* Navi10 */ 1915c349dbc7Sjsg {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1916c349dbc7Sjsg {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1917c349dbc7Sjsg {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1918c349dbc7Sjsg {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1919c349dbc7Sjsg {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1920c349dbc7Sjsg {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1921ad8b1aafSjsg {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1922c349dbc7Sjsg {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1923c349dbc7Sjsg /* Navi14 */ 1924c349dbc7Sjsg {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1925c349dbc7Sjsg {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1926c349dbc7Sjsg {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1927c349dbc7Sjsg {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1928c349dbc7Sjsg 1929c349dbc7Sjsg /* Renoir */ 19302ea8292cSjsg {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1931c349dbc7Sjsg {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1932ad8b1aafSjsg {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1933ad8b1aafSjsg {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1934c349dbc7Sjsg 1935c349dbc7Sjsg /* Navi12 */ 1936ad8b1aafSjsg {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1937ad8b1aafSjsg {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1938ad8b1aafSjsg 1939ad8b1aafSjsg /* Sienna_Cichlid */ 1940ad8b1aafSjsg {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1941ee4f4e21Sjsg {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1942ad8b1aafSjsg {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1943ad8b1aafSjsg {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 194452ec2841Sjsg {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 194552ec2841Sjsg {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 194652ec2841Sjsg {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1947ad8b1aafSjsg {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 194852ec2841Sjsg {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 194952ec2841Sjsg {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1950ad8b1aafSjsg {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951ad8b1aafSjsg {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952ad8b1aafSjsg {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953fb4d8502Sjsg 19545ca02815Sjsg /* Yellow Carp */ 19555ca02815Sjsg {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 19565ca02815Sjsg {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 19575ca02815Sjsg 19585ca02815Sjsg /* Navy_Flounder */ 19595ca02815Sjsg {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19605ca02815Sjsg {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19615ca02815Sjsg {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19625ca02815Sjsg {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19635ca02815Sjsg {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19645ca02815Sjsg {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19655ca02815Sjsg {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19665ca02815Sjsg {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19675ca02815Sjsg {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 19685ca02815Sjsg 19695ca02815Sjsg /* DIMGREY_CAVEFISH */ 19705ca02815Sjsg {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19715ca02815Sjsg {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19725ca02815Sjsg {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19735ca02815Sjsg {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19745ca02815Sjsg {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19755ca02815Sjsg {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19765ca02815Sjsg {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19775ca02815Sjsg {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19785ca02815Sjsg {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19795ca02815Sjsg {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19805ca02815Sjsg {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19815ca02815Sjsg {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 19825ca02815Sjsg 19835ca02815Sjsg /* Aldebaran */ 19841bb76ff1Sjsg {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 19851bb76ff1Sjsg {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 19861bb76ff1Sjsg {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 19871bb76ff1Sjsg {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 19885ca02815Sjsg 19895ca02815Sjsg /* CYAN_SKILLFISH */ 19905ca02815Sjsg {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 19911bb76ff1Sjsg {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 19925ca02815Sjsg 19935ca02815Sjsg /* BEIGE_GOBY */ 19945ca02815Sjsg {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 19955ca02815Sjsg {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 19965ca02815Sjsg {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 19975ca02815Sjsg {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1998b909cdd8Sjsg {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 19995ca02815Sjsg {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 20005ca02815Sjsg 20011bb76ff1Sjsg { PCI_DEVICE(0x1002, PCI_ANY_ID), 20021bb76ff1Sjsg .class = PCI_CLASS_DISPLAY_VGA << 8, 20031bb76ff1Sjsg .class_mask = 0xffffff, 20041bb76ff1Sjsg .driver_data = CHIP_IP_DISCOVERY }, 20051bb76ff1Sjsg 20061bb76ff1Sjsg { PCI_DEVICE(0x1002, PCI_ANY_ID), 20071bb76ff1Sjsg .class = PCI_CLASS_DISPLAY_OTHER << 8, 20081bb76ff1Sjsg .class_mask = 0xffffff, 20091bb76ff1Sjsg .driver_data = CHIP_IP_DISCOVERY }, 20101bb76ff1Sjsg 2011f005ef32Sjsg { PCI_DEVICE(0x1002, PCI_ANY_ID), 2012f005ef32Sjsg .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8, 2013f005ef32Sjsg .class_mask = 0xffffff, 2014f005ef32Sjsg .driver_data = CHIP_IP_DISCOVERY }, 2015f005ef32Sjsg 2016fb4d8502Sjsg {0, 0, 0} 2017fb4d8502Sjsg }; 2018fb4d8502Sjsg 2019fb4d8502Sjsg MODULE_DEVICE_TABLE(pci, pciidlist); 2020fb4d8502Sjsg 20211bb76ff1Sjsg static const struct drm_driver amdgpu_kms_driver; 20225ca02815Sjsg 20231bb76ff1Sjsg static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 20245ca02815Sjsg { 20251bb76ff1Sjsg STUB(); 20261bb76ff1Sjsg #ifdef notyet 20271bb76ff1Sjsg struct pci_dev *p = NULL; 20281bb76ff1Sjsg int i; 20295ca02815Sjsg 20301bb76ff1Sjsg /* 0 - GPU 20311bb76ff1Sjsg * 1 - audio 20321bb76ff1Sjsg * 2 - USB 20331bb76ff1Sjsg * 3 - UCSI 20341bb76ff1Sjsg */ 20351bb76ff1Sjsg for (i = 1; i < 4; i++) { 20361bb76ff1Sjsg p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 20371bb76ff1Sjsg adev->pdev->bus->number, i); 20381bb76ff1Sjsg if (p) { 20391bb76ff1Sjsg pm_runtime_get_sync(&p->dev); 20401bb76ff1Sjsg pm_runtime_mark_last_busy(&p->dev); 20411bb76ff1Sjsg pm_runtime_put_autosuspend(&p->dev); 20421bb76ff1Sjsg pci_dev_put(p); 20431bb76ff1Sjsg } 20441bb76ff1Sjsg } 20455ca02815Sjsg #endif 20465ca02815Sjsg } 2047fb4d8502Sjsg 2048fb4d8502Sjsg #ifdef notyet 2049fb4d8502Sjsg static int amdgpu_pci_probe(struct pci_dev *pdev, 2050fb4d8502Sjsg const struct pci_device_id *ent) 2051fb4d8502Sjsg { 2052ad8b1aafSjsg struct drm_device *ddev; 2053c349dbc7Sjsg struct amdgpu_device *adev; 2054fb4d8502Sjsg unsigned long flags = ent->driver_data; 2055875dd937Sjsg int ret, retry = 0, i; 2056fb4d8502Sjsg bool supports_atomic = false; 2057adba1814Sjsg 2058875dd937Sjsg /* skip devices which are owned by radeon */ 2059875dd937Sjsg for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2060875dd937Sjsg if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2061875dd937Sjsg return -ENODEV; 2062875dd937Sjsg } 2063875dd937Sjsg 20641bb76ff1Sjsg if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 20651bb76ff1Sjsg amdgpu_aspm = 0; 20661bb76ff1Sjsg 20675ca02815Sjsg if (amdgpu_virtual_display || 2068fb4d8502Sjsg amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2069fb4d8502Sjsg supports_atomic = true; 2070fb4d8502Sjsg 2071fb4d8502Sjsg if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2072fb4d8502Sjsg DRM_INFO("This hardware requires experimental hardware support.\n" 2073fb4d8502Sjsg "See modparam exp_hw_support\n"); 2074fb4d8502Sjsg return -ENODEV; 2075fb4d8502Sjsg } 2076e10e7b68Sjsg /* differentiate between P10 and P11 asics with the same DID */ 2077e10e7b68Sjsg if (pdev->device == 0x67FF && 2078e10e7b68Sjsg (pdev->revision == 0xE3 || 2079e10e7b68Sjsg pdev->revision == 0xE7 || 2080e10e7b68Sjsg pdev->revision == 0xF3 || 2081e10e7b68Sjsg pdev->revision == 0xF7)) { 2082e10e7b68Sjsg flags &= ~AMD_ASIC_MASK; 2083e10e7b68Sjsg flags |= CHIP_POLARIS10; 2084e10e7b68Sjsg } 2085fb4d8502Sjsg 2086ad8b1aafSjsg /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2087ad8b1aafSjsg * however, SME requires an indirect IOMMU mapping because the encryption 2088ad8b1aafSjsg * bit is beyond the DMA mask of the chip. 2089ad8b1aafSjsg */ 20901bb76ff1Sjsg if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 20911bb76ff1Sjsg ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2092ad8b1aafSjsg dev_info(&pdev->dev, 2093ad8b1aafSjsg "SME is not compatible with RAVEN\n"); 2094ad8b1aafSjsg return -ENOTSUPP; 2095ad8b1aafSjsg } 2096ad8b1aafSjsg 2097069b773dSjsg #ifdef CONFIG_DRM_AMDGPU_SI 2098069b773dSjsg if (!amdgpu_si_support) { 2099069b773dSjsg switch (flags & AMD_ASIC_MASK) { 2100069b773dSjsg case CHIP_TAHITI: 2101069b773dSjsg case CHIP_PITCAIRN: 2102069b773dSjsg case CHIP_VERDE: 2103069b773dSjsg case CHIP_OLAND: 2104069b773dSjsg case CHIP_HAINAN: 2105069b773dSjsg dev_info(&pdev->dev, 2106069b773dSjsg "SI support provided by radeon.\n"); 2107069b773dSjsg dev_info(&pdev->dev, 2108069b773dSjsg "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2109069b773dSjsg ); 2110069b773dSjsg return -ENODEV; 2111069b773dSjsg } 2112069b773dSjsg } 2113069b773dSjsg #endif 2114069b773dSjsg #ifdef CONFIG_DRM_AMDGPU_CIK 2115069b773dSjsg if (!amdgpu_cik_support) { 2116069b773dSjsg switch (flags & AMD_ASIC_MASK) { 2117069b773dSjsg case CHIP_KAVERI: 2118069b773dSjsg case CHIP_BONAIRE: 2119069b773dSjsg case CHIP_HAWAII: 2120069b773dSjsg case CHIP_KABINI: 2121069b773dSjsg case CHIP_MULLINS: 2122069b773dSjsg dev_info(&pdev->dev, 2123069b773dSjsg "CIK support provided by radeon.\n"); 2124069b773dSjsg dev_info(&pdev->dev, 2125069b773dSjsg "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2126069b773dSjsg ); 2127069b773dSjsg return -ENODEV; 2128069b773dSjsg } 2129069b773dSjsg } 2130069b773dSjsg #endif 2131069b773dSjsg 21325ca02815Sjsg adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2133ad8b1aafSjsg if (IS_ERR(adev)) 2134ad8b1aafSjsg return PTR_ERR(adev); 2135ad8b1aafSjsg 2136ad8b1aafSjsg adev->dev = &pdev->dev; 2137ad8b1aafSjsg adev->pdev = pdev; 2138ad8b1aafSjsg ddev = adev_to_drm(adev); 2139fb4d8502Sjsg 2140c349dbc7Sjsg if (!supports_atomic) 2141ad8b1aafSjsg ddev->driver_features &= ~DRIVER_ATOMIC; 2142c349dbc7Sjsg 2143fb4d8502Sjsg ret = pci_enable_device(pdev); 2144fb4d8502Sjsg if (ret) 2145ad8b1aafSjsg return ret; 2146fb4d8502Sjsg 2147ad8b1aafSjsg pci_set_drvdata(pdev, ddev); 2148fb4d8502Sjsg 2149e10e7b68Sjsg ret = amdgpu_driver_load_kms(adev, flags); 2150ad8b1aafSjsg if (ret) 2151ad8b1aafSjsg goto err_pci; 2152c349dbc7Sjsg 2153fb4d8502Sjsg retry_init: 2154e10e7b68Sjsg ret = drm_dev_register(ddev, flags); 2155fb4d8502Sjsg if (ret == -EAGAIN && ++retry <= 3) { 2156fb4d8502Sjsg DRM_INFO("retry init %d\n", retry); 2157fb4d8502Sjsg /* Don't request EX mode too frequently which is attacking */ 2158fb4d8502Sjsg drm_msleep(5000); 2159fb4d8502Sjsg goto retry_init; 2160ad8b1aafSjsg } else if (ret) { 2161fb4d8502Sjsg goto err_pci; 2162ad8b1aafSjsg } 2163fb4d8502Sjsg 2164f005ef32Sjsg ret = amdgpu_xcp_dev_register(adev, ent); 2165f005ef32Sjsg if (ret) 2166f005ef32Sjsg goto err_pci; 2167f005ef32Sjsg 21681bb76ff1Sjsg /* 21691bb76ff1Sjsg * 1. don't init fbdev on hw without DCE 21701bb76ff1Sjsg * 2. don't init fbdev if there are no connectors 21711bb76ff1Sjsg */ 21721bb76ff1Sjsg if (adev->mode_info.mode_config_initialized && 21731bb76ff1Sjsg !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 21741bb76ff1Sjsg /* select 8 bpp console on low vram cards */ 21751bb76ff1Sjsg if (adev->gmc.real_vram_size <= (32*1024*1024)) 21761bb76ff1Sjsg drm_fbdev_generic_setup(adev_to_drm(adev), 8); 21771bb76ff1Sjsg else 21781bb76ff1Sjsg drm_fbdev_generic_setup(adev_to_drm(adev), 32); 21791bb76ff1Sjsg } 21801bb76ff1Sjsg 2181c349dbc7Sjsg ret = amdgpu_debugfs_init(adev); 2182c349dbc7Sjsg if (ret) 2183c349dbc7Sjsg DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2184c349dbc7Sjsg 21851bb76ff1Sjsg if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 21861bb76ff1Sjsg /* only need to skip on ATPX */ 21871bb76ff1Sjsg if (amdgpu_device_supports_px(ddev)) 21881bb76ff1Sjsg dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 21891bb76ff1Sjsg /* we want direct complete for BOCO */ 21901bb76ff1Sjsg if (amdgpu_device_supports_boco(ddev)) 21911bb76ff1Sjsg dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 21921bb76ff1Sjsg DPM_FLAG_SMART_SUSPEND | 21931bb76ff1Sjsg DPM_FLAG_MAY_SKIP_RESUME); 21941bb76ff1Sjsg pm_runtime_use_autosuspend(ddev->dev); 21951bb76ff1Sjsg pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 21961bb76ff1Sjsg 21971bb76ff1Sjsg pm_runtime_allow(ddev->dev); 21981bb76ff1Sjsg 21991bb76ff1Sjsg pm_runtime_mark_last_busy(ddev->dev); 22001bb76ff1Sjsg pm_runtime_put_autosuspend(ddev->dev); 22011bb76ff1Sjsg 220254f9414eSjsg pci_wake_from_d3(pdev, TRUE); 220354f9414eSjsg 22041bb76ff1Sjsg /* 22051bb76ff1Sjsg * For runpm implemented via BACO, PMFW will handle the 22061bb76ff1Sjsg * timing for BACO in and out: 22071bb76ff1Sjsg * - put ASIC into BACO state only when both video and 22081bb76ff1Sjsg * audio functions are in D3 state. 22091bb76ff1Sjsg * - pull ASIC out of BACO state when either video or 22101bb76ff1Sjsg * audio function is in D0 state. 22111bb76ff1Sjsg * Also, at startup, PMFW assumes both functions are in 22121bb76ff1Sjsg * D0 state. 22131bb76ff1Sjsg * 22141bb76ff1Sjsg * So if snd driver was loaded prior to amdgpu driver 22151bb76ff1Sjsg * and audio function was put into D3 state, there will 22161bb76ff1Sjsg * be no PMFW-aware D-state transition(D0->D3) on runpm 22171bb76ff1Sjsg * suspend. Thus the BACO will be not correctly kicked in. 22181bb76ff1Sjsg * 22191bb76ff1Sjsg * Via amdgpu_get_secondary_funcs(), the audio dev is put 22201bb76ff1Sjsg * into D0 state. Then there will be a PMFW-aware D-state 22211bb76ff1Sjsg * transition(D0->D3) on runpm suspend. 22221bb76ff1Sjsg */ 22231bb76ff1Sjsg if (amdgpu_device_supports_baco(ddev) && 22241bb76ff1Sjsg !(adev->flags & AMD_IS_APU) && 22251bb76ff1Sjsg (adev->asic_type >= CHIP_NAVI10)) 22261bb76ff1Sjsg amdgpu_get_secondary_funcs(adev); 22271bb76ff1Sjsg } 22281bb76ff1Sjsg 2229fb4d8502Sjsg return 0; 2230fb4d8502Sjsg 2231fb4d8502Sjsg err_pci: 2232fb4d8502Sjsg pci_disable_device(pdev); 2233fb4d8502Sjsg return ret; 2234fb4d8502Sjsg } 2235fb4d8502Sjsg 2236fb4d8502Sjsg static void 2237fb4d8502Sjsg amdgpu_pci_remove(struct pci_dev *pdev) 2238fb4d8502Sjsg { 2239fb4d8502Sjsg struct drm_device *dev = pci_get_drvdata(pdev); 22401bb76ff1Sjsg struct amdgpu_device *adev = drm_to_adev(dev); 22411bb76ff1Sjsg 2242f005ef32Sjsg amdgpu_xcp_dev_unplug(adev); 2243e63de9fbSjsg drm_dev_unplug(dev); 2244e63de9fbSjsg 22451bb76ff1Sjsg if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 22461bb76ff1Sjsg pm_runtime_get_sync(dev->dev); 22471bb76ff1Sjsg pm_runtime_forbid(dev->dev); 22481bb76ff1Sjsg } 22491bb76ff1Sjsg 22501bb76ff1Sjsg if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 22511bb76ff1Sjsg !amdgpu_sriov_vf(adev)) { 22521bb76ff1Sjsg bool need_to_reset_gpu = false; 22531bb76ff1Sjsg 22541bb76ff1Sjsg if (adev->gmc.xgmi.num_physical_nodes > 1) { 22551bb76ff1Sjsg struct amdgpu_hive_info *hive; 22561bb76ff1Sjsg 22571bb76ff1Sjsg hive = amdgpu_get_xgmi_hive(adev); 22581bb76ff1Sjsg if (hive->device_remove_count == 0) 22591bb76ff1Sjsg need_to_reset_gpu = true; 22601bb76ff1Sjsg hive->device_remove_count++; 22611bb76ff1Sjsg amdgpu_put_xgmi_hive(hive); 22621bb76ff1Sjsg } else { 22631bb76ff1Sjsg need_to_reset_gpu = true; 22641bb76ff1Sjsg } 22651bb76ff1Sjsg 22661bb76ff1Sjsg /* Workaround for ASICs need to reset SMU. 22671bb76ff1Sjsg * Called only when the first device is removed. 22681bb76ff1Sjsg */ 22691bb76ff1Sjsg if (need_to_reset_gpu) { 22701bb76ff1Sjsg struct amdgpu_reset_context reset_context; 22711bb76ff1Sjsg 22721bb76ff1Sjsg adev->shutdown = true; 22731bb76ff1Sjsg memset(&reset_context, 0, sizeof(reset_context)); 22741bb76ff1Sjsg reset_context.method = AMD_RESET_METHOD_NONE; 22751bb76ff1Sjsg reset_context.reset_req_dev = adev; 22761bb76ff1Sjsg set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 22771bb76ff1Sjsg set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 22781bb76ff1Sjsg amdgpu_device_gpu_recover(adev, NULL, &reset_context); 22791bb76ff1Sjsg } 22801bb76ff1Sjsg } 22811bb76ff1Sjsg 22821bb76ff1Sjsg amdgpu_driver_unload_kms(dev); 2283fb4d8502Sjsg 22845ca02815Sjsg /* 22855ca02815Sjsg * Flush any in flight DMA operations from device. 22865ca02815Sjsg * Clear the Bus Master Enable bit and then wait on the PCIe Device 22875ca02815Sjsg * StatusTransactions Pending bit. 22885ca02815Sjsg */ 2289fb4d8502Sjsg pci_disable_device(pdev); 22905ca02815Sjsg pci_wait_for_pending_transaction(pdev); 2291fb4d8502Sjsg } 2292fb4d8502Sjsg 2293fb4d8502Sjsg static void 2294fb4d8502Sjsg amdgpu_pci_shutdown(struct pci_dev *pdev) 2295fb4d8502Sjsg { 2296fb4d8502Sjsg struct drm_device *dev = pci_get_drvdata(pdev); 2297ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(dev); 2298fb4d8502Sjsg 2299c349dbc7Sjsg if (amdgpu_ras_intr_triggered()) 2300c349dbc7Sjsg return; 2301c349dbc7Sjsg 2302fb4d8502Sjsg /* if we are running in a VM, make sure the device 2303fb4d8502Sjsg * torn down properly on reboot/shutdown. 2304fb4d8502Sjsg * unfortunately we can't detect certain 2305fb4d8502Sjsg * hypervisors so just do this all the time. 2306fb4d8502Sjsg */ 2307ad8b1aafSjsg if (!amdgpu_passthrough(adev)) 2308c349dbc7Sjsg adev->mp1_state = PP_MP1_STATE_UNLOAD; 2309fb4d8502Sjsg amdgpu_device_ip_suspend(adev); 2310c349dbc7Sjsg adev->mp1_state = PP_MP1_STATE_NONE; 2311fb4d8502Sjsg } 23125ca02815Sjsg #endif 23135ca02815Sjsg 23145ca02815Sjsg /** 23155ca02815Sjsg * amdgpu_drv_delayed_reset_work_handler - work handler for reset 23165ca02815Sjsg * 23175ca02815Sjsg * @work: work_struct. 23185ca02815Sjsg */ 23195ca02815Sjsg static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 23205ca02815Sjsg { 23215ca02815Sjsg struct list_head device_list; 23225ca02815Sjsg struct amdgpu_device *adev; 23235ca02815Sjsg int i, r; 23245ca02815Sjsg struct amdgpu_reset_context reset_context; 23255ca02815Sjsg 23265ca02815Sjsg memset(&reset_context, 0, sizeof(reset_context)); 23275ca02815Sjsg 23285ca02815Sjsg mutex_lock(&mgpu_info.mutex); 23295ca02815Sjsg if (mgpu_info.pending_reset == true) { 23305ca02815Sjsg mutex_unlock(&mgpu_info.mutex); 23315ca02815Sjsg return; 23325ca02815Sjsg } 23335ca02815Sjsg mgpu_info.pending_reset = true; 23345ca02815Sjsg mutex_unlock(&mgpu_info.mutex); 23355ca02815Sjsg 23365ca02815Sjsg /* Use a common context, just need to make sure full reset is done */ 23375ca02815Sjsg reset_context.method = AMD_RESET_METHOD_NONE; 23385ca02815Sjsg set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 23395ca02815Sjsg 23405ca02815Sjsg for (i = 0; i < mgpu_info.num_dgpu; i++) { 23415ca02815Sjsg adev = mgpu_info.gpu_ins[i].adev; 23425ca02815Sjsg reset_context.reset_req_dev = adev; 23435ca02815Sjsg r = amdgpu_device_pre_asic_reset(adev, &reset_context); 23445ca02815Sjsg if (r) { 23455ca02815Sjsg dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 23465ca02815Sjsg r, adev_to_drm(adev)->unique); 23475ca02815Sjsg } 23485ca02815Sjsg if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 23495ca02815Sjsg r = -EALREADY; 23505ca02815Sjsg } 23515ca02815Sjsg for (i = 0; i < mgpu_info.num_dgpu; i++) { 23525ca02815Sjsg adev = mgpu_info.gpu_ins[i].adev; 23535ca02815Sjsg flush_work(&adev->xgmi_reset_work); 23545ca02815Sjsg adev->gmc.xgmi.pending_reset = false; 23555ca02815Sjsg } 23565ca02815Sjsg 23575ca02815Sjsg /* reset function will rebuild the xgmi hive info , clear it now */ 23585ca02815Sjsg for (i = 0; i < mgpu_info.num_dgpu; i++) 23595ca02815Sjsg amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 23605ca02815Sjsg 23615ca02815Sjsg INIT_LIST_HEAD(&device_list); 23625ca02815Sjsg 23635ca02815Sjsg for (i = 0; i < mgpu_info.num_dgpu; i++) 23645ca02815Sjsg list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 23655ca02815Sjsg 23665ca02815Sjsg /* unregister the GPU first, reset function will add them back */ 23675ca02815Sjsg list_for_each_entry(adev, &device_list, reset_list) 23685ca02815Sjsg amdgpu_unregister_gpu_instance(adev); 23695ca02815Sjsg 23705ca02815Sjsg /* Use a common context, just need to make sure full reset is done */ 23715ca02815Sjsg set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 23725ca02815Sjsg r = amdgpu_do_asic_reset(&device_list, &reset_context); 23735ca02815Sjsg 23745ca02815Sjsg if (r) { 23755ca02815Sjsg DRM_ERROR("reinit gpus failure"); 23765ca02815Sjsg return; 23775ca02815Sjsg } 23785ca02815Sjsg for (i = 0; i < mgpu_info.num_dgpu; i++) { 23795ca02815Sjsg adev = mgpu_info.gpu_ins[i].adev; 23805ca02815Sjsg if (!adev->kfd.init_complete) 23815ca02815Sjsg amdgpu_amdkfd_device_init(adev); 23825ca02815Sjsg amdgpu_ttm_set_buffer_funcs_status(adev, true); 23835ca02815Sjsg } 23845ca02815Sjsg } 23855ca02815Sjsg 23865ca02815Sjsg static int amdgpu_pmops_prepare(struct device *dev) 23875ca02815Sjsg { 23885ca02815Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 238924943abfSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 23905ca02815Sjsg 23915ca02815Sjsg /* Return a positive number here so 23925ca02815Sjsg * DPM_FLAG_SMART_SUSPEND works properly 23935ca02815Sjsg */ 239436668b15Sjsg if (amdgpu_device_supports_boco(drm_dev) && 239536668b15Sjsg pm_runtime_suspended(dev)) 239636668b15Sjsg return 1; 23975ca02815Sjsg 239824943abfSjsg /* if we will not support s3 or s2i for the device 239924943abfSjsg * then skip suspend 240024943abfSjsg */ 240124943abfSjsg if (!amdgpu_acpi_is_s0ix_active(adev) && 240224943abfSjsg !amdgpu_acpi_is_s3_active(adev)) 240324943abfSjsg return 1; 240424943abfSjsg 240536668b15Sjsg return amdgpu_device_prepare(drm_dev); 24065ca02815Sjsg } 24075ca02815Sjsg 24085ca02815Sjsg static void amdgpu_pmops_complete(struct device *dev) 24095ca02815Sjsg { 24105ca02815Sjsg /* nothing to do */ 24115ca02815Sjsg } 2412fb4d8502Sjsg 2413fb4d8502Sjsg static int amdgpu_pmops_suspend(struct device *dev) 2414fb4d8502Sjsg { 2415c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 24165ca02815Sjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2417fb4d8502Sjsg 24182ef2b99cSjsg adev->suspend_complete = false; 24195ca02815Sjsg if (amdgpu_acpi_is_s0ix_active(adev)) 24205ca02815Sjsg adev->in_s0ix = true; 2421d87ad1f5Sjsg else if (amdgpu_acpi_is_s3_active(adev)) 24225ca02815Sjsg adev->in_s3 = true; 2423d87ad1f5Sjsg if (!adev->in_s0ix && !adev->in_s3) 2424d87ad1f5Sjsg return 0; 2425777c88bfSjsg return amdgpu_device_suspend(drm_dev, true); 2426777c88bfSjsg } 2427777c88bfSjsg 2428777c88bfSjsg static int amdgpu_pmops_suspend_noirq(struct device *dev) 2429777c88bfSjsg { 2430777c88bfSjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2431777c88bfSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2432777c88bfSjsg 24332ef2b99cSjsg adev->suspend_complete = true; 243495c2fe60Sjsg if (amdgpu_acpi_should_gpu_reset(adev)) 2435777c88bfSjsg return amdgpu_asic_reset(adev); 2436777c88bfSjsg 2437777c88bfSjsg return 0; 2438fb4d8502Sjsg } 2439fb4d8502Sjsg 2440fb4d8502Sjsg static int amdgpu_pmops_resume(struct device *dev) 2441fb4d8502Sjsg { 2442c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 24435ca02815Sjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 24445ca02815Sjsg int r; 2445fb4d8502Sjsg 2446d87ad1f5Sjsg if (!adev->in_s0ix && !adev->in_s3) 2447d87ad1f5Sjsg return 0; 2448d87ad1f5Sjsg 24491bb76ff1Sjsg /* Avoids registers access if device is physically gone */ 24501bb76ff1Sjsg if (!pci_device_is_present(adev->pdev)) 24511bb76ff1Sjsg adev->no_hw_access = true; 24521bb76ff1Sjsg 24535ca02815Sjsg r = amdgpu_device_resume(drm_dev, true); 24545ca02815Sjsg if (amdgpu_acpi_is_s0ix_active(adev)) 24555ca02815Sjsg adev->in_s0ix = false; 2456003ac5f7Sjsg else 2457003ac5f7Sjsg adev->in_s3 = false; 24585ca02815Sjsg return r; 2459fb4d8502Sjsg } 2460fb4d8502Sjsg 2461fb4d8502Sjsg static int amdgpu_pmops_freeze(struct device *dev) 2462fb4d8502Sjsg { 2463c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2464ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2465c349dbc7Sjsg int r; 2466fb4d8502Sjsg 24675ca02815Sjsg adev->in_s4 = true; 2468c349dbc7Sjsg r = amdgpu_device_suspend(drm_dev, true); 24695ca02815Sjsg adev->in_s4 = false; 2470c349dbc7Sjsg if (r) 2471c349dbc7Sjsg return r; 2472d65446bcSjsg 2473d65446bcSjsg if (amdgpu_acpi_should_gpu_reset(adev)) 2474c349dbc7Sjsg return amdgpu_asic_reset(adev); 2475d65446bcSjsg return 0; 2476fb4d8502Sjsg } 2477fb4d8502Sjsg 24781046ef31Skettenis #ifdef notyet 24791046ef31Skettenis 2480fb4d8502Sjsg static int amdgpu_pmops_thaw(struct device *dev) 2481fb4d8502Sjsg { 2482c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2483fb4d8502Sjsg 2484c349dbc7Sjsg return amdgpu_device_resume(drm_dev, true); 2485fb4d8502Sjsg } 2486fb4d8502Sjsg 2487fb4d8502Sjsg static int amdgpu_pmops_poweroff(struct device *dev) 2488fb4d8502Sjsg { 2489c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2490fb4d8502Sjsg 2491c349dbc7Sjsg return amdgpu_device_suspend(drm_dev, true); 2492fb4d8502Sjsg } 2493fb4d8502Sjsg 24941046ef31Skettenis #endif 24951046ef31Skettenis 2496fb4d8502Sjsg static int amdgpu_pmops_restore(struct device *dev) 2497fb4d8502Sjsg { 2498c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2499fb4d8502Sjsg 2500c349dbc7Sjsg return amdgpu_device_resume(drm_dev, true); 2501fb4d8502Sjsg } 2502fb4d8502Sjsg 25031046ef31Skettenis #ifdef notyet 25041046ef31Skettenis 25051bb76ff1Sjsg static int amdgpu_runtime_idle_check_display(struct device *dev) 25061bb76ff1Sjsg { 25071bb76ff1Sjsg struct pci_dev *pdev = to_pci_dev(dev); 25081bb76ff1Sjsg struct drm_device *drm_dev = pci_get_drvdata(pdev); 25091bb76ff1Sjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 25101bb76ff1Sjsg 25111bb76ff1Sjsg if (adev->mode_info.num_crtc) { 25121bb76ff1Sjsg struct drm_connector *list_connector; 25131bb76ff1Sjsg struct drm_connector_list_iter iter; 25141bb76ff1Sjsg int ret = 0; 25151bb76ff1Sjsg 2516f005ef32Sjsg if (amdgpu_runtime_pm != -2) { 25171bb76ff1Sjsg /* XXX: Return busy if any displays are connected to avoid 25181bb76ff1Sjsg * possible display wakeups after runtime resume due to 25191bb76ff1Sjsg * hotplug events in case any displays were connected while 25201bb76ff1Sjsg * the GPU was in suspend. Remove this once that is fixed. 25211bb76ff1Sjsg */ 25221bb76ff1Sjsg mutex_lock(&drm_dev->mode_config.mutex); 25231bb76ff1Sjsg drm_connector_list_iter_begin(drm_dev, &iter); 25241bb76ff1Sjsg drm_for_each_connector_iter(list_connector, &iter) { 25251bb76ff1Sjsg if (list_connector->status == connector_status_connected) { 25261bb76ff1Sjsg ret = -EBUSY; 25271bb76ff1Sjsg break; 25281bb76ff1Sjsg } 25291bb76ff1Sjsg } 25301bb76ff1Sjsg drm_connector_list_iter_end(&iter); 25311bb76ff1Sjsg mutex_unlock(&drm_dev->mode_config.mutex); 25321bb76ff1Sjsg 25331bb76ff1Sjsg if (ret) 25341bb76ff1Sjsg return ret; 2535f005ef32Sjsg } 25361bb76ff1Sjsg 2537f005ef32Sjsg if (adev->dc_enabled) { 25381bb76ff1Sjsg struct drm_crtc *crtc; 25391bb76ff1Sjsg 25401bb76ff1Sjsg drm_for_each_crtc(crtc, drm_dev) { 25411bb76ff1Sjsg drm_modeset_lock(&crtc->mutex, NULL); 25421bb76ff1Sjsg if (crtc->state->active) 25431bb76ff1Sjsg ret = -EBUSY; 25441bb76ff1Sjsg drm_modeset_unlock(&crtc->mutex); 25451bb76ff1Sjsg if (ret < 0) 25461bb76ff1Sjsg break; 25471bb76ff1Sjsg } 25481bb76ff1Sjsg } else { 25491bb76ff1Sjsg mutex_lock(&drm_dev->mode_config.mutex); 25501bb76ff1Sjsg drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 25511bb76ff1Sjsg 25521bb76ff1Sjsg drm_connector_list_iter_begin(drm_dev, &iter); 25531bb76ff1Sjsg drm_for_each_connector_iter(list_connector, &iter) { 25541bb76ff1Sjsg if (list_connector->dpms == DRM_MODE_DPMS_ON) { 25551bb76ff1Sjsg ret = -EBUSY; 25561bb76ff1Sjsg break; 25571bb76ff1Sjsg } 25581bb76ff1Sjsg } 25591bb76ff1Sjsg 25601bb76ff1Sjsg drm_connector_list_iter_end(&iter); 25611bb76ff1Sjsg 25621bb76ff1Sjsg drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 25631bb76ff1Sjsg mutex_unlock(&drm_dev->mode_config.mutex); 25641bb76ff1Sjsg } 25651bb76ff1Sjsg if (ret) 25661bb76ff1Sjsg return ret; 25671bb76ff1Sjsg } 25681bb76ff1Sjsg 25691bb76ff1Sjsg return 0; 25701bb76ff1Sjsg } 25711bb76ff1Sjsg 2572fb4d8502Sjsg static int amdgpu_pmops_runtime_suspend(struct device *dev) 2573fb4d8502Sjsg { 2574fb4d8502Sjsg struct pci_dev *pdev = to_pci_dev(dev); 2575fb4d8502Sjsg struct drm_device *drm_dev = pci_get_drvdata(pdev); 2576ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2577c349dbc7Sjsg int ret, i; 2578fb4d8502Sjsg 25791bb76ff1Sjsg if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2580fb4d8502Sjsg pm_runtime_forbid(dev); 2581fb4d8502Sjsg return -EBUSY; 2582fb4d8502Sjsg } 2583fb4d8502Sjsg 25841bb76ff1Sjsg ret = amdgpu_runtime_idle_check_display(dev); 25851bb76ff1Sjsg if (ret) 25861bb76ff1Sjsg return ret; 25871bb76ff1Sjsg 2588c349dbc7Sjsg /* wait for all rings to drain before suspending */ 2589c349dbc7Sjsg for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2590c349dbc7Sjsg struct amdgpu_ring *ring = adev->rings[i]; 2591f005ef32Sjsg 2592c349dbc7Sjsg if (ring && ring->sched.ready) { 2593c349dbc7Sjsg ret = amdgpu_fence_wait_empty(ring); 2594c349dbc7Sjsg if (ret) 2595c349dbc7Sjsg return -EBUSY; 2596c349dbc7Sjsg } 2597c349dbc7Sjsg } 2598c349dbc7Sjsg 2599c349dbc7Sjsg adev->in_runpm = true; 26005ca02815Sjsg if (amdgpu_device_supports_px(drm_dev)) 2601fb4d8502Sjsg drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 26025ca02815Sjsg 26035ca02815Sjsg /* 26045ca02815Sjsg * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 26055ca02815Sjsg * proper cleanups and put itself into a state ready for PNP. That 26065ca02815Sjsg * can address some random resuming failure observed on BOCO capable 26075ca02815Sjsg * platforms. 26085ca02815Sjsg * TODO: this may be also needed for PX capable platform. 26095ca02815Sjsg */ 26105ca02815Sjsg if (amdgpu_device_supports_boco(drm_dev)) 26115ca02815Sjsg adev->mp1_state = PP_MP1_STATE_UNLOAD; 2612fb4d8502Sjsg 261336668b15Sjsg ret = amdgpu_device_prepare(drm_dev); 261436668b15Sjsg if (ret) 261536668b15Sjsg return ret; 2616c349dbc7Sjsg ret = amdgpu_device_suspend(drm_dev, false); 26175ca02815Sjsg if (ret) { 26185ca02815Sjsg adev->in_runpm = false; 26195ca02815Sjsg if (amdgpu_device_supports_boco(drm_dev)) 26205ca02815Sjsg adev->mp1_state = PP_MP1_STATE_NONE; 2621c349dbc7Sjsg return ret; 26225ca02815Sjsg } 2623c349dbc7Sjsg 26245ca02815Sjsg if (amdgpu_device_supports_boco(drm_dev)) 26255ca02815Sjsg adev->mp1_state = PP_MP1_STATE_NONE; 26265ca02815Sjsg 26275ca02815Sjsg if (amdgpu_device_supports_px(drm_dev)) { 2628c349dbc7Sjsg /* Only need to handle PCI state in the driver for ATPX 2629c349dbc7Sjsg * PCI core handles it for _PR3. 2630c349dbc7Sjsg */ 2631ad8b1aafSjsg amdgpu_device_cache_pci_state(pdev); 2632fb4d8502Sjsg pci_disable_device(pdev); 2633fb4d8502Sjsg pci_ignore_hotplug(pdev); 2634fb4d8502Sjsg pci_set_power_state(pdev, PCI_D3cold); 2635fb4d8502Sjsg drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 26361060840fSjsg } else if (amdgpu_device_supports_boco(drm_dev)) { 26371060840fSjsg /* nothing to do */ 2638c349dbc7Sjsg } else if (amdgpu_device_supports_baco(drm_dev)) { 2639c349dbc7Sjsg amdgpu_device_baco_enter(drm_dev); 2640c349dbc7Sjsg } 2641fb4d8502Sjsg 2642f005ef32Sjsg dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); 2643f005ef32Sjsg 2644fb4d8502Sjsg return 0; 2645fb4d8502Sjsg } 2646fb4d8502Sjsg 2647fb4d8502Sjsg static int amdgpu_pmops_runtime_resume(struct device *dev) 2648fb4d8502Sjsg { 2649fb4d8502Sjsg struct pci_dev *pdev = to_pci_dev(dev); 2650fb4d8502Sjsg struct drm_device *drm_dev = pci_get_drvdata(pdev); 2651ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2652fb4d8502Sjsg int ret; 2653fb4d8502Sjsg 26541bb76ff1Sjsg if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2655fb4d8502Sjsg return -EINVAL; 2656fb4d8502Sjsg 26575ca02815Sjsg /* Avoids registers access if device is physically gone */ 26585ca02815Sjsg if (!pci_device_is_present(adev->pdev)) 26595ca02815Sjsg adev->no_hw_access = true; 26605ca02815Sjsg 26615ca02815Sjsg if (amdgpu_device_supports_px(drm_dev)) { 2662fb4d8502Sjsg drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2663fb4d8502Sjsg 2664c349dbc7Sjsg /* Only need to handle PCI state in the driver for ATPX 2665c349dbc7Sjsg * PCI core handles it for _PR3. 2666c349dbc7Sjsg */ 2667fb4d8502Sjsg pci_set_power_state(pdev, PCI_D0); 2668ad8b1aafSjsg amdgpu_device_load_pci_state(pdev); 2669fb4d8502Sjsg ret = pci_enable_device(pdev); 2670fb4d8502Sjsg if (ret) 2671fb4d8502Sjsg return ret; 2672fb4d8502Sjsg pci_set_master(pdev); 26735ca02815Sjsg } else if (amdgpu_device_supports_boco(drm_dev)) { 26745ca02815Sjsg /* Only need to handle PCI state in the driver for ATPX 26755ca02815Sjsg * PCI core handles it for _PR3. 26765ca02815Sjsg */ 26775ca02815Sjsg pci_set_master(pdev); 2678c349dbc7Sjsg } else if (amdgpu_device_supports_baco(drm_dev)) { 2679c349dbc7Sjsg amdgpu_device_baco_exit(drm_dev); 2680c349dbc7Sjsg } 2681c349dbc7Sjsg ret = amdgpu_device_resume(drm_dev, false); 26821bb76ff1Sjsg if (ret) { 26831bb76ff1Sjsg if (amdgpu_device_supports_px(drm_dev)) 26841bb76ff1Sjsg pci_disable_device(pdev); 26855ca02815Sjsg return ret; 26861bb76ff1Sjsg } 26875ca02815Sjsg 26885ca02815Sjsg if (amdgpu_device_supports_px(drm_dev)) 2689fb4d8502Sjsg drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2690c349dbc7Sjsg adev->in_runpm = false; 2691fb4d8502Sjsg return 0; 2692fb4d8502Sjsg } 2693fb4d8502Sjsg 2694fb4d8502Sjsg static int amdgpu_pmops_runtime_idle(struct device *dev) 2695fb4d8502Sjsg { 2696c349dbc7Sjsg struct drm_device *drm_dev = dev_get_drvdata(dev); 2697ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(drm_dev); 2698c349dbc7Sjsg /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2699c349dbc7Sjsg int ret = 1; 2700fb4d8502Sjsg 27011bb76ff1Sjsg if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2702fb4d8502Sjsg pm_runtime_forbid(dev); 2703fb4d8502Sjsg return -EBUSY; 2704fb4d8502Sjsg } 2705fb4d8502Sjsg 27061bb76ff1Sjsg ret = amdgpu_runtime_idle_check_display(dev); 2707c349dbc7Sjsg 2708fb4d8502Sjsg pm_runtime_mark_last_busy(dev); 2709fb4d8502Sjsg pm_runtime_autosuspend(dev); 2710c349dbc7Sjsg return ret; 2711fb4d8502Sjsg } 2712fb4d8502Sjsg #endif /* notyet */ 2713fb4d8502Sjsg 2714fb4d8502Sjsg #ifdef __linux__ 2715fb4d8502Sjsg long amdgpu_drm_ioctl(struct file *filp, 2716fb4d8502Sjsg unsigned int cmd, unsigned long arg) 2717fb4d8502Sjsg { 2718fb4d8502Sjsg struct drm_file *file_priv = filp->private_data; 2719fb4d8502Sjsg struct drm_device *dev; 2720fb4d8502Sjsg long ret; 2721f005ef32Sjsg 2722fb4d8502Sjsg dev = file_priv->minor->dev; 2723fb4d8502Sjsg ret = pm_runtime_get_sync(dev->dev); 2724fb4d8502Sjsg if (ret < 0) 2725ad8b1aafSjsg goto out; 2726fb4d8502Sjsg 2727fb4d8502Sjsg ret = drm_ioctl(filp, cmd, arg); 2728fb4d8502Sjsg 2729fb4d8502Sjsg pm_runtime_mark_last_busy(dev->dev); 2730ad8b1aafSjsg out: 2731fb4d8502Sjsg pm_runtime_put_autosuspend(dev->dev); 2732fb4d8502Sjsg return ret; 2733fb4d8502Sjsg } 2734fb4d8502Sjsg 2735fb4d8502Sjsg static const struct dev_pm_ops amdgpu_pm_ops = { 27365ca02815Sjsg .prepare = amdgpu_pmops_prepare, 27375ca02815Sjsg .complete = amdgpu_pmops_complete, 2738fb4d8502Sjsg .suspend = amdgpu_pmops_suspend, 2739777c88bfSjsg .suspend_noirq = amdgpu_pmops_suspend_noirq, 2740fb4d8502Sjsg .resume = amdgpu_pmops_resume, 2741fb4d8502Sjsg .freeze = amdgpu_pmops_freeze, 2742fb4d8502Sjsg .thaw = amdgpu_pmops_thaw, 2743fb4d8502Sjsg .poweroff = amdgpu_pmops_poweroff, 2744fb4d8502Sjsg .restore = amdgpu_pmops_restore, 2745fb4d8502Sjsg .runtime_suspend = amdgpu_pmops_runtime_suspend, 2746fb4d8502Sjsg .runtime_resume = amdgpu_pmops_runtime_resume, 2747fb4d8502Sjsg .runtime_idle = amdgpu_pmops_runtime_idle, 2748fb4d8502Sjsg }; 2749fb4d8502Sjsg 2750fb4d8502Sjsg static int amdgpu_flush(struct file *f, fl_owner_t id) 2751fb4d8502Sjsg { 2752fb4d8502Sjsg struct drm_file *file_priv = f->private_data; 2753fb4d8502Sjsg struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2754c349dbc7Sjsg long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2755fb4d8502Sjsg 2756c349dbc7Sjsg timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2757c349dbc7Sjsg timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2758fb4d8502Sjsg 2759c349dbc7Sjsg return timeout >= 0 ? 0 : timeout; 2760fb4d8502Sjsg } 2761fb4d8502Sjsg 2762fb4d8502Sjsg static const struct file_operations amdgpu_driver_kms_fops = { 2763fb4d8502Sjsg .owner = THIS_MODULE, 2764fb4d8502Sjsg .open = drm_open, 2765fb4d8502Sjsg .flush = amdgpu_flush, 2766fb4d8502Sjsg .release = drm_release, 2767fb4d8502Sjsg .unlocked_ioctl = amdgpu_drm_ioctl, 27685ca02815Sjsg .mmap = drm_gem_mmap, 2769fb4d8502Sjsg .poll = drm_poll, 2770fb4d8502Sjsg .read = drm_read, 2771fb4d8502Sjsg #ifdef CONFIG_COMPAT 2772fb4d8502Sjsg .compat_ioctl = amdgpu_kms_compat_ioctl, 2773fb4d8502Sjsg #endif 27745ca02815Sjsg #ifdef CONFIG_PROC_FS 2775f005ef32Sjsg .show_fdinfo = drm_show_fdinfo, 27765ca02815Sjsg #endif 2777fb4d8502Sjsg }; 2778c349dbc7Sjsg 2779fb4d8502Sjsg #endif /* __linux__ */ 2780fb4d8502Sjsg 2781c349dbc7Sjsg int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2782fb4d8502Sjsg { 2783c349dbc7Sjsg STUB(); 2784c349dbc7Sjsg return -ENOSYS; 2785c349dbc7Sjsg #ifdef notyet 2786c349dbc7Sjsg struct drm_file *file; 2787c349dbc7Sjsg 2788c349dbc7Sjsg if (!filp) 2789c349dbc7Sjsg return -EINVAL; 2790c349dbc7Sjsg 2791f005ef32Sjsg if (filp->f_op != &amdgpu_driver_kms_fops) 2792c349dbc7Sjsg return -EINVAL; 2793c349dbc7Sjsg 2794c349dbc7Sjsg file = filp->private_data; 2795c349dbc7Sjsg *fpriv = file->driver_priv; 2796c349dbc7Sjsg return 0; 2797c349dbc7Sjsg #endif 2798fb4d8502Sjsg } 2799fb4d8502Sjsg 28005ca02815Sjsg const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 28015ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28025ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28035ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28045ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 28055ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28065ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28075ca02815Sjsg /* KMS */ 28085ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28095ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28105ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28115ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28125ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28135ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28145ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28155ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28165ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28175ca02815Sjsg DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 28185ca02815Sjsg }; 28195ca02815Sjsg 28201bb76ff1Sjsg static const struct drm_driver amdgpu_kms_driver = { 2821fb4d8502Sjsg .driver_features = 2822c349dbc7Sjsg DRIVER_ATOMIC | 2823c349dbc7Sjsg DRIVER_GEM | 2824c349dbc7Sjsg DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2825c349dbc7Sjsg DRIVER_SYNCOBJ_TIMELINE, 2826fb4d8502Sjsg .open = amdgpu_driver_open_kms, 2827c349dbc7Sjsg #ifdef __OpenBSD__ 28285ca02815Sjsg .mmap = drm_gem_mmap, 2829c349dbc7Sjsg #endif 2830fb4d8502Sjsg .postclose = amdgpu_driver_postclose_kms, 2831fb4d8502Sjsg .lastclose = amdgpu_driver_lastclose_kms, 2832fb4d8502Sjsg .ioctls = amdgpu_ioctls_kms, 28335ca02815Sjsg .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2834fb4d8502Sjsg .dumb_create = amdgpu_mode_dumb_create, 2835fb4d8502Sjsg .dumb_map_offset = amdgpu_mode_dumb_mmap, 2836fb4d8502Sjsg #ifdef __linux__ 2837fb4d8502Sjsg .fops = &amdgpu_driver_kms_fops, 2838fb4d8502Sjsg #endif 28395ca02815Sjsg .release = &amdgpu_driver_release_kms, 2840f005ef32Sjsg #ifdef CONFIG_PROC_FS 2841f005ef32Sjsg .show_fdinfo = amdgpu_show_fdinfo, 2842fb4d8502Sjsg #endif 2843fb4d8502Sjsg 2844f005ef32Sjsg .gem_prime_import = amdgpu_gem_prime_import, 2845f005ef32Sjsg 2846f005ef32Sjsg .name = DRIVER_NAME, 2847f005ef32Sjsg .desc = DRIVER_DESC, 2848f005ef32Sjsg .date = DRIVER_DATE, 2849f005ef32Sjsg .major = KMS_DRIVER_MAJOR, 2850f005ef32Sjsg .minor = KMS_DRIVER_MINOR, 2851f005ef32Sjsg .patchlevel = KMS_DRIVER_PATCHLEVEL, 2852f005ef32Sjsg }; 2853f005ef32Sjsg 2854f005ef32Sjsg const struct drm_driver amdgpu_partition_driver = { 2855f005ef32Sjsg .driver_features = 2856f005ef32Sjsg DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | 2857f005ef32Sjsg DRIVER_SYNCOBJ_TIMELINE, 2858f005ef32Sjsg .open = amdgpu_driver_open_kms, 2859f005ef32Sjsg .postclose = amdgpu_driver_postclose_kms, 2860f005ef32Sjsg .lastclose = amdgpu_driver_lastclose_kms, 2861f005ef32Sjsg .ioctls = amdgpu_ioctls_kms, 2862f005ef32Sjsg .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2863f005ef32Sjsg .dumb_create = amdgpu_mode_dumb_create, 2864f005ef32Sjsg .dumb_map_offset = amdgpu_mode_dumb_mmap, 2865f005ef32Sjsg #ifdef __linux__ 2866f005ef32Sjsg .fops = &amdgpu_driver_kms_fops, 2867f005ef32Sjsg #endif 2868f005ef32Sjsg .release = &amdgpu_driver_release_kms, 2869f005ef32Sjsg 2870f005ef32Sjsg .gem_prime_import = amdgpu_gem_prime_import, 2871f005ef32Sjsg 2872fb4d8502Sjsg .name = DRIVER_NAME, 2873fb4d8502Sjsg .desc = DRIVER_DESC, 2874fb4d8502Sjsg .date = DRIVER_DATE, 2875fb4d8502Sjsg .major = KMS_DRIVER_MAJOR, 2876fb4d8502Sjsg .minor = KMS_DRIVER_MINOR, 2877fb4d8502Sjsg .patchlevel = KMS_DRIVER_PATCHLEVEL, 2878fb4d8502Sjsg }; 2879fb4d8502Sjsg 2880fb4d8502Sjsg #ifdef __linux__ 2881ad8b1aafSjsg static struct pci_error_handlers amdgpu_pci_err_handler = { 2882ad8b1aafSjsg .error_detected = amdgpu_pci_error_detected, 2883ad8b1aafSjsg .mmio_enabled = amdgpu_pci_mmio_enabled, 2884ad8b1aafSjsg .slot_reset = amdgpu_pci_slot_reset, 2885ad8b1aafSjsg .resume = amdgpu_pci_resume, 2886ad8b1aafSjsg }; 2887ad8b1aafSjsg 28885ca02815Sjsg static const struct attribute_group *amdgpu_sysfs_groups[] = { 28895ca02815Sjsg &amdgpu_vram_mgr_attr_group, 28905ca02815Sjsg &amdgpu_gtt_mgr_attr_group, 2891f005ef32Sjsg &amdgpu_flash_attr_group, 28925ca02815Sjsg NULL, 28935ca02815Sjsg }; 28945ca02815Sjsg 2895fb4d8502Sjsg static struct pci_driver amdgpu_kms_pci_driver = { 2896fb4d8502Sjsg .name = DRIVER_NAME, 2897fb4d8502Sjsg .id_table = pciidlist, 2898fb4d8502Sjsg .probe = amdgpu_pci_probe, 2899fb4d8502Sjsg .remove = amdgpu_pci_remove, 2900fb4d8502Sjsg .shutdown = amdgpu_pci_shutdown, 2901fb4d8502Sjsg .driver.pm = &amdgpu_pm_ops, 2902ad8b1aafSjsg .err_handler = &amdgpu_pci_err_handler, 29035ca02815Sjsg .dev_groups = amdgpu_sysfs_groups, 2904fb4d8502Sjsg }; 2905fb4d8502Sjsg 2906fb4d8502Sjsg static int __init amdgpu_init(void) 2907fb4d8502Sjsg { 2908fb4d8502Sjsg int r; 2909fb4d8502Sjsg 29101bb76ff1Sjsg if (drm_firmware_drivers_only()) 2911fb4d8502Sjsg return -EINVAL; 2912fb4d8502Sjsg 2913fb4d8502Sjsg r = amdgpu_sync_init(); 2914fb4d8502Sjsg if (r) 2915fb4d8502Sjsg goto error_sync; 2916fb4d8502Sjsg 2917fb4d8502Sjsg r = amdgpu_fence_slab_init(); 2918fb4d8502Sjsg if (r) 2919fb4d8502Sjsg goto error_fence; 2920fb4d8502Sjsg 2921fb4d8502Sjsg DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2922fb4d8502Sjsg amdgpu_register_atpx_handler(); 29235ca02815Sjsg amdgpu_acpi_detect(); 2924c349dbc7Sjsg 2925c349dbc7Sjsg /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2926c349dbc7Sjsg amdgpu_amdkfd_init(); 2927c349dbc7Sjsg 2928fb4d8502Sjsg /* let modprobe override vga console setting */ 2929c349dbc7Sjsg return pci_register_driver(&amdgpu_kms_pci_driver); 2930fb4d8502Sjsg 2931fb4d8502Sjsg error_fence: 2932fb4d8502Sjsg amdgpu_sync_fini(); 2933fb4d8502Sjsg 2934fb4d8502Sjsg error_sync: 2935fb4d8502Sjsg return r; 2936fb4d8502Sjsg } 2937fb4d8502Sjsg 2938fb4d8502Sjsg static void __exit amdgpu_exit(void) 2939fb4d8502Sjsg { 2940fb4d8502Sjsg amdgpu_amdkfd_fini(); 2941c349dbc7Sjsg pci_unregister_driver(&amdgpu_kms_pci_driver); 2942fb4d8502Sjsg amdgpu_unregister_atpx_handler(); 2943f005ef32Sjsg amdgpu_acpi_release(); 2944fb4d8502Sjsg amdgpu_sync_fini(); 2945fb4d8502Sjsg amdgpu_fence_slab_fini(); 2946c349dbc7Sjsg mmu_notifier_synchronize(); 2947f005ef32Sjsg amdgpu_xcp_drv_release(); 2948fb4d8502Sjsg } 2949fb4d8502Sjsg 2950fb4d8502Sjsg module_init(amdgpu_init); 2951fb4d8502Sjsg module_exit(amdgpu_exit); 2952fb4d8502Sjsg 2953fb4d8502Sjsg MODULE_AUTHOR(DRIVER_AUTHOR); 2954fb4d8502Sjsg MODULE_DESCRIPTION(DRIVER_DESC); 2955fb4d8502Sjsg MODULE_LICENSE("GPL and additional rights"); 2956fb4d8502Sjsg #endif /* __linux__ */ 29571bb76ff1Sjsg 29581bb76ff1Sjsg #include <drm/drm_drv.h> 2959bc31cd49Sbentley #include <drm/drm_utils.h> 2960f005ef32Sjsg #include <drm/drm_fb_helper.h> 29611bb76ff1Sjsg 29621bb76ff1Sjsg #include "vga.h" 29631bb76ff1Sjsg 29641bb76ff1Sjsg #if NVGA > 0 29651bb76ff1Sjsg #include <dev/ic/mc6845reg.h> 29661bb76ff1Sjsg #include <dev/ic/pcdisplayvar.h> 29671bb76ff1Sjsg #include <dev/ic/vgareg.h> 29681bb76ff1Sjsg #include <dev/ic/vgavar.h> 29691bb76ff1Sjsg 29701bb76ff1Sjsg extern int vga_console_attached; 29711bb76ff1Sjsg #endif 29721bb76ff1Sjsg 29731bb76ff1Sjsg #ifdef __amd64__ 29741bb76ff1Sjsg #include "efifb.h" 29751bb76ff1Sjsg #include <machine/biosvar.h> 29761bb76ff1Sjsg #endif 29771bb76ff1Sjsg 29781bb76ff1Sjsg #if NEFIFB > 0 29791bb76ff1Sjsg #include <machine/efifbvar.h> 29801bb76ff1Sjsg #endif 29811bb76ff1Sjsg 29821bb76ff1Sjsg int amdgpu_probe(struct device *, void *, void *); 29831bb76ff1Sjsg void amdgpu_attach(struct device *, struct device *, void *); 29841bb76ff1Sjsg int amdgpu_detach(struct device *, int); 29851bb76ff1Sjsg int amdgpu_activate(struct device *, int); 29861bb76ff1Sjsg void amdgpu_attachhook(struct device *); 29871bb76ff1Sjsg int amdgpu_forcedetach(struct amdgpu_device *); 29881bb76ff1Sjsg 29891bb76ff1Sjsg bool amdgpu_msi_ok(struct amdgpu_device *); 29901bb76ff1Sjsg 29911bb76ff1Sjsg /* 29921bb76ff1Sjsg * set if the mountroot hook has a fatal error 29931bb76ff1Sjsg * such as not being able to find the firmware 29941bb76ff1Sjsg */ 29951bb76ff1Sjsg int amdgpu_fatal_error; 29961bb76ff1Sjsg 29971bb76ff1Sjsg const struct cfattach amdgpu_ca = { 29981bb76ff1Sjsg sizeof (struct amdgpu_device), amdgpu_probe, amdgpu_attach, 29991bb76ff1Sjsg amdgpu_detach, amdgpu_activate 30001bb76ff1Sjsg }; 30011bb76ff1Sjsg 30021bb76ff1Sjsg struct cfdriver amdgpu_cd = { 30031bb76ff1Sjsg NULL, "amdgpu", DV_DULL 30041bb76ff1Sjsg }; 30051bb76ff1Sjsg 30061bb76ff1Sjsg int 30071bb76ff1Sjsg amdgpu_probe(struct device *parent, void *match, void *aux) 30081bb76ff1Sjsg { 30091bb76ff1Sjsg struct pci_attach_args *pa = aux; 30101bb76ff1Sjsg const struct pci_device_id *id_entry; 30111bb76ff1Sjsg unsigned long flags = 0; 30121bb76ff1Sjsg int i; 30131bb76ff1Sjsg 30141bb76ff1Sjsg if (amdgpu_fatal_error) 30151bb76ff1Sjsg return 0; 30161bb76ff1Sjsg 30171bb76ff1Sjsg id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 30181bb76ff1Sjsg PCI_PRODUCT(pa->pa_id), pciidlist); 30191bb76ff1Sjsg if (id_entry != NULL) { 30201bb76ff1Sjsg flags = id_entry->driver_data; 30211bb76ff1Sjsg 30221bb76ff1Sjsg if (id_entry->device == PCI_ANY_ID) { 30231bb76ff1Sjsg if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 30241bb76ff1Sjsg return 0; 30251bb76ff1Sjsg if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA && 30261bb76ff1Sjsg PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_MISC) 30271bb76ff1Sjsg return 0; 30281bb76ff1Sjsg } 30291bb76ff1Sjsg 30301bb76ff1Sjsg /* skip devices which are owned by radeon */ 30311bb76ff1Sjsg for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 30321bb76ff1Sjsg if (amdgpu_unsupported_pciidlist[i] == 30331bb76ff1Sjsg PCI_PRODUCT(pa->pa_id)) 30341bb76ff1Sjsg return 0; 30351bb76ff1Sjsg } 30361bb76ff1Sjsg 30371bb76ff1Sjsg if (flags & AMD_EXP_HW_SUPPORT) 30381bb76ff1Sjsg return 0; 30391bb76ff1Sjsg else 30401bb76ff1Sjsg return 20; 30411bb76ff1Sjsg } 30421bb76ff1Sjsg 30431bb76ff1Sjsg return 0; 30441bb76ff1Sjsg } 30451bb76ff1Sjsg 30461bb76ff1Sjsg /* 30471bb76ff1Sjsg * some functions are only called once on init regardless of how many times 30481bb76ff1Sjsg * amdgpu attaches in linux this is handled via module_init()/module_exit() 30491bb76ff1Sjsg */ 30501bb76ff1Sjsg int amdgpu_refcnt; 30511bb76ff1Sjsg 30521bb76ff1Sjsg int __init drm_sched_fence_slab_init(void); 30531bb76ff1Sjsg void __exit drm_sched_fence_slab_fini(void); 30541bb76ff1Sjsg irqreturn_t amdgpu_irq_handler(void *); 30551bb76ff1Sjsg 30561bb76ff1Sjsg void 30571bb76ff1Sjsg amdgpu_attach(struct device *parent, struct device *self, void *aux) 30581bb76ff1Sjsg { 30591bb76ff1Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)self; 30601bb76ff1Sjsg struct drm_device *dev; 30611bb76ff1Sjsg struct pci_attach_args *pa = aux; 30621bb76ff1Sjsg const struct pci_device_id *id_entry; 30631bb76ff1Sjsg pcireg_t type; 30641bb76ff1Sjsg int i; 30651bb76ff1Sjsg uint8_t rmmio_bar; 30661bb76ff1Sjsg paddr_t fb_aper; 30671bb76ff1Sjsg pcireg_t addr, mask; 30681bb76ff1Sjsg int s; 30691bb76ff1Sjsg bool supports_atomic = false; 30701bb76ff1Sjsg 30711bb76ff1Sjsg id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 30721bb76ff1Sjsg PCI_PRODUCT(pa->pa_id), pciidlist); 30731bb76ff1Sjsg adev->flags = id_entry->driver_data; 30741bb76ff1Sjsg adev->family = adev->flags & AMD_ASIC_MASK; 30751bb76ff1Sjsg adev->pc = pa->pa_pc; 30761bb76ff1Sjsg adev->pa_tag = pa->pa_tag; 30771bb76ff1Sjsg adev->iot = pa->pa_iot; 30781bb76ff1Sjsg adev->memt = pa->pa_memt; 30791bb76ff1Sjsg adev->dmat = pa->pa_dmat; 30801bb76ff1Sjsg 30811bb76ff1Sjsg if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 30821bb76ff1Sjsg PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 30831bb76ff1Sjsg (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 30841bb76ff1Sjsg & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 30851bb76ff1Sjsg == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 30861bb76ff1Sjsg adev->primary = 1; 30871bb76ff1Sjsg #if NVGA > 0 30881bb76ff1Sjsg adev->console = vga_is_console(pa->pa_iot, -1); 30891bb76ff1Sjsg vga_console_attached = 1; 30901bb76ff1Sjsg #endif 30911bb76ff1Sjsg } 30921bb76ff1Sjsg #if NEFIFB > 0 30931bb76ff1Sjsg if (efifb_is_primary(pa)) { 30941bb76ff1Sjsg adev->primary = 1; 30951bb76ff1Sjsg adev->console = efifb_is_console(pa); 30961bb76ff1Sjsg efifb_detach(); 30971bb76ff1Sjsg } 30981bb76ff1Sjsg #endif 30991bb76ff1Sjsg 31001bb76ff1Sjsg #define AMDGPU_PCI_MEM 0x10 31011bb76ff1Sjsg 31021bb76ff1Sjsg type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM); 31031bb76ff1Sjsg if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 31041bb76ff1Sjsg pci_mapreg_info(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, 31051bb76ff1Sjsg type, &adev->fb_aper_offset, &adev->fb_aper_size, NULL)) { 3106961f2fc7Sjsg printf(": can't get framebuffer info\n"); 31071bb76ff1Sjsg return; 31081bb76ff1Sjsg } 31091bb76ff1Sjsg 31101bb76ff1Sjsg if (adev->fb_aper_offset == 0) { 31111bb76ff1Sjsg bus_size_t start, end, pci_mem_end; 31121bb76ff1Sjsg bus_addr_t base; 31131bb76ff1Sjsg 31141bb76ff1Sjsg KASSERT(pa->pa_memex != NULL); 31151bb76ff1Sjsg 31161bb76ff1Sjsg start = max(PCI_MEM_START, pa->pa_memex->ex_start); 31171bb76ff1Sjsg if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 31181bb76ff1Sjsg pci_mem_end = PCI_MEM64_END; 31191bb76ff1Sjsg else 31201bb76ff1Sjsg pci_mem_end = PCI_MEM_END; 31211bb76ff1Sjsg end = min(pci_mem_end, pa->pa_memex->ex_end); 31221bb76ff1Sjsg if (extent_alloc_subregion(pa->pa_memex, start, end, 31231bb76ff1Sjsg adev->fb_aper_size, adev->fb_aper_size, 0, 0, 0, &base)) { 31241bb76ff1Sjsg printf(": can't reserve framebuffer space\n"); 31251bb76ff1Sjsg return; 31261bb76ff1Sjsg } 31271bb76ff1Sjsg pci_conf_write(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, base); 31281bb76ff1Sjsg if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 31291bb76ff1Sjsg pci_conf_write(pa->pa_pc, pa->pa_tag, 31301bb76ff1Sjsg AMDGPU_PCI_MEM + 4, (uint64_t)base >> 32); 31311bb76ff1Sjsg adev->fb_aper_offset = base; 31321bb76ff1Sjsg } 31331bb76ff1Sjsg 31341bb76ff1Sjsg if (adev->family >= CHIP_BONAIRE) 31351bb76ff1Sjsg rmmio_bar = 0x24; 31361bb76ff1Sjsg else 31371bb76ff1Sjsg rmmio_bar = 0x18; 31381bb76ff1Sjsg 31391bb76ff1Sjsg type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); 31401bb76ff1Sjsg if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 31411bb76ff1Sjsg pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, 31421bb76ff1Sjsg &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base, 31431bb76ff1Sjsg &adev->rmmio_size, 0)) { 31441bb76ff1Sjsg printf(": can't map rmmio space\n"); 31451bb76ff1Sjsg return; 31461bb76ff1Sjsg } 31471bb76ff1Sjsg adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh); 31481bb76ff1Sjsg 31491bb76ff1Sjsg /* 31501bb76ff1Sjsg * Make sure we have a base address for the ROM such that we 31511bb76ff1Sjsg * can map it later. 31521bb76ff1Sjsg */ 31531bb76ff1Sjsg s = splhigh(); 31541bb76ff1Sjsg addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 31551bb76ff1Sjsg pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 31561bb76ff1Sjsg mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 31571bb76ff1Sjsg pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 31581bb76ff1Sjsg splx(s); 31591bb76ff1Sjsg 31601bb76ff1Sjsg if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 31611bb76ff1Sjsg bus_size_t size, start, end; 31621bb76ff1Sjsg bus_addr_t base; 31631bb76ff1Sjsg 31641bb76ff1Sjsg size = PCI_ROM_SIZE(mask); 31651bb76ff1Sjsg start = max(PCI_MEM_START, pa->pa_memex->ex_start); 31661bb76ff1Sjsg end = min(PCI_MEM_END, pa->pa_memex->ex_end); 31671bb76ff1Sjsg if (extent_alloc_subregion(pa->pa_memex, start, end, size, 31681bb76ff1Sjsg size, 0, 0, 0, &base) == 0) 31691bb76ff1Sjsg pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 31701bb76ff1Sjsg } 31711bb76ff1Sjsg 31721bb76ff1Sjsg printf("\n"); 31731bb76ff1Sjsg 31741bb76ff1Sjsg /* from amdgpu_pci_probe(), aspm test done later */ 31751bb76ff1Sjsg 31761bb76ff1Sjsg if (!amdgpu_virtual_display && 31771bb76ff1Sjsg amdgpu_device_asic_has_dc_support(adev->family)) 31781bb76ff1Sjsg supports_atomic = true; 31791bb76ff1Sjsg 31801bb76ff1Sjsg if ((adev->flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 31811bb76ff1Sjsg DRM_INFO("This hardware requires experimental hardware support.\n"); 31821bb76ff1Sjsg return; 31831bb76ff1Sjsg } 31841bb76ff1Sjsg 31851bb76ff1Sjsg /* 31861bb76ff1Sjsg * Initialize amdkfd before starting radeon. 31871bb76ff1Sjsg */ 31881bb76ff1Sjsg amdgpu_amdkfd_init(); 31891bb76ff1Sjsg 31901bb76ff1Sjsg dev = drm_attach_pci(&amdgpu_kms_driver, pa, 0, adev->primary, 31911bb76ff1Sjsg self, &adev->ddev); 31921bb76ff1Sjsg if (dev == NULL) { 31931bb76ff1Sjsg printf("%s: drm attach failed\n", adev->self.dv_xname); 31941bb76ff1Sjsg return; 31951bb76ff1Sjsg } 31961bb76ff1Sjsg adev->pdev = dev->pdev; 31971bb76ff1Sjsg 31981bb76ff1Sjsg /* from amdgpu_pci_probe() */ 31991bb76ff1Sjsg if (amdgpu_aspm == -1 && !pcie_aspm_enabled(adev->pdev)) 32001bb76ff1Sjsg amdgpu_aspm = 0; 32011bb76ff1Sjsg 32021bb76ff1Sjsg if (!supports_atomic) 32031bb76ff1Sjsg dev->driver_features &= ~DRIVER_ATOMIC; 32041bb76ff1Sjsg 32051bb76ff1Sjsg if (!amdgpu_msi_ok(adev)) 32061bb76ff1Sjsg pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 32071bb76ff1Sjsg 32081bb76ff1Sjsg /* from amdgpu_init() */ 32091bb76ff1Sjsg if (amdgpu_refcnt == 0) { 32101bb76ff1Sjsg drm_sched_fence_slab_init(); 32111bb76ff1Sjsg 32121bb76ff1Sjsg if (amdgpu_sync_init()) { 32131bb76ff1Sjsg printf("%s: amdgpu_sync_init failed\n", 32141bb76ff1Sjsg adev->self.dv_xname); 32151bb76ff1Sjsg return; 32161bb76ff1Sjsg } 32171bb76ff1Sjsg 32181bb76ff1Sjsg if (amdgpu_fence_slab_init()) { 32191bb76ff1Sjsg amdgpu_sync_fini(); 32201bb76ff1Sjsg printf("%s: amdgpu_fence_slab_init failed\n", 32211bb76ff1Sjsg adev->self.dv_xname); 32221bb76ff1Sjsg return; 32231bb76ff1Sjsg } 32241bb76ff1Sjsg 32251bb76ff1Sjsg amdgpu_register_atpx_handler(); 32261bb76ff1Sjsg amdgpu_acpi_detect(); 32271bb76ff1Sjsg } 32281bb76ff1Sjsg amdgpu_refcnt++; 32291bb76ff1Sjsg 32301bb76ff1Sjsg adev->irq.msi_enabled = false; 32311bb76ff1Sjsg if (pci_intr_map_msi(pa, &adev->intrh) == 0) 32321bb76ff1Sjsg adev->irq.msi_enabled = true; 32331bb76ff1Sjsg else if (pci_intr_map(pa, &adev->intrh) != 0) { 32341bb76ff1Sjsg printf("%s: couldn't map interrupt\n", adev->self.dv_xname); 32351bb76ff1Sjsg return; 32361bb76ff1Sjsg } 32371bb76ff1Sjsg printf("%s: %s\n", adev->self.dv_xname, 32381bb76ff1Sjsg pci_intr_string(pa->pa_pc, adev->intrh)); 32391bb76ff1Sjsg 32401bb76ff1Sjsg adev->irqh = pci_intr_establish(pa->pa_pc, adev->intrh, IPL_TTY, 32411bb76ff1Sjsg amdgpu_irq_handler, &adev->ddev, adev->self.dv_xname); 32421bb76ff1Sjsg if (adev->irqh == NULL) { 32431bb76ff1Sjsg printf("%s: couldn't establish interrupt\n", 32441bb76ff1Sjsg adev->self.dv_xname); 32451bb76ff1Sjsg return; 32461bb76ff1Sjsg } 32471bb76ff1Sjsg adev->pdev->irq = 0; 32481bb76ff1Sjsg 32491bb76ff1Sjsg fb_aper = bus_space_mmap(adev->memt, adev->fb_aper_offset, 0, 0, 0); 32501bb76ff1Sjsg if (fb_aper != -1) 32511bb76ff1Sjsg rasops_claim_framebuffer(fb_aper, adev->fb_aper_size, self); 32521bb76ff1Sjsg 32531bb76ff1Sjsg 32541bb76ff1Sjsg adev->shutdown = true; 32551bb76ff1Sjsg config_mountroot(self, amdgpu_attachhook); 32561bb76ff1Sjsg } 32571bb76ff1Sjsg 32581bb76ff1Sjsg int 32591bb76ff1Sjsg amdgpu_forcedetach(struct amdgpu_device *adev) 32601bb76ff1Sjsg { 32611bb76ff1Sjsg struct pci_softc *sc = (struct pci_softc *)adev->self.dv_parent; 32621bb76ff1Sjsg pcitag_t tag = adev->pa_tag; 32631bb76ff1Sjsg 32641bb76ff1Sjsg #if NVGA > 0 32651bb76ff1Sjsg if (adev->primary) 32661bb76ff1Sjsg vga_console_attached = 0; 32671bb76ff1Sjsg #endif 32681bb76ff1Sjsg 32691bb76ff1Sjsg /* reprobe pci device for non efi systems */ 32701bb76ff1Sjsg #if NEFIFB > 0 32711bb76ff1Sjsg if (bios_efiinfo == NULL && !efifb_cb_found()) { 32721bb76ff1Sjsg #endif 32731bb76ff1Sjsg config_detach(&adev->self, 0); 32741bb76ff1Sjsg return pci_probe_device(sc, tag, NULL, NULL); 32751bb76ff1Sjsg #if NEFIFB > 0 32761bb76ff1Sjsg } else if (adev->primary) { 32771bb76ff1Sjsg efifb_reattach(); 32781bb76ff1Sjsg } 32791bb76ff1Sjsg #endif 32801bb76ff1Sjsg 32811bb76ff1Sjsg return 0; 32821bb76ff1Sjsg } 32831bb76ff1Sjsg 32841bb76ff1Sjsg void amdgpu_burner(void *, u_int, u_int); 32851bb76ff1Sjsg void amdgpu_burner_cb(void *); 32861bb76ff1Sjsg int amdgpu_wsioctl(void *, u_long, caddr_t, int, struct proc *); 32871bb76ff1Sjsg paddr_t amdgpu_wsmmap(void *, off_t, int); 32881bb76ff1Sjsg int amdgpu_alloc_screen(void *, const struct wsscreen_descr *, 32891bb76ff1Sjsg void **, int *, int *, uint32_t *); 32901bb76ff1Sjsg void amdgpu_free_screen(void *, void *); 32911bb76ff1Sjsg int amdgpu_show_screen(void *, void *, int, 32921bb76ff1Sjsg void (*)(void *, int, int), void *); 32931bb76ff1Sjsg void amdgpu_doswitch(void *); 32941bb76ff1Sjsg void amdgpu_enter_ddb(void *, void *); 32951bb76ff1Sjsg 32961bb76ff1Sjsg struct wsscreen_descr amdgpu_stdscreen = { 32971bb76ff1Sjsg "std", 32981bb76ff1Sjsg 0, 0, 32991bb76ff1Sjsg 0, 33001bb76ff1Sjsg 0, 0, 33011bb76ff1Sjsg WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 33021bb76ff1Sjsg WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 33031bb76ff1Sjsg }; 33041bb76ff1Sjsg 33051bb76ff1Sjsg const struct wsscreen_descr *amdgpu_scrlist[] = { 33061bb76ff1Sjsg &amdgpu_stdscreen, 33071bb76ff1Sjsg }; 33081bb76ff1Sjsg 33091bb76ff1Sjsg struct wsscreen_list amdgpu_screenlist = { 33101bb76ff1Sjsg nitems(amdgpu_scrlist), amdgpu_scrlist 33111bb76ff1Sjsg }; 33121bb76ff1Sjsg 33131bb76ff1Sjsg struct wsdisplay_accessops amdgpu_accessops = { 33141bb76ff1Sjsg .ioctl = amdgpu_wsioctl, 33151bb76ff1Sjsg .mmap = amdgpu_wsmmap, 33161bb76ff1Sjsg .alloc_screen = amdgpu_alloc_screen, 33171bb76ff1Sjsg .free_screen = amdgpu_free_screen, 33181bb76ff1Sjsg .show_screen = amdgpu_show_screen, 33191bb76ff1Sjsg .enter_ddb = amdgpu_enter_ddb, 33201bb76ff1Sjsg .getchar = rasops_getchar, 33211bb76ff1Sjsg .load_font = rasops_load_font, 33221bb76ff1Sjsg .list_font = rasops_list_font, 33231bb76ff1Sjsg .scrollback = rasops_scrollback, 33241bb76ff1Sjsg .burn_screen = amdgpu_burner 33251bb76ff1Sjsg }; 33261bb76ff1Sjsg 33271bb76ff1Sjsg int 33281bb76ff1Sjsg amdgpu_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 33291bb76ff1Sjsg { 33301bb76ff1Sjsg struct rasops_info *ri = v; 33311bb76ff1Sjsg struct amdgpu_device *adev = ri->ri_hw; 33321bb76ff1Sjsg struct backlight_device *bd = adev->dm.backlight_dev[0]; 33331bb76ff1Sjsg struct wsdisplay_param *dp = (struct wsdisplay_param *)data; 33341bb76ff1Sjsg struct wsdisplay_fbinfo *wdf; 33351bb76ff1Sjsg 33361bb76ff1Sjsg switch (cmd) { 33371bb76ff1Sjsg case WSDISPLAYIO_GTYPE: 33381bb76ff1Sjsg *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; 33391bb76ff1Sjsg return 0; 33401bb76ff1Sjsg case WSDISPLAYIO_GINFO: 33411bb76ff1Sjsg wdf = (struct wsdisplay_fbinfo *)data; 33421bb76ff1Sjsg wdf->width = ri->ri_width; 33431bb76ff1Sjsg wdf->height = ri->ri_height; 33441bb76ff1Sjsg wdf->depth = ri->ri_depth; 33451bb76ff1Sjsg wdf->stride = ri->ri_stride; 33461bb76ff1Sjsg wdf->offset = 0; 33471bb76ff1Sjsg wdf->cmsize = 0; 33481bb76ff1Sjsg return 0; 33491bb76ff1Sjsg case WSDISPLAYIO_GETPARAM: 33501bb76ff1Sjsg if (bd == NULL) 33511bb76ff1Sjsg return -1; 33521bb76ff1Sjsg 33531bb76ff1Sjsg switch (dp->param) { 33541bb76ff1Sjsg case WSDISPLAYIO_PARAM_BRIGHTNESS: 33551bb76ff1Sjsg dp->min = 0; 33561bb76ff1Sjsg dp->max = bd->props.max_brightness; 33571bb76ff1Sjsg dp->curval = bd->props.brightness; 33581bb76ff1Sjsg return (dp->max > dp->min) ? 0 : -1; 33591bb76ff1Sjsg } 33601bb76ff1Sjsg break; 33611bb76ff1Sjsg case WSDISPLAYIO_SETPARAM: 33621bb76ff1Sjsg if (bd == NULL || dp->curval > bd->props.max_brightness) 33631bb76ff1Sjsg return -1; 33641bb76ff1Sjsg 33651bb76ff1Sjsg switch (dp->param) { 33661bb76ff1Sjsg case WSDISPLAYIO_PARAM_BRIGHTNESS: 33671bb76ff1Sjsg bd->props.brightness = dp->curval; 33681bb76ff1Sjsg backlight_update_status(bd); 3369c78098b6Svisa knote_locked(&adev->ddev.note, NOTE_CHANGE); 33701bb76ff1Sjsg return 0; 33711bb76ff1Sjsg } 33721bb76ff1Sjsg break; 3373804fcafaSjsg case WSDISPLAYIO_SVIDEO: 3374804fcafaSjsg case WSDISPLAYIO_GVIDEO: 3375804fcafaSjsg return 0; 33761bb76ff1Sjsg } 33771bb76ff1Sjsg 33781bb76ff1Sjsg return (-1); 33791bb76ff1Sjsg } 33801bb76ff1Sjsg 33811bb76ff1Sjsg paddr_t 33821bb76ff1Sjsg amdgpu_wsmmap(void *v, off_t off, int prot) 33831bb76ff1Sjsg { 33841bb76ff1Sjsg return (-1); 33851bb76ff1Sjsg } 33861bb76ff1Sjsg 33871bb76ff1Sjsg int 33881bb76ff1Sjsg amdgpu_alloc_screen(void *v, const struct wsscreen_descr *type, 33891bb76ff1Sjsg void **cookiep, int *curxp, int *curyp, uint32_t *attrp) 33901bb76ff1Sjsg { 33911bb76ff1Sjsg return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 33921bb76ff1Sjsg } 33931bb76ff1Sjsg 33941bb76ff1Sjsg void 33951bb76ff1Sjsg amdgpu_free_screen(void *v, void *cookie) 33961bb76ff1Sjsg { 33971bb76ff1Sjsg return rasops_free_screen(v, cookie); 33981bb76ff1Sjsg } 33991bb76ff1Sjsg 34001bb76ff1Sjsg int 34011bb76ff1Sjsg amdgpu_show_screen(void *v, void *cookie, int waitok, 34021bb76ff1Sjsg void (*cb)(void *, int, int), void *cbarg) 34031bb76ff1Sjsg { 34041bb76ff1Sjsg struct rasops_info *ri = v; 34051bb76ff1Sjsg struct amdgpu_device *adev = ri->ri_hw; 34061bb76ff1Sjsg 34071bb76ff1Sjsg if (cookie == ri->ri_active) 34081bb76ff1Sjsg return (0); 34091bb76ff1Sjsg 34101bb76ff1Sjsg adev->switchcb = cb; 34111bb76ff1Sjsg adev->switchcbarg = cbarg; 34121bb76ff1Sjsg adev->switchcookie = cookie; 34131bb76ff1Sjsg if (cb) { 34141bb76ff1Sjsg task_add(systq, &adev->switchtask); 34151bb76ff1Sjsg return (EAGAIN); 34161bb76ff1Sjsg } 34171bb76ff1Sjsg 34181bb76ff1Sjsg amdgpu_doswitch(v); 34191bb76ff1Sjsg 34201bb76ff1Sjsg return (0); 34211bb76ff1Sjsg } 34221bb76ff1Sjsg 34231bb76ff1Sjsg void 34241bb76ff1Sjsg amdgpu_doswitch(void *v) 34251bb76ff1Sjsg { 34261bb76ff1Sjsg struct rasops_info *ri = v; 34271bb76ff1Sjsg struct amdgpu_device *adev = ri->ri_hw; 34281bb76ff1Sjsg struct amdgpu_crtc *amdgpu_crtc; 34291bb76ff1Sjsg int i, crtc; 34301bb76ff1Sjsg 34311bb76ff1Sjsg rasops_show_screen(ri, adev->switchcookie, 0, NULL, NULL); 34321bb76ff1Sjsg drm_fb_helper_restore_fbdev_mode_unlocked(adev_to_drm(adev)->fb_helper); 34331bb76ff1Sjsg 34341bb76ff1Sjsg if (adev->switchcb) 34351bb76ff1Sjsg (adev->switchcb)(adev->switchcbarg, 0, 0); 34361bb76ff1Sjsg } 34371bb76ff1Sjsg 34381bb76ff1Sjsg void 34391bb76ff1Sjsg amdgpu_enter_ddb(void *v, void *cookie) 34401bb76ff1Sjsg { 34411bb76ff1Sjsg struct rasops_info *ri = v; 34421bb76ff1Sjsg struct amdgpu_device *adev = ri->ri_hw; 34431bb76ff1Sjsg struct drm_fb_helper *fb_helper = adev_to_drm(adev)->fb_helper; 34441bb76ff1Sjsg 34451bb76ff1Sjsg if (cookie == ri->ri_active) 34461bb76ff1Sjsg return; 34471bb76ff1Sjsg 34481bb76ff1Sjsg rasops_show_screen(ri, cookie, 0, NULL, NULL); 3449f005ef32Sjsg drm_fb_helper_debug_enter(fb_helper->info); 34501bb76ff1Sjsg } 34511bb76ff1Sjsg 34521bb76ff1Sjsg void 34531bb76ff1Sjsg amdgpu_init_backlight(struct amdgpu_device *adev) 34541bb76ff1Sjsg { 34551bb76ff1Sjsg struct drm_device *dev = &adev->ddev; 34561bb76ff1Sjsg struct backlight_device *bd = adev->dm.backlight_dev[0]; 34571bb76ff1Sjsg struct drm_connector_list_iter conn_iter; 34581bb76ff1Sjsg struct drm_connector *connector; 3459a904d29fSjsg struct amdgpu_dm_connector *aconnector; 34601bb76ff1Sjsg 34611bb76ff1Sjsg if (bd == NULL) 34621bb76ff1Sjsg return; 34631bb76ff1Sjsg 34641bb76ff1Sjsg drm_connector_list_iter_begin(dev, &conn_iter); 34651bb76ff1Sjsg drm_for_each_connector_iter(connector, &conn_iter) { 3466a904d29fSjsg aconnector = to_amdgpu_dm_connector(connector); 3467a904d29fSjsg 34684ea48d79Sjsg if (connector->registration_state != DRM_CONNECTOR_REGISTERED) 34694ea48d79Sjsg continue; 34704ea48d79Sjsg 3471a904d29fSjsg if (aconnector->bl_idx == -1) 34721bb76ff1Sjsg continue; 34731bb76ff1Sjsg 34744ea48d79Sjsg dev->registered = false; 34754ea48d79Sjsg connector->registration_state = DRM_CONNECTOR_UNREGISTERED; 34764ea48d79Sjsg 34771bb76ff1Sjsg connector->backlight_device = bd; 34781bb76ff1Sjsg connector->backlight_property = drm_property_create_range(dev, 34791bb76ff1Sjsg 0, "Backlight", 0, bd->props.max_brightness); 34801bb76ff1Sjsg drm_object_attach_property(&connector->base, 34811bb76ff1Sjsg connector->backlight_property, bd->props.brightness); 3482a904d29fSjsg 34834ea48d79Sjsg connector->registration_state = DRM_CONNECTOR_REGISTERED; 34844ea48d79Sjsg dev->registered = true; 34854ea48d79Sjsg 3486a904d29fSjsg break; 34871bb76ff1Sjsg } 34881bb76ff1Sjsg drm_connector_list_iter_end(&conn_iter); 34891bb76ff1Sjsg } 34901bb76ff1Sjsg 34911bb76ff1Sjsg void 34921bb76ff1Sjsg amdgpu_attachhook(struct device *self) 34931bb76ff1Sjsg { 34941bb76ff1Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)self; 34951bb76ff1Sjsg struct drm_device *dev = &adev->ddev; 3496*92465751Sjsg struct pci_dev *pdev = adev->pdev; 34971bb76ff1Sjsg int r, acpi_status; 34981bb76ff1Sjsg struct rasops_info *ri = &adev->ro; 34991bb76ff1Sjsg struct drm_fb_helper *fb_helper; 35001bb76ff1Sjsg struct drm_framebuffer *fb; 35011bb76ff1Sjsg struct drm_gem_object *obj; 35021bb76ff1Sjsg struct amdgpu_bo *rbo; 35031bb76ff1Sjsg 3504*92465751Sjsg pci_set_drvdata(pdev, dev); 3505cc2e793aSkettenis 350621faacacSjsg r = amdgpu_driver_load_kms(adev, adev->flags); 350721faacacSjsg if (r) 35081bb76ff1Sjsg goto out; 35091bb76ff1Sjsg 35101bb76ff1Sjsg /* 35111bb76ff1Sjsg * 1. don't init fbdev on hw without DCE 35121bb76ff1Sjsg * 2. don't init fbdev if there are no connectors 35131bb76ff1Sjsg */ 35141bb76ff1Sjsg if (adev->mode_info.mode_config_initialized && 35151bb76ff1Sjsg !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 35161bb76ff1Sjsg 35171bb76ff1Sjsg /* 35181bb76ff1Sjsg * in linux via amdgpu_pci_probe -> drm_dev_register 3519f81690b7Sjsg * must be before drm_fbdev_generic_setup() 35201bb76ff1Sjsg */ 35211bb76ff1Sjsg drm_dev_register(dev, adev->flags); 35221bb76ff1Sjsg 3523f81690b7Sjsg /* OpenBSD specific backlight property on connector */ 3524f81690b7Sjsg amdgpu_init_backlight(adev); 3525f81690b7Sjsg 35261bb76ff1Sjsg /* select 8 bpp console on low vram cards */ 35271bb76ff1Sjsg if (adev->gmc.real_vram_size <= (32*1024*1024)) 35281bb76ff1Sjsg drm_fbdev_generic_setup(adev_to_drm(adev), 8); 35291bb76ff1Sjsg else 35301bb76ff1Sjsg drm_fbdev_generic_setup(adev_to_drm(adev), 32); 35311bb76ff1Sjsg 35321bb76ff1Sjsg fb_helper = adev_to_drm(adev)->fb_helper; 35331bb76ff1Sjsg if (fb_helper == NULL) { 35341bb76ff1Sjsg printf("fb_helper NULL\n"); 35351bb76ff1Sjsg return; 35361bb76ff1Sjsg } 35371bb76ff1Sjsg fb = fb_helper->fb; 35381bb76ff1Sjsg obj = fb->obj[0]; 35391bb76ff1Sjsg rbo = gem_to_amdgpu_bo(obj); 3540e028d900Skettenis amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM); 35411bb76ff1Sjsg amdgpu_bo_kmap(rbo, (void **)(&ri->ri_bits)); 35421bb76ff1Sjsg 35431bb76ff1Sjsg ri->ri_depth = fb->format->cpp[0] * 8; 35441bb76ff1Sjsg ri->ri_stride = fb->pitches[0]; 3545f005ef32Sjsg ri->ri_width = fb_helper->info->var.xres; 3546f005ef32Sjsg ri->ri_height = fb_helper->info->var.yres; 35471bb76ff1Sjsg 35481bb76ff1Sjsg switch (fb->format->format) { 35491bb76ff1Sjsg case DRM_FORMAT_XRGB8888: 35501bb76ff1Sjsg ri->ri_rnum = 8; 35511bb76ff1Sjsg ri->ri_rpos = 16; 35521bb76ff1Sjsg ri->ri_gnum = 8; 35531bb76ff1Sjsg ri->ri_gpos = 8; 35541bb76ff1Sjsg ri->ri_bnum = 8; 35551bb76ff1Sjsg ri->ri_bpos = 0; 35561bb76ff1Sjsg break; 35571bb76ff1Sjsg case DRM_FORMAT_RGB565: 35581bb76ff1Sjsg ri->ri_rnum = 5; 35591bb76ff1Sjsg ri->ri_rpos = 11; 35601bb76ff1Sjsg ri->ri_gnum = 6; 35611bb76ff1Sjsg ri->ri_gpos = 5; 35621bb76ff1Sjsg ri->ri_bnum = 5; 35631bb76ff1Sjsg ri->ri_bpos = 0; 35641bb76ff1Sjsg break; 35651bb76ff1Sjsg } 35661bb76ff1Sjsg } 35671bb76ff1Sjsg { 35681bb76ff1Sjsg struct wsemuldisplaydev_attach_args aa; 3569bc31cd49Sbentley int orientation_quirk; 35701bb76ff1Sjsg 35711bb76ff1Sjsg task_set(&adev->switchtask, amdgpu_doswitch, ri); 35721bb76ff1Sjsg task_set(&adev->burner_task, amdgpu_burner_cb, adev); 35731bb76ff1Sjsg 35741bb76ff1Sjsg if (ri->ri_bits == NULL) 35751bb76ff1Sjsg return; 35761bb76ff1Sjsg 35771bb76ff1Sjsg ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 3578bc31cd49Sbentley 3579bc31cd49Sbentley orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width, 3580bc31cd49Sbentley ri->ri_height); 3581bc31cd49Sbentley if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP) 3582bc31cd49Sbentley ri->ri_flg |= RI_ROTATE_CCW; 3583bc31cd49Sbentley else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP) 3584bc31cd49Sbentley ri->ri_flg |= RI_ROTATE_CW; 3585bc31cd49Sbentley 35861bb76ff1Sjsg rasops_init(ri, 160, 160); 35871bb76ff1Sjsg 35881bb76ff1Sjsg ri->ri_hw = adev; 35891bb76ff1Sjsg 35901bb76ff1Sjsg amdgpu_stdscreen.capabilities = ri->ri_caps; 35911bb76ff1Sjsg amdgpu_stdscreen.nrows = ri->ri_rows; 35921bb76ff1Sjsg amdgpu_stdscreen.ncols = ri->ri_cols; 35931bb76ff1Sjsg amdgpu_stdscreen.textops = &ri->ri_ops; 35941bb76ff1Sjsg amdgpu_stdscreen.fontwidth = ri->ri_font->fontwidth; 35951bb76ff1Sjsg amdgpu_stdscreen.fontheight = ri->ri_font->fontheight; 35961bb76ff1Sjsg 35971bb76ff1Sjsg aa.console = adev->console; 35981bb76ff1Sjsg aa.primary = adev->primary; 35991bb76ff1Sjsg aa.scrdata = &amdgpu_screenlist; 36001bb76ff1Sjsg aa.accessops = &amdgpu_accessops; 36011bb76ff1Sjsg aa.accesscookie = ri; 36021bb76ff1Sjsg aa.defaultscreens = 0; 36031bb76ff1Sjsg 36041bb76ff1Sjsg if (adev->console) { 36051bb76ff1Sjsg uint32_t defattr; 36061bb76ff1Sjsg 36071bb76ff1Sjsg ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); 36081bb76ff1Sjsg wsdisplay_cnattach(&amdgpu_stdscreen, ri->ri_active, 36091bb76ff1Sjsg ri->ri_ccol, ri->ri_crow, defattr); 36101bb76ff1Sjsg } 36111bb76ff1Sjsg 36121bb76ff1Sjsg /* 36131bb76ff1Sjsg * Now that we've taken over the console, disable decoding of 36141bb76ff1Sjsg * VGA legacy addresses, and opt out of arbitration. 36151bb76ff1Sjsg */ 36161bb76ff1Sjsg amdgpu_asic_set_vga_state(adev, false); 36171bb76ff1Sjsg pci_disable_legacy_vga(&adev->self); 36181bb76ff1Sjsg 36191bb76ff1Sjsg printf("%s: %dx%d, %dbpp\n", adev->self.dv_xname, 36201bb76ff1Sjsg ri->ri_width, ri->ri_height, ri->ri_depth); 36211bb76ff1Sjsg 36221bb76ff1Sjsg config_found_sm(&adev->self, &aa, wsemuldisplaydevprint, 36231bb76ff1Sjsg wsemuldisplaydevsubmatch); 36241bb76ff1Sjsg } 36251bb76ff1Sjsg 36261bb76ff1Sjsg out: 36271bb76ff1Sjsg if (r) { 36281bb76ff1Sjsg amdgpu_fatal_error = 1; 36291bb76ff1Sjsg amdgpu_forcedetach(adev); 36301bb76ff1Sjsg } 36311bb76ff1Sjsg } 36321bb76ff1Sjsg 36331bb76ff1Sjsg /* from amdgpu_exit amdgpu_driver_unload_kms */ 36341bb76ff1Sjsg int 36351bb76ff1Sjsg amdgpu_detach(struct device *self, int flags) 36361bb76ff1Sjsg { 36371bb76ff1Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)self; 36381bb76ff1Sjsg struct drm_device *dev = &adev->ddev; 36391bb76ff1Sjsg 36401bb76ff1Sjsg if (adev == NULL) 36411bb76ff1Sjsg return 0; 36421bb76ff1Sjsg 36431bb76ff1Sjsg amdgpu_refcnt--; 36441bb76ff1Sjsg 36451bb76ff1Sjsg if (amdgpu_refcnt == 0) 36461bb76ff1Sjsg amdgpu_amdkfd_fini(); 36471bb76ff1Sjsg 36481bb76ff1Sjsg pci_intr_disestablish(adev->pc, adev->irqh); 36491bb76ff1Sjsg 36501bb76ff1Sjsg amdgpu_unregister_gpu_instance(adev); 36511bb76ff1Sjsg 36521bb76ff1Sjsg amdgpu_acpi_fini(adev); 36531bb76ff1Sjsg amdgpu_device_fini_hw(adev); 36541bb76ff1Sjsg 36551bb76ff1Sjsg if (amdgpu_refcnt == 0) { 36561bb76ff1Sjsg amdgpu_unregister_atpx_handler(); 36571bb76ff1Sjsg amdgpu_sync_fini(); 36581bb76ff1Sjsg amdgpu_fence_slab_fini(); 36591bb76ff1Sjsg 36601bb76ff1Sjsg drm_sched_fence_slab_fini(); 36611bb76ff1Sjsg } 36621bb76ff1Sjsg 36631bb76ff1Sjsg config_detach(adev->ddev.dev, flags); 36641bb76ff1Sjsg 36651bb76ff1Sjsg return 0; 36661bb76ff1Sjsg } 36671bb76ff1Sjsg 36681bb76ff1Sjsg int 36691bb76ff1Sjsg amdgpu_activate(struct device *self, int act) 36701bb76ff1Sjsg { 36711bb76ff1Sjsg struct amdgpu_device *adev = (struct amdgpu_device *)self; 36721bb76ff1Sjsg struct drm_device *dev = &adev->ddev; 36731bb76ff1Sjsg int rv = 0; 36741bb76ff1Sjsg 3675bd26684bSjsg if (dev->dev == NULL || amdgpu_fatal_error || adev->shutdown) 36761bb76ff1Sjsg return (0); 36771bb76ff1Sjsg 36781bb76ff1Sjsg switch (act) { 36791bb76ff1Sjsg case DVACT_QUIESCE: 36801bb76ff1Sjsg rv = config_activate_children(self, act); 3681cc2e793aSkettenis amdgpu_pmops_prepare(self); 36821046ef31Skettenis if (acpi_softc && acpi_softc->sc_state == ACPI_STATE_S4) 36831046ef31Skettenis amdgpu_pmops_freeze(self); 36841046ef31Skettenis else 3685cc2e793aSkettenis amdgpu_pmops_suspend(self); 36861bb76ff1Sjsg break; 36871bb76ff1Sjsg case DVACT_SUSPEND: 36881046ef31Skettenis if (!acpi_softc || acpi_softc->sc_state != ACPI_STATE_S4) 3689cc2e793aSkettenis amdgpu_pmops_suspend_noirq(self); 36901bb76ff1Sjsg break; 36911bb76ff1Sjsg case DVACT_RESUME: 36921bb76ff1Sjsg break; 36931bb76ff1Sjsg case DVACT_WAKEUP: 36941046ef31Skettenis if (acpi_softc && acpi_softc->sc_state == ACPI_STATE_S4) 36951046ef31Skettenis amdgpu_pmops_restore(self); 36961046ef31Skettenis else 3697cc2e793aSkettenis amdgpu_pmops_resume(self); 36981bb76ff1Sjsg rv = config_activate_children(self, act); 36991bb76ff1Sjsg break; 37001bb76ff1Sjsg } 37011bb76ff1Sjsg 37021bb76ff1Sjsg return (rv); 37031bb76ff1Sjsg } 37041bb76ff1Sjsg 37051bb76ff1Sjsg void 37061bb76ff1Sjsg amdgpu_burner(void *v, u_int on, u_int flags) 37071bb76ff1Sjsg { 37081bb76ff1Sjsg struct rasops_info *ri = v; 37091bb76ff1Sjsg struct amdgpu_device *adev = ri->ri_hw; 37101bb76ff1Sjsg 37111bb76ff1Sjsg task_del(systq, &adev->burner_task); 37121bb76ff1Sjsg 37131bb76ff1Sjsg if (on) 37141bb76ff1Sjsg adev->burner_fblank = FB_BLANK_UNBLANK; 37151bb76ff1Sjsg else { 37161bb76ff1Sjsg if (flags & WSDISPLAY_BURN_VBLANK) 37171bb76ff1Sjsg adev->burner_fblank = FB_BLANK_VSYNC_SUSPEND; 37181bb76ff1Sjsg else 37191bb76ff1Sjsg adev->burner_fblank = FB_BLANK_NORMAL; 37201bb76ff1Sjsg } 37211bb76ff1Sjsg 37221bb76ff1Sjsg /* 37231bb76ff1Sjsg * Setting the DPMS mode may sleep while waiting for vblank so 37241bb76ff1Sjsg * hand things off to a taskq. 37251bb76ff1Sjsg */ 37261bb76ff1Sjsg task_add(systq, &adev->burner_task); 37271bb76ff1Sjsg } 37281bb76ff1Sjsg 37291bb76ff1Sjsg void 37301bb76ff1Sjsg amdgpu_burner_cb(void *arg1) 37311bb76ff1Sjsg { 37321bb76ff1Sjsg struct amdgpu_device *adev = arg1; 37331bb76ff1Sjsg struct drm_fb_helper *helper = adev_to_drm(adev)->fb_helper; 37341bb76ff1Sjsg 3735f005ef32Sjsg drm_fb_helper_blank(adev->burner_fblank, helper->info); 37361bb76ff1Sjsg } 3737