1fb4d8502Sjsg /* 2fb4d8502Sjsg * Copyright 2017 Advanced Micro Devices, Inc. 3fb4d8502Sjsg * 4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"), 6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation 7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions: 10fb4d8502Sjsg * 11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in 12fb4d8502Sjsg * all copies or substantial portions of the Software. 13fb4d8502Sjsg * 14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21fb4d8502Sjsg * 22fb4d8502Sjsg */ 23fb4d8502Sjsg #ifndef __AMDGPU_DISPLAY_H__ 24fb4d8502Sjsg #define __AMDGPU_DISPLAY_H__ 25fb4d8502Sjsg 26c349dbc7Sjsg #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 27c349dbc7Sjsg #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 28c349dbc7Sjsg #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 29c349dbc7Sjsg #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 30c349dbc7Sjsg #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 31c349dbc7Sjsg #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 32c349dbc7Sjsg #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 33c349dbc7Sjsg #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 34c349dbc7Sjsg #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 35c349dbc7Sjsg #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 36c349dbc7Sjsg #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 37c349dbc7Sjsg 38*f005ef32Sjsg void amdgpu_display_hotplug_work_func(struct work_struct *work); 39c349dbc7Sjsg void amdgpu_display_update_priority(struct amdgpu_device *adev); 40c349dbc7Sjsg uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 41c349dbc7Sjsg uint64_t bo_flags); 42fb4d8502Sjsg struct drm_framebuffer * 43fb4d8502Sjsg amdgpu_display_user_framebuffer_create(struct drm_device *dev, 44fb4d8502Sjsg struct drm_file *file_priv, 45fb4d8502Sjsg const struct drm_mode_fb_cmd2 *mode_cmd); 465ca02815Sjsg const struct drm_format_info * 475ca02815Sjsg amdgpu_lookup_format_info(u32 format, uint64_t modifier); 485ca02815Sjsg 495ca02815Sjsg int amdgpu_display_suspend_helper(struct amdgpu_device *adev); 505ca02815Sjsg int amdgpu_display_resume_helper(struct amdgpu_device *adev); 51fb4d8502Sjsg 52fb4d8502Sjsg #endif 53