1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright 2020 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included in 12c349dbc7Sjsg * all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c349dbc7Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c349dbc7Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c349dbc7Sjsg * OTHER DEALINGS IN THE SOFTWARE. 21c349dbc7Sjsg * 22c349dbc7Sjsg */ 23c349dbc7Sjsg 24c349dbc7Sjsg #ifndef __AMDGPU_DF_H__ 25c349dbc7Sjsg #define __AMDGPU_DF_H__ 26c349dbc7Sjsg 27c349dbc7Sjsg struct amdgpu_df_hash_status { 28c349dbc7Sjsg bool hash_64k; 29c349dbc7Sjsg bool hash_2m; 30c349dbc7Sjsg bool hash_1g; 31c349dbc7Sjsg }; 32c349dbc7Sjsg 33c349dbc7Sjsg struct amdgpu_df_funcs { 34c349dbc7Sjsg void (*sw_init)(struct amdgpu_device *adev); 35c349dbc7Sjsg void (*sw_fini)(struct amdgpu_device *adev); 36c349dbc7Sjsg void (*enable_broadcast_mode)(struct amdgpu_device *adev, 37c349dbc7Sjsg bool enable); 38c349dbc7Sjsg u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 39c349dbc7Sjsg u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 40c349dbc7Sjsg void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 41c349dbc7Sjsg bool enable); 42c349dbc7Sjsg void (*get_clockgating_state)(struct amdgpu_device *adev, 43*1bb76ff1Sjsg u64 *flags); 44c349dbc7Sjsg void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 45c349dbc7Sjsg bool enable); 46c349dbc7Sjsg int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 475ca02815Sjsg int counter_idx, int is_add); 48c349dbc7Sjsg int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 495ca02815Sjsg int counter_idx, int is_remove); 50c349dbc7Sjsg void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 515ca02815Sjsg int counter_idx, uint64_t *count); 52c349dbc7Sjsg uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); 53c349dbc7Sjsg void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, 54c349dbc7Sjsg uint32_t ficadl_val, uint32_t ficadh_val); 55*1bb76ff1Sjsg bool (*query_ras_poison_mode)(struct amdgpu_device *adev); 56c349dbc7Sjsg }; 57c349dbc7Sjsg 58c349dbc7Sjsg struct amdgpu_df { 59c349dbc7Sjsg struct amdgpu_df_hash_status hash_status; 60c349dbc7Sjsg const struct amdgpu_df_funcs *funcs; 61c349dbc7Sjsg }; 62c349dbc7Sjsg 63c349dbc7Sjsg #endif /* __AMDGPU_DF_H__ */ 64