xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_csa.c (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
1c349dbc7Sjsg /*
2c349dbc7Sjsg  * Copyright 2016 Advanced Micro Devices, Inc.
3c349dbc7Sjsg  *
4c349dbc7Sjsg  * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg  * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg  * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg  * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg  * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg  *
11c349dbc7Sjsg  * The above copyright notice and this permission notice shall be included in
12c349dbc7Sjsg  * all copies or substantial portions of the Software.
13c349dbc7Sjsg  *
14c349dbc7Sjsg  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15c349dbc7Sjsg  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16c349dbc7Sjsg  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17c349dbc7Sjsg  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18c349dbc7Sjsg  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19c349dbc7Sjsg  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20c349dbc7Sjsg  * OTHER DEALINGS IN THE SOFTWARE.
21c349dbc7Sjsg 
22c349dbc7Sjsg  * * Author: Monk.liu@amd.com
23c349dbc7Sjsg  */
24c349dbc7Sjsg 
25*f005ef32Sjsg #include <drm/drm_exec.h>
26*f005ef32Sjsg 
27c349dbc7Sjsg #include "amdgpu.h"
28c349dbc7Sjsg 
amdgpu_csa_vaddr(struct amdgpu_device * adev)29c349dbc7Sjsg uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
30c349dbc7Sjsg {
31c349dbc7Sjsg 	uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
32c349dbc7Sjsg 
33c349dbc7Sjsg 	addr -= AMDGPU_VA_RESERVED_SIZE;
34c349dbc7Sjsg 	addr = amdgpu_gmc_sign_extend(addr);
35c349dbc7Sjsg 
36c349dbc7Sjsg 	return addr;
37c349dbc7Sjsg }
38c349dbc7Sjsg 
amdgpu_allocate_static_csa(struct amdgpu_device * adev,struct amdgpu_bo ** bo,u32 domain,uint32_t size)39c349dbc7Sjsg int amdgpu_allocate_static_csa(struct amdgpu_device *adev, struct amdgpu_bo **bo,
40c349dbc7Sjsg 				u32 domain, uint32_t size)
41c349dbc7Sjsg {
42c349dbc7Sjsg 	void *ptr;
43c349dbc7Sjsg 
445ca02815Sjsg 	amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
45c349dbc7Sjsg 				domain, bo,
46c349dbc7Sjsg 				NULL, &ptr);
47c349dbc7Sjsg 	if (!*bo)
48c349dbc7Sjsg 		return -ENOMEM;
49c349dbc7Sjsg 
50c349dbc7Sjsg 	memset(ptr, 0, size);
51c349dbc7Sjsg 	adev->virt.csa_cpu_addr = ptr;
52c349dbc7Sjsg 	return 0;
53c349dbc7Sjsg }
54c349dbc7Sjsg 
amdgpu_free_static_csa(struct amdgpu_bo ** bo)55c349dbc7Sjsg void amdgpu_free_static_csa(struct amdgpu_bo **bo)
56c349dbc7Sjsg {
57c349dbc7Sjsg 	amdgpu_bo_free_kernel(bo, NULL, NULL);
58c349dbc7Sjsg }
59c349dbc7Sjsg 
60c349dbc7Sjsg /*
61c349dbc7Sjsg  * amdgpu_map_static_csa should be called during amdgpu_vm_init
62c349dbc7Sjsg  * it maps virtual address amdgpu_csa_vaddr() to this VM, and each command
63c349dbc7Sjsg  * submission of GFX should use this virtual address within META_DATA init
64c349dbc7Sjsg  * package to support SRIOV gfx preemption.
65c349dbc7Sjsg  */
amdgpu_map_static_csa(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo * bo,struct amdgpu_bo_va ** bo_va,uint64_t csa_addr,uint32_t size)66c349dbc7Sjsg int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
67c349dbc7Sjsg 			  struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
68c349dbc7Sjsg 			  uint64_t csa_addr, uint32_t size)
69c349dbc7Sjsg {
70*f005ef32Sjsg 	struct drm_exec exec;
71c349dbc7Sjsg 	int r;
72c349dbc7Sjsg 
73*f005ef32Sjsg 	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
74*f005ef32Sjsg 	drm_exec_until_all_locked(&exec) {
75*f005ef32Sjsg 		r = amdgpu_vm_lock_pd(vm, &exec, 0);
76*f005ef32Sjsg 		if (likely(!r))
77*f005ef32Sjsg 			r = drm_exec_lock_obj(&exec, &bo->tbo.base);
78*f005ef32Sjsg 		drm_exec_retry_on_contention(&exec);
79*f005ef32Sjsg 		if (unlikely(r)) {
80c349dbc7Sjsg 			DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
81*f005ef32Sjsg 			goto error;
82*f005ef32Sjsg 		}
83c349dbc7Sjsg 	}
84c349dbc7Sjsg 
85c349dbc7Sjsg 	*bo_va = amdgpu_vm_bo_add(adev, vm, bo);
86c349dbc7Sjsg 	if (!*bo_va) {
87*f005ef32Sjsg 		r = -ENOMEM;
88*f005ef32Sjsg 		goto error;
89c349dbc7Sjsg 	}
90c349dbc7Sjsg 
91c349dbc7Sjsg 	r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, size,
92c349dbc7Sjsg 			     AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
93c349dbc7Sjsg 			     AMDGPU_PTE_EXECUTABLE);
94c349dbc7Sjsg 
95c349dbc7Sjsg 	if (r) {
96c349dbc7Sjsg 		DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
971bb76ff1Sjsg 		amdgpu_vm_bo_del(adev, *bo_va);
98*f005ef32Sjsg 		goto error;
99*f005ef32Sjsg 	}
100*f005ef32Sjsg 
101*f005ef32Sjsg error:
102*f005ef32Sjsg 	drm_exec_fini(&exec);
103c349dbc7Sjsg 	return r;
104c349dbc7Sjsg }
105c349dbc7Sjsg 
amdgpu_unmap_static_csa(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo * bo,struct amdgpu_bo_va * bo_va,uint64_t csa_addr)106*f005ef32Sjsg int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
107*f005ef32Sjsg 			    struct amdgpu_bo *bo, struct amdgpu_bo_va *bo_va,
108*f005ef32Sjsg 			    uint64_t csa_addr)
109*f005ef32Sjsg {
110*f005ef32Sjsg 	struct drm_exec exec;
111*f005ef32Sjsg 	int r;
112*f005ef32Sjsg 
113*f005ef32Sjsg 	drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT);
114*f005ef32Sjsg 	drm_exec_until_all_locked(&exec) {
115*f005ef32Sjsg 		r = amdgpu_vm_lock_pd(vm, &exec, 0);
116*f005ef32Sjsg 		if (likely(!r))
117*f005ef32Sjsg 			r = drm_exec_lock_obj(&exec, &bo->tbo.base);
118*f005ef32Sjsg 		drm_exec_retry_on_contention(&exec);
119*f005ef32Sjsg 		if (unlikely(r)) {
120*f005ef32Sjsg 			DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
121*f005ef32Sjsg 			goto error;
122*f005ef32Sjsg 		}
123*f005ef32Sjsg 	}
124*f005ef32Sjsg 
125*f005ef32Sjsg 	r = amdgpu_vm_bo_unmap(adev, bo_va, csa_addr);
126*f005ef32Sjsg 	if (r) {
127*f005ef32Sjsg 		DRM_ERROR("failed to do bo_unmap on static CSA, err=%d\n", r);
128*f005ef32Sjsg 		goto error;
129*f005ef32Sjsg 	}
130*f005ef32Sjsg 
131*f005ef32Sjsg 	amdgpu_vm_bo_del(adev, bo_va);
132*f005ef32Sjsg 
133*f005ef32Sjsg error:
134*f005ef32Sjsg 	drm_exec_fini(&exec);
135*f005ef32Sjsg 	return r;
136c349dbc7Sjsg }
137