1 /* $OpenBSD: cz.c,v 1.5 2002/01/30 20:45:34 nordin Exp $ */ 2 /* $NetBSD: cz.c,v 1.15 2001/01/20 19:10:36 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 2000 Zembu Labs, Inc. 6 * All rights reserved. 7 * 8 * Authors: Jason R. Thorpe <thorpej@zembu.com> 9 * Bill Studenmund <wrstuden@zembu.com> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Zembu Labs, Inc. 22 * 4. Neither the name of Zembu Labs nor the names of its employees may 23 * be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS 27 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR- 28 * RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS- 29 * CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT, 30 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Cyclades-Z series multi-port serial adapter driver for NetBSD. 40 * 41 * Some notes: 42 * 43 * - The Cyclades-Z has fully automatic hardware (and software!) 44 * flow control. We only utilize RTS/CTS flow control here, 45 * and it is implemented in a very simplistic manner. This 46 * may be an area of future work. 47 * 48 * - The PLX can map the either the board's RAM or host RAM 49 * into the MIPS's memory window. This would enable us to 50 * use less expensive (for us) memory reads/writes to host 51 * RAM, rather than time-consuming reads/writes to PCI 52 * memory space. However, the PLX can only map a 0-128M 53 * window, so we would have to ensure that the DMA address 54 * of the host RAM fits there. This is kind of a pain, 55 * so we just don't bother right now. 56 * 57 * - In a perfect world, we would use the autoconfiguration 58 * mechanism to attach the TTYs that we find. However, 59 * that leads to somewhat icky looking autoconfiguration 60 * messages (one for every TTY, up to 64 per board!). So 61 * we don't do it that way, but assign minors as if there 62 * were the max of 64 ports per board. 63 * 64 * - We don't bother with PPS support here. There are so many 65 * ports, each with a large amount of buffer space, that the 66 * normal mode of operation is to poll the boards regularly 67 * (generally, every 20ms or so). This makes this driver 68 * unsuitable for PPS, as the latency will be generally too 69 * high. 70 */ 71 /* 72 * This driver inspired by the FreeBSD driver written by Brian J. McGovern 73 * for FreeBSD 3.2. 74 */ 75 76 #include <sys/param.h> 77 #include <sys/systm.h> 78 #include <sys/proc.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/tty.h> 82 #include <sys/conf.h> 83 #include <sys/time.h> 84 #include <sys/kernel.h> 85 #include <sys/fcntl.h> 86 #include <sys/syslog.h> 87 88 #include <dev/pci/pcireg.h> 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcidevs.h> 91 #include <dev/pci/czreg.h> 92 93 #include <dev/pci/plx9060reg.h> 94 #include <dev/pci/plx9060var.h> 95 96 #include <dev/microcode/cyclades/cyzfirm.h> 97 98 #define CZ_DRIVER_VERSION 0x20000411 99 100 #define CZ_POLL_MS 20 101 102 /* These are the interrupts we always use. */ 103 #define CZ_INTERRUPTS \ 104 (C_IN_MDSR | C_IN_MRI | C_IN_MRTS | C_IN_MCTS | C_IN_TXBEMPTY | \ 105 C_IN_TXFEMPTY | C_IN_TXLOWWM | C_IN_RXHIWM | C_IN_RXNNDT | \ 106 C_IN_MDCD | C_IN_PR_ERROR | C_IN_FR_ERROR | C_IN_OVR_ERROR | \ 107 C_IN_RXOFL | C_IN_IOCTLW | C_IN_RXBRK) 108 109 /* 110 * cztty_softc: 111 * 112 * Per-channel (TTY) state. 113 */ 114 struct cztty_softc { 115 struct cz_softc *sc_parent; 116 struct tty *sc_tty; 117 118 struct timeout sc_diag_to; 119 120 int sc_channel; /* Also used to flag unattached chan */ 121 #define CZTTY_CHANNEL_DEAD -1 122 123 bus_space_tag_t sc_chan_st; /* channel space tag */ 124 bus_space_handle_t sc_chan_sh; /* channel space handle */ 125 bus_space_handle_t sc_buf_sh; /* buffer space handle */ 126 127 u_int sc_overflows, 128 sc_parity_errors, 129 sc_framing_errors, 130 sc_errors; 131 132 int sc_swflags; 133 134 u_int32_t sc_rs_control_dtr, 135 sc_chanctl_hw_flow, 136 sc_chanctl_comm_baud, 137 sc_chanctl_rs_control, 138 sc_chanctl_comm_data_l, 139 sc_chanctl_comm_parity; 140 }; 141 142 /* 143 * cz_softc: 144 * 145 * Per-board state. 146 */ 147 struct cz_softc { 148 struct device cz_dev; /* generic device info */ 149 struct plx9060_config cz_plx; /* PLX 9060 config info */ 150 bus_space_tag_t cz_win_st; /* window space tag */ 151 bus_space_handle_t cz_win_sh; /* window space handle */ 152 struct timeout cz_timeout; /* timeout for polling-mode */ 153 154 void *cz_ih; /* interrupt handle */ 155 156 u_int32_t cz_mailbox0; /* our MAILBOX0 value */ 157 int cz_nchannels; /* number of channels */ 158 int cz_nopenchan; /* number of open channels */ 159 struct cztty_softc *cz_ports; /* our array of ports */ 160 161 bus_addr_t cz_fwctl; /* offset of firmware control */ 162 }; 163 164 int cz_match(struct device *, void *, void *); 165 void cz_attach(struct device *, struct device *, void *); 166 int cz_wait_pci_doorbell(struct cz_softc *, char *); 167 168 struct cfattach cz_ca = { 169 sizeof(struct cz_softc), cz_match, cz_attach 170 }; 171 172 void cz_reset_board(struct cz_softc *); 173 int cz_load_firmware(struct cz_softc *); 174 175 int cz_intr(void *); 176 void cz_poll(void *); 177 int cztty_transmit(struct cztty_softc *, struct tty *); 178 int cztty_receive(struct cztty_softc *, struct tty *); 179 180 struct cztty_softc * cztty_getttysoftc(dev_t dev); 181 int cztty_findmajor(void); 182 int cztty_major; 183 int cztty_attached_ttys; 184 int cz_timeout_ticks; 185 186 cdev_decl(cztty); 187 188 void czttystart(struct tty *tp); 189 int czttyparam(struct tty *tp, struct termios *t); 190 void cztty_shutdown(struct cztty_softc *sc); 191 void cztty_modem(struct cztty_softc *sc, int onoff); 192 void cztty_break(struct cztty_softc *sc, int onoff); 193 void tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits); 194 int cztty_to_tiocm(struct cztty_softc *sc); 195 void cztty_diag(void *arg); 196 197 struct cfdriver cz_cd = { 198 0, "cz", DV_TTY 199 }; 200 201 /* 202 * Macros to read and write the PLX. 203 */ 204 #define CZ_PLX_READ(cz, reg) \ 205 bus_space_read_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, (reg)) 206 #define CZ_PLX_WRITE(cz, reg, val) \ 207 bus_space_write_4((cz)->cz_plx.plx_st, (cz)->cz_plx.plx_sh, \ 208 (reg), (val)) 209 210 /* 211 * Macros to read and write the FPGA. We must already be in the FPGA 212 * window for this. 213 */ 214 #define CZ_FPGA_READ(cz, reg) \ 215 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg)) 216 #define CZ_FPGA_WRITE(cz, reg, val) \ 217 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, (reg), (val)) 218 219 /* 220 * Macros to read and write the firmware control structures in board RAM. 221 */ 222 #define CZ_FWCTL_READ(cz, off) \ 223 bus_space_read_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 224 (cz)->cz_fwctl + (off)) 225 226 #define CZ_FWCTL_WRITE(cz, off, val) \ 227 bus_space_write_4((cz)->cz_win_st, (cz)->cz_win_sh, \ 228 (cz)->cz_fwctl + (off), (val)) 229 230 /* 231 * Convenience macros for cztty routines. PLX window MUST be to RAM. 232 */ 233 #define CZTTY_CHAN_READ(sc, off) \ 234 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_chan_sh, (off)) 235 236 #define CZTTY_CHAN_WRITE(sc, off, val) \ 237 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_chan_sh, \ 238 (off), (val)) 239 240 #define CZTTY_BUF_READ(sc, off) \ 241 bus_space_read_4((sc)->sc_chan_st, (sc)->sc_buf_sh, (off)) 242 243 #define CZTTY_BUF_WRITE(sc, off, val) \ 244 bus_space_write_4((sc)->sc_chan_st, (sc)->sc_buf_sh, \ 245 (off), (val)) 246 247 /* 248 * Convenience macros. 249 */ 250 #define CZ_WIN_RAM(cz) \ 251 do { \ 252 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_RAM); \ 253 delay(100); \ 254 } while (0) 255 256 #define CZ_WIN_FPGA(cz) \ 257 do { \ 258 CZ_PLX_WRITE((cz), PLX_LAS0BA, LOCAL_ADDR0_FPGA); \ 259 delay(100); \ 260 } while (0) 261 262 /***************************************************************************** 263 * Cyclades-Z controller code starts here... 264 *****************************************************************************/ 265 266 /* 267 * cz_match: 268 * 269 * Determine if the given PCI device is a Cyclades-Z board. 270 */ 271 int 272 cz_match(parent, match, aux) 273 struct device *parent; 274 void *match, *aux; 275 { 276 struct pci_attach_args *pa = aux; 277 278 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYCLADES) { 279 switch (PCI_PRODUCT(pa->pa_id)) { 280 case PCI_PRODUCT_CYCLADES_CYCLOMZ_2: 281 return (1); 282 } 283 } 284 285 return (0); 286 } 287 288 /* 289 * cz_attach: 290 * 291 * A Cyclades-Z board was found; attach it. 292 */ 293 void 294 cz_attach(parent, self, aux) 295 struct device *parent, *self; 296 void *aux; 297 { 298 struct cz_softc *cz = (void *) self; 299 struct pci_attach_args *pa = aux; 300 pci_chipset_tag_t pc = pa->pa_pc; 301 pci_intr_handle_t ih; 302 const char *intrstr = NULL; 303 struct cztty_softc *sc; 304 struct tty *tp; 305 int i; 306 307 printf(": Cyclades-Z multiport serial\n"); 308 309 cz->cz_plx.plx_pc = pa->pa_pc; 310 cz->cz_plx.plx_tag = pa->pa_tag; 311 312 if (pci_mapreg_map(pa, PLX_PCI_RUNTIME_MEMADDR, 313 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 314 &cz->cz_plx.plx_st, &cz->cz_plx.plx_sh, NULL, NULL, 0) != 0) { 315 printf("%s: unable to map PLX registers\n", 316 cz->cz_dev.dv_xname); 317 return; 318 } 319 if (pci_mapreg_map(pa, PLX_PCI_LOCAL_ADDR0, 320 PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0, 321 &cz->cz_win_st, &cz->cz_win_sh, NULL, NULL, 0) != 0) { 322 printf("%s: unable to map device window\n", 323 cz->cz_dev.dv_xname); 324 return; 325 } 326 327 cz->cz_mailbox0 = CZ_PLX_READ(cz, PLX_MAILBOX0); 328 cz->cz_nopenchan = 0; 329 330 /* 331 * Make sure that the board is completely stopped. 332 */ 333 CZ_WIN_FPGA(cz); 334 CZ_FPGA_WRITE(cz, FPGA_CPU_STOP, 0); 335 336 /* 337 * Load the board's firmware. 338 */ 339 if (cz_load_firmware(cz) != 0) 340 return; 341 342 /* 343 * Now that we're ready to roll, map and establish the interrupt 344 * handler. 345 */ 346 if (pci_intr_map(pa, &ih) != 0) { 347 /* 348 * The common case is for Cyclades-Z boards to run 349 * in polling mode, and thus not have an interrupt 350 * mapped for them. Don't bother reporting that 351 * the interrupt is not mappable, since this isn't 352 * really an error. 353 */ 354 cz->cz_ih = NULL; 355 goto polling_mode; 356 } else { 357 intrstr = pci_intr_string(pa->pa_pc, ih); 358 cz->cz_ih = pci_intr_establish(pc, ih, IPL_TTY, 359 cz_intr, cz, cz->cz_dev.dv_xname); 360 } 361 if (cz->cz_ih == NULL) { 362 printf("%s: unable to establish interrupt", 363 cz->cz_dev.dv_xname); 364 if (intrstr != NULL) 365 printf(" at %s", intrstr); 366 printf("\n"); 367 /* We will fall-back on polling mode. */ 368 } else 369 printf("%s: interrupting at %s\n", 370 cz->cz_dev.dv_xname, intrstr); 371 372 polling_mode: 373 if (cz->cz_ih == NULL) { 374 timeout_set(&cz->cz_timeout, cz_poll, cz); 375 if (cz_timeout_ticks == 0) 376 cz_timeout_ticks = max(1, hz * CZ_POLL_MS / 1000); 377 printf("%s: polling mode, %d ms interval (%d tick%s)\n", 378 cz->cz_dev.dv_xname, CZ_POLL_MS, cz_timeout_ticks, 379 cz_timeout_ticks == 1 ? "" : "s"); 380 } 381 382 if (cztty_major == 0) 383 cztty_major = cztty_findmajor(); 384 /* 385 * Allocate sufficient pointers for the children and 386 * attach them. Set all ports to a reasonable initial 387 * configuration while we're at it: 388 * 389 * disabled 390 * 8N1 391 * default baud rate 392 * hardware flow control. 393 */ 394 CZ_WIN_RAM(cz); 395 396 if (cz->cz_nchannels == 0) { 397 /* No channels? No more work to do! */ 398 return; 399 } 400 401 cz->cz_ports = malloc(sizeof(struct cztty_softc) * cz->cz_nchannels, 402 M_DEVBUF, M_WAITOK); 403 cztty_attached_ttys += cz->cz_nchannels; 404 memset(cz->cz_ports, 0, 405 sizeof(struct cztty_softc) * cz->cz_nchannels); 406 407 for (i = 0; i < cz->cz_nchannels; i++) { 408 sc = &cz->cz_ports[i]; 409 410 sc->sc_channel = i; 411 sc->sc_chan_st = cz->cz_win_st; 412 sc->sc_parent = cz; 413 414 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 415 cz->cz_fwctl + ZFIRM_CHNCTL_OFF(i, 0), 416 ZFIRM_CHNCTL_SIZE, &sc->sc_chan_sh)) { 417 printf("%s: unable to subregion channel %d control\n", 418 cz->cz_dev.dv_xname, i); 419 sc->sc_channel = CZTTY_CHANNEL_DEAD; 420 continue; 421 } 422 if (bus_space_subregion(cz->cz_win_st, cz->cz_win_sh, 423 cz->cz_fwctl + ZFIRM_BUFCTL_OFF(i, 0), 424 ZFIRM_BUFCTL_SIZE, &sc->sc_buf_sh)) { 425 printf("%s: unable to subregion channel %d buffer\n", 426 cz->cz_dev.dv_xname, i); 427 sc->sc_channel = CZTTY_CHANNEL_DEAD; 428 continue; 429 } 430 431 timeout_set(&sc->sc_diag_to, cztty_diag, sc); 432 433 tp = ttymalloc(); 434 tp->t_dev = makedev(cztty_major, 435 (cz->cz_dev.dv_unit * ZFIRM_MAX_CHANNELS) + i); 436 tp->t_oproc = czttystart; 437 tp->t_param = czttyparam; 438 tty_attach(tp); 439 440 sc->sc_tty = tp; 441 442 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 443 CZTTY_CHAN_WRITE(sc, CHNCTL_INTR_ENABLE, CZ_INTERRUPTS); 444 CZTTY_CHAN_WRITE(sc, CHNCTL_SW_FLOW, 0); 445 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XON, 0x11); 446 CZTTY_CHAN_WRITE(sc, CHNCTL_FLOW_XOFF, 0x13); 447 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, TTYDEF_SPEED); 448 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, C_PR_NONE); 449 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, C_DL_CS8 | C_DL_1STOP); 450 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_FLAGS, 0); 451 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, C_RS_CTS | C_RS_RTS); 452 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, 0); 453 } 454 } 455 456 /* 457 * cz_reset_board: 458 * 459 * Reset the board via the PLX. 460 */ 461 void 462 cz_reset_board(struct cz_softc *cz) 463 { 464 u_int32_t reg; 465 466 reg = CZ_PLX_READ(cz, PLX_CONTROL); 467 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_SWR); 468 delay(1000); 469 470 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 471 delay(1000); 472 473 /* Now reload the PLX from its EEPROM. */ 474 reg = CZ_PLX_READ(cz, PLX_CONTROL); 475 CZ_PLX_WRITE(cz, PLX_CONTROL, reg | CONTROL_RELOADCFG); 476 delay(1000); 477 CZ_PLX_WRITE(cz, PLX_CONTROL, reg); 478 } 479 480 /* 481 * cz_load_firmware: 482 * 483 * Load the ZFIRM firmware into the board's RAM and start it 484 * running. 485 */ 486 int 487 cz_load_firmware(struct cz_softc *cz) 488 { 489 struct zfirm_header *zfh; 490 struct zfirm_config *zfc; 491 struct zfirm_block *zfb, *zblocks; 492 const u_int8_t *cp; 493 const char *board; 494 u_int32_t fid; 495 int i, j, nconfigs, nblocks, nbytes; 496 497 zfh = (struct zfirm_header *) cycladesz_firmware; 498 499 /* Find the config header. */ 500 if (letoh32(zfh->zfh_configoff) & (sizeof(u_int32_t) - 1)) { 501 printf("%s: bad ZFIRM config offset: 0x%x\n", 502 cz->cz_dev.dv_xname, letoh32(zfh->zfh_configoff)); 503 return (EIO); 504 } 505 zfc = (struct zfirm_config *)(cycladesz_firmware + 506 letoh32(zfh->zfh_configoff)); 507 nconfigs = letoh32(zfh->zfh_nconfig); 508 509 /* Locate the correct configuration for our board. */ 510 for (i = 0; i < nconfigs; i++, zfc++) { 511 if (letoh32(zfc->zfc_mailbox) == cz->cz_mailbox0 && 512 letoh32(zfc->zfc_function) == ZFC_FUNCTION_NORMAL) 513 break; 514 } 515 if (i == nconfigs) { 516 printf("%s: unable to locate config header\n", 517 cz->cz_dev.dv_xname); 518 return (EIO); 519 } 520 521 nblocks = letoh32(zfc->zfc_nblocks); 522 zblocks = (struct zfirm_block *)(cycladesz_firmware + 523 letoh32(zfh->zfh_blockoff)); 524 525 /* 526 * 8Zo ver. 1 doesn't have an FPGA. Load it on all others if 527 * necessary. 528 */ 529 if (cz->cz_mailbox0 != MAILBOX0_8Zo_V1 530 #if 0 531 && ((CZ_PLX_READ(cz, PLX_CONTROL) & CONTROL_FPGA_LOADED) == 0) 532 #endif 533 ) { 534 #ifdef CZ_DEBUG 535 printf("%s: Loading FPGA...", cz->cz_dev.dv_xname); 536 #endif 537 CZ_WIN_FPGA(cz); 538 for (i = 0; i < nblocks; i++) { 539 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 540 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 541 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FPGA) { 542 nbytes = letoh32(zfb->zfb_size); 543 cp = &cycladesz_firmware[ 544 letoh32(zfb->zfb_fileoff)]; 545 for (j = 0; j < nbytes; j++, cp++) { 546 bus_space_write_1(cz->cz_win_st, 547 cz->cz_win_sh, 0, *cp); 548 /* FPGA needs 30-100us to settle. */ 549 delay(10); 550 } 551 } 552 } 553 #ifdef CZ_DEBUG 554 printf("done\n"); 555 #endif 556 } 557 558 /* Now load the firmware. */ 559 CZ_WIN_RAM(cz); 560 561 for (i = 0; i < nblocks; i++) { 562 /* zfb = zblocks + letoh32(zfc->zfc_blocklist[i]) ?? */ 563 zfb = &zblocks[letoh32(zfc->zfc_blocklist[i])]; 564 if (letoh32(zfb->zfb_type) == ZFB_TYPE_FIRMWARE) { 565 const u_int32_t *lp; 566 u_int32_t ro = letoh32(zfb->zfb_ramoff); 567 nbytes = letoh32(zfb->zfb_size); 568 lp = (const u_int32_t *) 569 &cycladesz_firmware[letoh32(zfb->zfb_fileoff)]; 570 for (j = 0; j < nbytes; j += 4, lp++) { 571 bus_space_write_4(cz->cz_win_st, cz->cz_win_sh, 572 ro + j, letoh32(*lp)); 573 delay(10); 574 } 575 } 576 } 577 578 /* Now restart the MIPS. */ 579 CZ_WIN_FPGA(cz); 580 CZ_FPGA_WRITE(cz, FPGA_CPU_START, 0); 581 582 /* Wait for the MIPS to start, then report the results. */ 583 CZ_WIN_RAM(cz); 584 585 #ifdef CZ_DEBUG 586 printf("%s: waiting for MIPS to start", cz->cz_dev.dv_xname); 587 #endif 588 for (i = 0; i < 100; i++) { 589 fid = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 590 ZFIRM_SIG_OFF); 591 if (fid == ZFIRM_SIG) { 592 /* MIPS has booted. */ 593 break; 594 } else if (fid == ZFIRM_HLT) { 595 /* 596 * The MIPS has halted, usually due to a power 597 * shortage on the expansion module. 598 */ 599 printf("%s: MIPS halted; possible power supply " 600 "problem\n", cz->cz_dev.dv_xname); 601 return (EIO); 602 } else { 603 #ifdef CZ_DEBUG 604 if ((i % 8) == 0) 605 printf("."); 606 #endif 607 delay(250000); 608 } 609 } 610 #ifdef CZ_DEBUG 611 printf("\n"); 612 #endif 613 if (i == 100) { 614 CZ_WIN_FPGA(cz); 615 printf("%s: MIPS failed to start; wanted 0x%08x got 0x%08x\n", 616 cz->cz_dev.dv_xname, ZFIRM_SIG, fid); 617 printf("%s: FPGA ID 0x%08x, FPGA version 0x%08x\n", 618 cz->cz_dev.dv_xname, CZ_FPGA_READ(cz, FPGA_ID), 619 CZ_FPGA_READ(cz, FPGA_VERSION)); 620 return (EIO); 621 } 622 623 /* 624 * Locate the firmware control structures. 625 */ 626 cz->cz_fwctl = bus_space_read_4(cz->cz_win_st, cz->cz_win_sh, 627 ZFIRM_CTRLADDR_OFF); 628 #ifdef CZ_DEBUG 629 printf("%s: FWCTL structure at offset 0x%08lx\n", 630 cz->cz_dev.dv_xname, cz->cz_fwctl); 631 #endif 632 633 CZ_FWCTL_WRITE(cz, BRDCTL_C_OS, C_OS_BSD); 634 CZ_FWCTL_WRITE(cz, BRDCTL_DRVERSION, CZ_DRIVER_VERSION); 635 636 cz->cz_nchannels = CZ_FWCTL_READ(cz, BRDCTL_NCHANNEL); 637 638 switch (cz->cz_mailbox0) { 639 case MAILBOX0_8Zo_V1: 640 board = "Cyclades-8Zo ver. 1"; 641 break; 642 643 case MAILBOX0_8Zo_V2: 644 board = "Cyclades-8Zo ver. 2"; 645 break; 646 647 case MAILBOX0_Ze_V1: 648 board = "Cyclades-Ze"; 649 break; 650 651 default: 652 board = "unknown Cyclades Z-series"; 653 break; 654 } 655 656 fid = CZ_FWCTL_READ(cz, BRDCTL_FWVERSION); 657 printf("%s: %s, ", cz->cz_dev.dv_xname, board); 658 if (cz->cz_nchannels == 0) 659 printf("no channels attached, "); 660 else 661 printf("%d channels (ttyCZ%04d..ttyCZ%04d), ", 662 cz->cz_nchannels, cztty_attached_ttys, 663 cztty_attached_ttys + (cz->cz_nchannels - 1)); 664 printf("firmware %x.%x.%x\n", 665 (fid >> 8) & 0xf, (fid >> 4) & 0xf, fid & 0xf); 666 667 return (0); 668 } 669 670 /* 671 * cz_poll: 672 * 673 * This card doesn't do interrupts, so scan it for activity every CZ_POLL_MS 674 * ms. 675 */ 676 void 677 cz_poll(void *arg) 678 { 679 int s = spltty(); 680 struct cz_softc *cz = arg; 681 682 cz_intr(cz); 683 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 684 685 splx(s); 686 } 687 688 /* 689 * cz_intr: 690 * 691 * Interrupt service routine. 692 * 693 * We either are receiving an interrupt directly from the board, or we are 694 * in polling mode and it's time to poll. 695 */ 696 int 697 cz_intr(void *arg) 698 { 699 int rval = 0; 700 u_int command, channel, param; 701 struct cz_softc *cz = arg; 702 struct cztty_softc *sc; 703 struct tty *tp; 704 705 while ((command = (CZ_PLX_READ(cz, PLX_LOCAL_PCI_DOORBELL) & 0xff))) { 706 rval = 1; 707 channel = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_CHANNEL); 708 param = CZ_FWCTL_READ(cz, BRDCTL_FWCMD_PARAM); 709 710 /* now clear this interrupt, posslibly enabling another */ 711 CZ_PLX_WRITE(cz, PLX_LOCAL_PCI_DOORBELL, command); 712 713 if (cz->cz_ports == NULL) { 714 #ifdef CZ_DEBUG 715 printf("%s: interrupt on channel %d, but no channels\n", 716 cz->cz_dev.dv_xname, channel); 717 #endif 718 continue; 719 } 720 721 sc = &cz->cz_ports[channel]; 722 723 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 724 break; 725 726 tp = sc->sc_tty; 727 728 switch (command) { 729 case C_CM_TXFEMPTY: /* transmit cases */ 730 case C_CM_TXBEMPTY: 731 case C_CM_TXLOWWM: 732 case C_CM_INTBACK: 733 if (!ISSET(tp->t_state, TS_ISOPEN)) { 734 #ifdef CZ_DEBUG 735 printf("%s: tx intr on closed channel %d\n", 736 cz->cz_dev.dv_xname, channel); 737 #endif 738 break; 739 } 740 741 if (cztty_transmit(sc, tp)) { 742 /* 743 * Do wakeup stuff here. 744 */ 745 ttwakeup(tp); 746 wakeup(tp); 747 } 748 break; 749 750 case C_CM_RXNNDT: /* receive cases */ 751 case C_CM_RXHIWM: 752 case C_CM_INTBACK2: /* from restart ?? */ 753 #if 0 754 case C_CM_ICHAR: 755 #endif 756 if (!ISSET(tp->t_state, TS_ISOPEN)) { 757 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 758 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 759 break; 760 } 761 762 if (cztty_receive(sc, tp)) { 763 /* 764 * Do wakeup stuff here. 765 */ 766 ttwakeup(tp); 767 wakeup(tp); 768 } 769 break; 770 771 case C_CM_MDCD: 772 if (!ISSET(tp->t_state, TS_ISOPEN)) 773 break; 774 775 (void) (*linesw[tp->t_line].l_modem)(tp, 776 ISSET(C_RS_DCD, CZTTY_CHAN_READ(sc, 777 CHNCTL_RS_STATUS))); 778 break; 779 780 case C_CM_MDSR: 781 case C_CM_MRI: 782 case C_CM_MCTS: 783 case C_CM_MRTS: 784 break; 785 786 case C_CM_IOCTLW: 787 break; 788 789 case C_CM_PR_ERROR: 790 sc->sc_parity_errors++; 791 goto error_common; 792 793 case C_CM_FR_ERROR: 794 sc->sc_framing_errors++; 795 goto error_common; 796 797 case C_CM_OVR_ERROR: 798 sc->sc_overflows++; 799 error_common: 800 if (sc->sc_errors++ == 0) 801 timeout_add(&sc->sc_diag_to, 60 * hz); 802 break; 803 804 case C_CM_RXBRK: 805 if (!ISSET(tp->t_state, TS_ISOPEN)) 806 break; 807 808 /* 809 * A break is a \000 character with TTY_FE error 810 * flags set. So TTY_FE by itself works. 811 */ 812 (*linesw[tp->t_line].l_rint)(TTY_FE, tp); 813 ttwakeup(tp); 814 wakeup(tp); 815 break; 816 817 default: 818 #ifdef CZ_DEBUG 819 printf("%s: channel %d: Unknown interrupt 0x%x\n", 820 cz->cz_dev.dv_xname, sc->sc_channel, command); 821 #endif 822 break; 823 } 824 } 825 826 return (rval); 827 } 828 829 /* 830 * cz_wait_pci_doorbell: 831 * 832 * Wait for the pci doorbell to be clear - wait for pending 833 * activity to drain. 834 */ 835 int 836 cz_wait_pci_doorbell(struct cz_softc *cz, char *wstring) 837 { 838 int error; 839 840 while (CZ_PLX_READ(cz, PLX_PCI_LOCAL_DOORBELL)) { 841 error = tsleep(cz, TTIPRI | PCATCH, wstring, max(1, hz/100)); 842 if ((error != 0) && (error != EWOULDBLOCK)) 843 return (error); 844 } 845 return (0); 846 } 847 848 /***************************************************************************** 849 * Cyclades-Z TTY code starts here... 850 *****************************************************************************/ 851 852 #define CZTTYDIALOUT_MASK 0x80 853 854 #define CZTTY_DIALOUT(dev) (minor((dev)) & CZTTYDIALOUT_MASK) 855 #define CZTTY_CZ(sc) ((sc)->sc_parent) 856 857 #define CZTTY_SOFTC(dev) cztty_getttysoftc(dev) 858 859 struct cztty_softc * 860 cztty_getttysoftc(dev_t dev) 861 { 862 int i, j, k, u = minor(dev) & ~CZTTYDIALOUT_MASK; 863 struct cz_softc *cz; 864 865 for (i = 0, j = 0; i < cz_cd.cd_ndevs; i++) { 866 k = j; 867 cz = (struct cz_softc *)device_lookup(&cz_cd, i); 868 if (cz == NULL) 869 continue; 870 if (cz->cz_ports == NULL) 871 continue; 872 j += cz->cz_nchannels; 873 if (j > u) 874 break; 875 } 876 877 if (i >= cz_cd.cd_ndevs) 878 return (NULL); 879 else 880 return (&cz->cz_ports[u - k]); 881 } 882 883 int 884 cztty_findmajor(void) 885 { 886 int maj; 887 888 for (maj = 0; maj < nchrdev; maj++) { 889 if (cdevsw[maj].d_open == czttyopen) 890 break; 891 } 892 893 return (maj == nchrdev) ? 0 : maj; 894 } 895 896 /* 897 * czttytty: 898 * 899 * Return a pointer to our tty. 900 */ 901 struct tty * 902 czttytty(dev_t dev) 903 { 904 struct cztty_softc *sc = CZTTY_SOFTC(dev); 905 906 #ifdef DIAGNOSTIC 907 if (sc == NULL) 908 panic("czttytty"); 909 #endif 910 911 return (sc->sc_tty); 912 } 913 914 /* 915 * cztty_shutdown: 916 * 917 * Shut down a port. 918 */ 919 void 920 cztty_shutdown(struct cztty_softc *sc) 921 { 922 struct cz_softc *cz = CZTTY_CZ(sc); 923 struct tty *tp = sc->sc_tty; 924 int s; 925 926 s = spltty(); 927 928 /* Clear any break condition set with TIOCSBRK. */ 929 cztty_break(sc, 0); 930 931 /* 932 * Hang up if necessary. Wait a bit, so the other side has time to 933 * notice even if we immediately open the port again. 934 */ 935 if (ISSET(tp->t_cflag, HUPCL)) { 936 cztty_modem(sc, 0); 937 (void) tsleep(tp, TTIPRI, ttclos, hz); 938 } 939 940 /* Disable the channel. */ 941 cz_wait_pci_doorbell(cz, "czdis"); 942 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_DISABLE); 943 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 944 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTL); 945 946 if ((--cz->cz_nopenchan == 0) && (cz->cz_ih == NULL)) { 947 #ifdef CZ_DEBUG 948 printf("%s: Disabling polling\n", cz->cz_dev.dv_xname); 949 #endif 950 timeout_del(&cz->cz_timeout); 951 } 952 953 splx(s); 954 } 955 956 /* 957 * czttyopen: 958 * 959 * Open a Cyclades-Z serial port. 960 */ 961 int 962 czttyopen(dev_t dev, int flags, int mode, struct proc *p) 963 { 964 struct cztty_softc *sc = CZTTY_SOFTC(dev); 965 struct cz_softc *cz; 966 struct tty *tp; 967 int s, error; 968 969 if (sc == NULL) 970 return (ENXIO); 971 972 if (sc->sc_channel == CZTTY_CHANNEL_DEAD) 973 return (ENXIO); 974 975 cz = CZTTY_CZ(sc); 976 tp = sc->sc_tty; 977 978 if (ISSET(tp->t_state, TS_ISOPEN) && 979 ISSET(tp->t_state, TS_XCLUDE) && 980 p->p_ucred->cr_uid != 0) 981 return (EBUSY); 982 983 s = spltty(); 984 985 /* 986 * Do the following iff this is a first open. 987 */ 988 if (!ISSET(tp->t_state, TS_ISOPEN)) { 989 struct termios t; 990 991 tp->t_dev = dev; 992 993 /* If we're turning things on, enable interrupts */ 994 if ((cz->cz_nopenchan++ == 0) && (cz->cz_ih == NULL)) { 995 #ifdef CZ_DEBUG 996 printf("%s: Enabling polling.\n", 997 cz->cz_dev.dv_xname); 998 #endif 999 timeout_add(&cz->cz_timeout, cz_timeout_ticks); 1000 } 1001 1002 /* 1003 * Enable the channel. Don't actually ring the 1004 * doorbell here; czttyparam() will do it for us. 1005 */ 1006 cz_wait_pci_doorbell(cz, "czopen"); 1007 1008 CZTTY_CHAN_WRITE(sc, CHNCTL_OP_MODE, C_CH_ENABLE); 1009 1010 /* 1011 * Initialize the termios status to the defaults. Add in the 1012 * sticky bits from TIOCSFLAGS. 1013 */ 1014 t.c_ispeed = 0; 1015 t.c_ospeed = TTYDEF_SPEED; 1016 t.c_cflag = TTYDEF_CFLAG; 1017 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1018 SET(t.c_cflag, CLOCAL); 1019 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1020 SET(t.c_cflag, CRTSCTS); 1021 1022 /* 1023 * Reset the input and output rings. Do this before 1024 * we call czttyparam(), as that function enables 1025 * the channel. 1026 */ 1027 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, 1028 CZTTY_BUF_READ(sc, BUFCTL_RX_PUT)); 1029 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, 1030 CZTTY_BUF_READ(sc, BUFCTL_TX_GET)); 1031 1032 /* Make sure czttyparam() will see changes. */ 1033 tp->t_ospeed = 0; 1034 (void) czttyparam(tp, &t); 1035 tp->t_iflag = TTYDEF_IFLAG; 1036 tp->t_oflag = TTYDEF_OFLAG; 1037 tp->t_lflag = TTYDEF_LFLAG; 1038 ttychars(tp); 1039 ttsetwater(tp); 1040 1041 /* 1042 * Turn on DTR. We must always do this, even if carrier is not 1043 * present, because otherwise we'd have to use TIOCSDTR 1044 * immediately after setting CLOCAL, which applications do not 1045 * expect. We always assert DTR while the device is open 1046 * unless explicitly requested to deassert it. 1047 */ 1048 cztty_modem(sc, 1); 1049 } 1050 1051 splx(s); 1052 1053 error = ttyopen(CZTTY_DIALOUT(dev), tp); 1054 if (error) 1055 goto bad; 1056 1057 error = (*linesw[tp->t_line].l_open)(dev, tp); 1058 if (error) 1059 goto bad; 1060 1061 return (0); 1062 1063 bad: 1064 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1065 /* 1066 * We failed to open the device, and nobody else had it opened. 1067 * Clean up the state as appropriate. 1068 */ 1069 cztty_shutdown(sc); 1070 } 1071 1072 return (error); 1073 } 1074 1075 /* 1076 * czttyclose: 1077 * 1078 * Close a Cyclades-Z serial port. 1079 */ 1080 int 1081 czttyclose(dev_t dev, int flags, int mode, struct proc *p) 1082 { 1083 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1084 struct tty *tp = sc->sc_tty; 1085 1086 /* XXX This is for cons.c. */ 1087 if (!ISSET(tp->t_state, TS_ISOPEN)) 1088 return (0); 1089 1090 (*linesw[tp->t_line].l_close)(tp, flags); 1091 ttyclose(tp); 1092 1093 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1094 /* 1095 * Although we got a last close, the device may still be in 1096 * use; e.g. if this was the dialout node, and there are still 1097 * processes waiting for carrier on the non-dialout node. 1098 */ 1099 cztty_shutdown(sc); 1100 } 1101 1102 return (0); 1103 } 1104 1105 /* 1106 * czttyread: 1107 * 1108 * Read from a Cyclades-Z serial port. 1109 */ 1110 int 1111 czttyread(dev_t dev, struct uio *uio, int flags) 1112 { 1113 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1114 struct tty *tp = sc->sc_tty; 1115 1116 return ((*linesw[tp->t_line].l_read)(tp, uio, flags)); 1117 } 1118 1119 /* 1120 * czttywrite: 1121 * 1122 * Write to a Cyclades-Z serial port. 1123 */ 1124 int 1125 czttywrite(dev_t dev, struct uio *uio, int flags) 1126 { 1127 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1128 struct tty *tp = sc->sc_tty; 1129 1130 return ((*linesw[tp->t_line].l_write)(tp, uio, flags)); 1131 } 1132 1133 #if 0 1134 /* 1135 * czttypoll: 1136 * 1137 * Poll a Cyclades-Z serial port. 1138 */ 1139 int 1140 czttypoll(dev_t dev, int events, struct proc p) 1141 { 1142 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1143 struct tty *tp = sc->sc_tty; 1144 1145 return ((*linesw[tp->t_line].l_poll)(tp, events, p)); 1146 } 1147 #endif 1148 1149 /* 1150 * czttyioctl: 1151 * 1152 * Perform a control operation on a Cyclades-Z serial port. 1153 */ 1154 int 1155 czttyioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 1156 { 1157 struct cztty_softc *sc = CZTTY_SOFTC(dev); 1158 struct tty *tp = sc->sc_tty; 1159 int s, error; 1160 1161 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 1162 if (error >= 0) 1163 return (error); 1164 1165 error = ttioctl(tp, cmd, data, flag, p); 1166 if (error >= 0) 1167 return (error); 1168 1169 error = 0; 1170 1171 s = spltty(); 1172 1173 switch (cmd) { 1174 case TIOCSBRK: 1175 cztty_break(sc, 1); 1176 break; 1177 1178 case TIOCCBRK: 1179 cztty_break(sc, 0); 1180 break; 1181 1182 case TIOCGFLAGS: 1183 *(int *)data = sc->sc_swflags; 1184 break; 1185 1186 case TIOCSFLAGS: 1187 error = suser(p->p_ucred, &p->p_acflag); 1188 if (error) 1189 break; 1190 sc->sc_swflags = *(int *)data; 1191 break; 1192 1193 case TIOCSDTR: 1194 cztty_modem(sc, 1); 1195 break; 1196 1197 case TIOCCDTR: 1198 cztty_modem(sc, 0); 1199 break; 1200 1201 case TIOCMSET: 1202 case TIOCMBIS: 1203 case TIOCMBIC: 1204 tiocm_to_cztty(sc, cmd, *(int *)data); 1205 break; 1206 1207 case TIOCMGET: 1208 *(int *)data = cztty_to_tiocm(sc); 1209 break; 1210 1211 default: 1212 error = ENOTTY; 1213 break; 1214 } 1215 1216 splx(s); 1217 1218 return (error); 1219 } 1220 1221 /* 1222 * cztty_break: 1223 * 1224 * Set or clear BREAK on a port. 1225 */ 1226 void 1227 cztty_break(struct cztty_softc *sc, int onoff) 1228 { 1229 struct cz_softc *cz = CZTTY_CZ(sc); 1230 1231 cz_wait_pci_doorbell(cz, "czbreak"); 1232 1233 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1234 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, 1235 onoff ? C_CM_SET_BREAK : C_CM_CLR_BREAK); 1236 } 1237 1238 /* 1239 * cztty_modem: 1240 * 1241 * Set or clear DTR on a port. 1242 */ 1243 void 1244 cztty_modem(struct cztty_softc *sc, int onoff) 1245 { 1246 struct cz_softc *cz = CZTTY_CZ(sc); 1247 1248 if (sc->sc_rs_control_dtr == 0) 1249 return; 1250 1251 cz_wait_pci_doorbell(cz, "czmod"); 1252 1253 if (onoff) 1254 sc->sc_chanctl_rs_control |= sc->sc_rs_control_dtr; 1255 else 1256 sc->sc_chanctl_rs_control &= ~sc->sc_rs_control_dtr; 1257 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1258 1259 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1260 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1261 } 1262 1263 /* 1264 * tiocm_to_cztty: 1265 * 1266 * Process TIOCM* ioctls. 1267 */ 1268 void 1269 tiocm_to_cztty(struct cztty_softc *sc, u_long how, int ttybits) 1270 { 1271 struct cz_softc *cz = CZTTY_CZ(sc); 1272 u_int32_t czttybits; 1273 1274 czttybits = 0; 1275 if (ISSET(ttybits, TIOCM_DTR)) 1276 SET(czttybits, C_RS_DTR); 1277 if (ISSET(ttybits, TIOCM_RTS)) 1278 SET(czttybits, C_RS_RTS); 1279 1280 cz_wait_pci_doorbell(cz, "cztiocm"); 1281 1282 switch (how) { 1283 case TIOCMBIC: 1284 CLR(sc->sc_chanctl_rs_control, czttybits); 1285 break; 1286 1287 case TIOCMBIS: 1288 SET(sc->sc_chanctl_rs_control, czttybits); 1289 break; 1290 1291 case TIOCMSET: 1292 CLR(sc->sc_chanctl_rs_control, C_RS_DTR | C_RS_RTS); 1293 SET(sc->sc_chanctl_rs_control, czttybits); 1294 break; 1295 } 1296 1297 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1298 1299 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1300 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1301 } 1302 1303 /* 1304 * cztty_to_tiocm: 1305 * 1306 * Process the TIOCMGET ioctl. 1307 */ 1308 int 1309 cztty_to_tiocm(struct cztty_softc *sc) 1310 { 1311 struct cz_softc *cz = CZTTY_CZ(sc); 1312 u_int32_t rs_status, op_mode; 1313 int ttybits = 0; 1314 1315 cz_wait_pci_doorbell(cz, "cztty"); 1316 1317 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1318 op_mode = CZTTY_CHAN_READ(sc, CHNCTL_OP_MODE); 1319 1320 if (ISSET(rs_status, C_RS_RTS)) 1321 SET(ttybits, TIOCM_RTS); 1322 if (ISSET(rs_status, C_RS_CTS)) 1323 SET(ttybits, TIOCM_CTS); 1324 if (ISSET(rs_status, C_RS_DCD)) 1325 SET(ttybits, TIOCM_CAR); 1326 if (ISSET(rs_status, C_RS_DTR)) 1327 SET(ttybits, TIOCM_DTR); 1328 if (ISSET(rs_status, C_RS_RI)) 1329 SET(ttybits, TIOCM_RNG); 1330 if (ISSET(rs_status, C_RS_DSR)) 1331 SET(ttybits, TIOCM_DSR); 1332 1333 if (ISSET(op_mode, C_CH_ENABLE)) 1334 SET(ttybits, TIOCM_LE); 1335 1336 return (ttybits); 1337 } 1338 1339 /* 1340 * czttyparam: 1341 * 1342 * Set Cyclades-Z serial port parameters from termios. 1343 * 1344 * XXX Should just copy the whole termios after making 1345 * XXX sure all the changes could be done. 1346 */ 1347 int 1348 czttyparam(struct tty *tp, struct termios *t) 1349 { 1350 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1351 struct cz_softc *cz = CZTTY_CZ(sc); 1352 u_int32_t rs_status; 1353 int ospeed, cflag; 1354 1355 ospeed = t->c_ospeed; 1356 cflag = t->c_cflag; 1357 1358 /* Check requested parameters. */ 1359 if (ospeed < 0) 1360 return (EINVAL); 1361 if (t->c_ispeed && t->c_ispeed != ospeed) 1362 return (EINVAL); 1363 1364 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR)) { 1365 SET(cflag, CLOCAL); 1366 CLR(cflag, HUPCL); 1367 } 1368 1369 /* 1370 * If there were no changes, don't do anything. This avoids dropping 1371 * input and improves performance when all we did was frob things like 1372 * VMIN and VTIME. 1373 */ 1374 if (tp->t_ospeed == ospeed && 1375 tp->t_cflag == cflag) 1376 return (0); 1377 1378 /* Data bits. */ 1379 sc->sc_chanctl_comm_data_l = 0; 1380 switch (t->c_cflag & CSIZE) { 1381 case CS5: 1382 sc->sc_chanctl_comm_data_l |= C_DL_CS5; 1383 break; 1384 1385 case CS6: 1386 sc->sc_chanctl_comm_data_l |= C_DL_CS6; 1387 break; 1388 1389 case CS7: 1390 sc->sc_chanctl_comm_data_l |= C_DL_CS7; 1391 break; 1392 1393 case CS8: 1394 sc->sc_chanctl_comm_data_l |= C_DL_CS8; 1395 break; 1396 } 1397 1398 /* Stop bits. */ 1399 if (t->c_cflag & CSTOPB) { 1400 if ((sc->sc_chanctl_comm_data_l & C_DL_CS) == C_DL_CS5) 1401 sc->sc_chanctl_comm_data_l |= C_DL_15STOP; 1402 else 1403 sc->sc_chanctl_comm_data_l |= C_DL_2STOP; 1404 } else 1405 sc->sc_chanctl_comm_data_l |= C_DL_1STOP; 1406 1407 /* Parity. */ 1408 if (t->c_cflag & PARENB) { 1409 if (t->c_cflag & PARODD) 1410 sc->sc_chanctl_comm_parity = C_PR_ODD; 1411 else 1412 sc->sc_chanctl_comm_parity = C_PR_EVEN; 1413 } else 1414 sc->sc_chanctl_comm_parity = C_PR_NONE; 1415 1416 /* 1417 * Initialize flow control pins depending on the current flow control 1418 * mode. 1419 */ 1420 if (ISSET(t->c_cflag, CRTSCTS)) { 1421 sc->sc_rs_control_dtr = C_RS_DTR; 1422 sc->sc_chanctl_hw_flow = C_RS_CTS | C_RS_RTS; 1423 } else if (ISSET(t->c_cflag, MDMBUF)) { 1424 sc->sc_rs_control_dtr = 0; 1425 sc->sc_chanctl_hw_flow = C_RS_DCD | C_RS_DTR; 1426 } else { 1427 /* 1428 * If no flow control, then always set RTS. This will make 1429 * the other side happy if it mistakenly thinks we're doing 1430 * RTS/CTS flow control. 1431 */ 1432 sc->sc_rs_control_dtr = C_RS_DTR | C_RS_RTS; 1433 sc->sc_chanctl_hw_flow = 0; 1434 if (ISSET(sc->sc_chanctl_rs_control, C_RS_DTR)) 1435 SET(sc->sc_chanctl_rs_control, C_RS_RTS); 1436 else 1437 CLR(sc->sc_chanctl_rs_control, C_RS_RTS); 1438 } 1439 1440 /* Baud rate. */ 1441 sc->sc_chanctl_comm_baud = ospeed; 1442 1443 /* Copy to tty. */ 1444 tp->t_ispeed = 0; 1445 tp->t_ospeed = t->c_ospeed; 1446 tp->t_cflag = t->c_cflag; 1447 1448 /* 1449 * Now load the channel control structure. 1450 */ 1451 1452 cz_wait_pci_doorbell(cz, "czparam"); 1453 1454 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_BAUD, sc->sc_chanctl_comm_baud); 1455 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_DATA_L, sc->sc_chanctl_comm_data_l); 1456 CZTTY_CHAN_WRITE(sc, CHNCTL_COMM_PARITY, sc->sc_chanctl_comm_parity); 1457 CZTTY_CHAN_WRITE(sc, CHNCTL_HW_FLOW, sc->sc_chanctl_hw_flow); 1458 CZTTY_CHAN_WRITE(sc, CHNCTL_RS_CONTROL, sc->sc_chanctl_rs_control); 1459 1460 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1461 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLW); 1462 1463 cz_wait_pci_doorbell(cz, "czparam"); 1464 1465 CZ_FWCTL_WRITE(cz, BRDCTL_HCMD_CHANNEL, sc->sc_channel); 1466 CZ_PLX_WRITE(cz, PLX_PCI_LOCAL_DOORBELL, C_CM_IOCTLM); 1467 1468 cz_wait_pci_doorbell(cz, "czparam"); 1469 1470 /* 1471 * Update the tty layer's idea of the carrier bit, in case we changed 1472 * CLOCAL. We don't hang up here; we only do that by explicit 1473 * request. 1474 */ 1475 rs_status = CZTTY_CHAN_READ(sc, CHNCTL_RS_STATUS); 1476 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(rs_status, C_RS_DCD)); 1477 1478 return (0); 1479 } 1480 1481 /* 1482 * czttystart: 1483 * 1484 * Start or restart transmission. 1485 */ 1486 void 1487 czttystart(struct tty *tp) 1488 { 1489 struct cztty_softc *sc = CZTTY_SOFTC(tp->t_dev); 1490 int s; 1491 1492 s = spltty(); 1493 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1494 goto out; 1495 1496 if (tp->t_outq.c_cc <= tp->t_lowat) { 1497 if (ISSET(tp->t_state, TS_ASLEEP)) { 1498 CLR(tp->t_state, TS_ASLEEP); 1499 wakeup(&tp->t_outq); 1500 } 1501 selwakeup(&tp->t_wsel); 1502 if (tp->t_outq.c_cc == 0) 1503 goto out; 1504 } 1505 1506 cztty_transmit(sc, tp); 1507 out: 1508 splx(s); 1509 } 1510 1511 /* 1512 * czttystop: 1513 * 1514 * Stop output, e.g., for ^S or output flush. 1515 */ 1516 int 1517 czttystop(struct tty *tp, int flag) 1518 { 1519 1520 /* 1521 * XXX We don't do anything here, yet. Mostly, I don't know 1522 * XXX exactly how this should be implemented on this device. 1523 * XXX We've given a big chunk of data to the MIPS already, 1524 * XXX and I don't know how we request the MIPS to stop sending 1525 * XXX the data. So, punt for now. --thorpej 1526 */ 1527 return (0); 1528 } 1529 1530 /* 1531 * cztty_diag: 1532 * 1533 * Issue a scheduled diagnostic message. 1534 */ 1535 void 1536 cztty_diag(void *arg) 1537 { 1538 struct cztty_softc *sc = arg; 1539 struct cz_softc *cz = CZTTY_CZ(sc); 1540 u_int overflows, parity_errors, framing_errors; 1541 int s; 1542 1543 s = spltty(); 1544 1545 overflows = sc->sc_overflows; 1546 sc->sc_overflows = 0; 1547 1548 parity_errors = sc->sc_parity_errors; 1549 sc->sc_parity_errors = 0; 1550 1551 framing_errors = sc->sc_framing_errors; 1552 sc->sc_framing_errors = 0; 1553 1554 sc->sc_errors = 0; 1555 1556 splx(s); 1557 1558 log(LOG_WARNING, 1559 "%s: channel %d: %u overflow%s, %u parity, %u framing error%s\n", 1560 cz->cz_dev.dv_xname, sc->sc_channel, 1561 overflows, overflows == 1 ? "" : "s", 1562 parity_errors, 1563 framing_errors, framing_errors == 1 ? "" : "s"); 1564 } 1565 1566 /* 1567 * tx and rx ring buffer size macros: 1568 * 1569 * The transmitter and receiver both use ring buffers. For each one, there 1570 * is a get (consumer) and a put (producer) offset. The get value is the 1571 * next byte to be read from the ring, and the put is the next one to be 1572 * put into the ring. get == put means the ring is empty. 1573 * 1574 * For each ring, the firmware controls one of (get, put) and this driver 1575 * controls the other. For transmission, this driver updates put to point 1576 * past the valid data, and the firmware moves get as bytes are sent. Likewise 1577 * for receive, the driver controls put, and this driver controls get. 1578 */ 1579 #define TX_MOVEABLE(g, p, s) (((g) > (p)) ? ((g) - (p) - 1) : ((s) - (p))) 1580 #define RX_MOVEABLE(g, p, s) (((g) > (p)) ? ((s) - (g)) : ((p) - (g))) 1581 1582 /* 1583 * cztty_transmit() 1584 * 1585 * Look at the tty for this port and start sending. 1586 */ 1587 int 1588 cztty_transmit(struct cztty_softc *sc, struct tty *tp) 1589 { 1590 struct cz_softc *cz = CZTTY_CZ(sc); 1591 u_int move, get, put, size, address; 1592 #ifdef HOSTRAMCODE 1593 int error, done = 0; 1594 #else 1595 int done = 0; 1596 #endif 1597 1598 size = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFSIZE); 1599 get = CZTTY_BUF_READ(sc, BUFCTL_TX_GET); 1600 put = CZTTY_BUF_READ(sc, BUFCTL_TX_PUT); 1601 address = CZTTY_BUF_READ(sc, BUFCTL_TX_BUFADDR); 1602 1603 while ((tp->t_outq.c_cc > 0) && ((move = TX_MOVEABLE(get, put, size)))){ 1604 #ifdef HOSTRAMCODE 1605 if (0) { 1606 move = min(tp->t_outq.c_cc, move); 1607 error = q_to_b(&tp->t_outq, 0, move); 1608 if (error != move) { 1609 printf("%s: channel %d: error moving to " 1610 "transmit buf\n", cz->cz_dev.dv_xname, 1611 sc->sc_channel); 1612 move = error; 1613 } 1614 } else { 1615 #endif 1616 move = min(ndqb(&tp->t_outq, 0), move); 1617 bus_space_write_region_1(cz->cz_win_st, cz->cz_win_sh, 1618 address + put, tp->t_outq.c_cf, move); 1619 ndflush(&tp->t_outq, move); 1620 #ifdef HOSTRAMCODE 1621 } 1622 #endif 1623 1624 put = ((put + move) % size); 1625 done = 1; 1626 } 1627 if (done) { 1628 CZTTY_BUF_WRITE(sc, BUFCTL_TX_PUT, put); 1629 } 1630 return (done); 1631 } 1632 1633 int 1634 cztty_receive(struct cztty_softc *sc, struct tty *tp) 1635 { 1636 struct cz_softc *cz = CZTTY_CZ(sc); 1637 u_int get, put, size, address; 1638 int done = 0, ch; 1639 1640 size = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFSIZE); 1641 get = CZTTY_BUF_READ(sc, BUFCTL_RX_GET); 1642 put = CZTTY_BUF_READ(sc, BUFCTL_RX_PUT); 1643 address = CZTTY_BUF_READ(sc, BUFCTL_RX_BUFADDR); 1644 1645 while ((get != put) && ((tp->t_canq.c_cc + tp->t_rawq.c_cc) < tp->t_hiwat)) { 1646 #ifdef HOSTRAMCODE 1647 if (hostram) 1648 ch = ((char *)fifoaddr)[get]; 1649 } else { 1650 #endif 1651 ch = bus_space_read_1(cz->cz_win_st, cz->cz_win_sh, 1652 address + get); 1653 #ifdef HOSTRAMCODE 1654 } 1655 #endif 1656 (*linesw[tp->t_line].l_rint)(ch, tp); 1657 get = (get + 1) % size; 1658 done = 1; 1659 } 1660 if (done) { 1661 CZTTY_BUF_WRITE(sc, BUFCTL_RX_GET, get); 1662 } 1663 return (done); 1664 } 1665