1 /* $OpenBSD: rtsx.c,v 1.5 2013/11/06 13:51:02 stsp Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Realtek RTS5209/RTS5229 Card Reader driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/kthread.h> 28 #include <sys/systm.h> 29 30 #include <dev/ic/rtsxreg.h> 31 #include <dev/ic/rtsxvar.h> 32 #include <dev/sdmmc/sdmmcvar.h> 33 #include <dev/sdmmc/sdmmc_ioreg.h> 34 35 /* 36 * We use two DMA buffers, a command buffer and a data buffer. 37 * 38 * The command buffer contains a command queue for the host controller, 39 * which describes SD/MMC commands to run, and other parameters. The chip 40 * runs the command queue when a special bit in the RTSX_HCBAR register is set 41 * and signals completion with the TRANS_OK interrupt. 42 * Each command is encoded as a 4 byte sequence containing command number 43 * (read, write, or check a host controller register), a register address, 44 * and a data bit-mask and value. 45 * 46 * The data buffer is used to transfer data sectors to or from the SD card. 47 * Data transfer is controlled via the RTSX_HDBAR register. Completion is 48 * also signalled by the TRANS_OK interrupt. 49 * 50 * The chip is unable to perform DMA above 4GB. 51 * 52 * SD/MMC commands which do not transfer any data from/to the card only use 53 * the command buffer. 54 */ 55 56 #define RTSX_DMA_MAX_SEGSIZE 0x80000 57 #define RTSX_HOSTCMD_MAX 256 58 #define RTSX_HOSTCMD_BUFSIZE (sizeof(u_int32_t) * RTSX_HOSTCMD_MAX) 59 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 60 61 #define READ4(sc, reg) \ 62 (bus_space_read_4((sc)->iot, (sc)->ioh, (reg))) 63 #define WRITE4(sc, reg, val) \ 64 bus_space_write_4((sc)->iot, (sc)->ioh, (reg), (val)) 65 66 #define RTSX_READ(sc, reg, val) \ 67 do { \ 68 int err = rtsx_read((sc), (reg), (val)); \ 69 if (err) \ 70 return (err); \ 71 } while (0) 72 73 #define RTSX_WRITE(sc, reg, val) \ 74 do { \ 75 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 76 if (err) \ 77 return (err); \ 78 } while (0) 79 80 #define RTSX_CLR(sc, reg, bits) \ 81 do { \ 82 int err = rtsx_write((sc), (reg), (bits), 0); \ 83 if (err) \ 84 return (err); \ 85 } while (0) 86 87 #define RTSX_SET(sc, reg, bits) \ 88 do { \ 89 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 90 if (err) \ 91 return (err); \ 92 } while (0) 93 94 int rtsx_host_reset(sdmmc_chipset_handle_t); 95 u_int32_t rtsx_host_ocr(sdmmc_chipset_handle_t); 96 int rtsx_host_maxblklen(sdmmc_chipset_handle_t); 97 int rtsx_card_detect(sdmmc_chipset_handle_t); 98 int rtsx_bus_power(sdmmc_chipset_handle_t, u_int32_t); 99 int rtsx_bus_clock(sdmmc_chipset_handle_t, int); 100 void rtsx_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *); 101 int rtsx_init(struct rtsx_softc *, int); 102 void rtsx_soft_reset(struct rtsx_softc *); 103 int rtsx_bus_power_off(struct rtsx_softc *); 104 int rtsx_bus_power_on(struct rtsx_softc *); 105 int rtsx_set_bus_width(struct rtsx_softc *, int); 106 int rtsx_stop_sd_clock(struct rtsx_softc *); 107 int rtsx_switch_sd_clock(struct rtsx_softc *, u_int8_t, int, int); 108 int rtsx_wait_intr(struct rtsx_softc *, int, int); 109 int rtsx_read(struct rtsx_softc *, u_int16_t, u_int8_t *); 110 int rtsx_write(struct rtsx_softc *, u_int16_t, u_int8_t, u_int8_t); 111 #ifdef notyet 112 int rtsx_read_phy(struct rtsx_softc *, u_int8_t, u_int16_t *); 113 #endif 114 int rtsx_write_phy(struct rtsx_softc *, u_int8_t, u_int16_t); 115 int rtsx_read_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t *); 116 #ifdef notyet 117 int rtsx_write_cfg(struct rtsx_softc *, u_int8_t, u_int16_t, u_int32_t, 118 u_int32_t); 119 #endif 120 void rtsx_hostcmd(u_int32_t *, int *, u_int8_t, u_int16_t, u_int8_t, 121 u_int8_t); 122 int rtsx_hostcmd_send(struct rtsx_softc *, int); 123 u_int8_t rtsx_response_type(u_int16_t); 124 int rtsx_xfer(struct rtsx_softc *, struct sdmmc_command *, u_int32_t *); 125 void rtsx_card_insert(struct rtsx_softc *); 126 void rtsx_card_eject(struct rtsx_softc *); 127 int rtsx_led_enable(struct rtsx_softc *); 128 int rtsx_led_disable(struct rtsx_softc *); 129 void rtsx_save_regs(struct rtsx_softc *); 130 void rtsx_restore_regs(struct rtsx_softc *); 131 132 #ifdef RTSX_DEBUG 133 int rtsxdebug = 0; 134 #define DPRINTF(n,s) do { if ((n) <= rtsxdebug) printf s; } while (0) 135 #else 136 #define DPRINTF(n,s) do {} while(0) 137 #endif 138 139 struct sdmmc_chip_functions rtsx_functions = { 140 /* host controller reset */ 141 rtsx_host_reset, 142 /* host controller capabilities */ 143 rtsx_host_ocr, 144 rtsx_host_maxblklen, 145 /* card detection */ 146 rtsx_card_detect, 147 /* bus power and clock frequency */ 148 rtsx_bus_power, 149 rtsx_bus_clock, 150 /* command execution */ 151 rtsx_exec_command, 152 /* card interrupt */ 153 NULL, NULL 154 }; 155 156 struct cfdriver rtsx_cd = { 157 NULL, "rtsx", DV_DULL 158 }; 159 160 /* 161 * Called by attachment driver. 162 */ 163 int 164 rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot, 165 bus_space_handle_t ioh, bus_size_t iosize, bus_dma_tag_t dmat, int flags) 166 { 167 struct sdmmcbus_attach_args saa; 168 u_int32_t sdio_cfg; 169 170 sc->iot = iot; 171 sc->ioh = ioh; 172 sc->dmat = dmat; 173 sc->flags = flags; 174 175 if (rtsx_init(sc, 1)) 176 return 1; 177 178 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg)) { 179 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 180 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 181 sc->flags |= RTSX_F_SDIO_SUPPORT; 182 } 183 184 if (bus_dmamap_create(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 1, 185 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 186 &sc->dmap_cmd) != 0) 187 return 1; 188 if (bus_dmamap_create(sc->dmat, RTSX_DMA_DATA_BUFSIZE, 1, 189 RTSX_DMA_MAX_SEGSIZE, 0, BUS_DMA_NOWAIT, 190 &sc->dmap_data) != 0) 191 return 1; 192 193 /* 194 * Attach the generic SD/MMC bus driver. (The bus driver must 195 * not invoke any chipset functions before it is attached.) 196 */ 197 bzero(&saa, sizeof(saa)); 198 saa.saa_busname = "sdmmc"; 199 saa.sct = &rtsx_functions; 200 saa.sch = sc; 201 saa.flags = SMF_STOP_AFTER_MULTIPLE; 202 203 sc->sdmmc = config_found(&sc->sc_dev, &saa, NULL); 204 if (sc->sdmmc == NULL) 205 return 1; 206 207 /* Now handle cards discovered during attachment. */ 208 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 209 rtsx_card_insert(sc); 210 211 return 0; 212 } 213 214 int 215 rtsx_init(struct rtsx_softc *sc, int attaching) 216 { 217 u_int32_t status; 218 u_int8_t version; 219 int error; 220 221 /* Read IC version from dummy register. */ 222 if (sc->flags & RTSX_F_5229) { 223 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 224 switch (version & 0x0F) { 225 case RTSX_IC_VERSION_A: 226 case RTSX_IC_VERSION_B: 227 case RTSX_IC_VERSION_D: 228 break; 229 case RTSX_IC_VERSION_C: 230 sc->flags |= RTSX_F_5229_TYPE_C; 231 break; 232 default: 233 printf("rtsx_init: unknown ic %02x\n", version); 234 return (1); 235 } 236 } 237 238 /* Enable interrupt write-clear (default is read-clear). */ 239 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 240 241 /* Clear any pending interrupts. */ 242 status = READ4(sc, RTSX_BIPR); 243 WRITE4(sc, RTSX_BIPR, status); 244 245 /* Check for cards already inserted at attach time. */ 246 if (attaching && (status & RTSX_SD_EXIST)) 247 sc->flags |= RTSX_F_CARD_PRESENT; 248 249 /* Enable interrupts. */ 250 WRITE4(sc, RTSX_BIER, 251 RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN); 252 253 /* Power on SSC clock. */ 254 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 255 delay(200); 256 257 /* XXX magic numbers from linux driver */ 258 if (sc->flags & RTSX_F_5209) 259 error = rtsx_write_phy(sc, 0x00, 0xB966); 260 else 261 error = rtsx_write_phy(sc, 0x00, 0xBA42); 262 if (error) { 263 printf("%s: cannot write phy register\n", DEVNAME(sc)); 264 return (1); 265 } 266 267 RTSX_SET(sc, RTSX_CLK_DIV, 0x07); 268 269 /* Disable sleep mode. */ 270 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 271 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 272 273 /* Disable card clock. */ 274 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 275 276 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 277 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG | 0x04); 278 RTSX_WRITE(sc, RTSX_SD30_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_3V3); 279 280 /* Enable SSC clock. */ 281 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 282 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 283 284 RTSX_SET(sc, RTSX_CHANGE_LINK_STATE, RTSX_MAC_PHY_RST_N_DBG); 285 RTSX_SET(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT); 286 287 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 288 289 /* Set RC oscillator to 400K. */ 290 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 291 292 /* Request clock by driving CLKREQ pin to zero. */ 293 RTSX_SET(sc, RTSX_PETXCFG, RTSX_PETXCFG_CLKREQ_PIN); 294 295 /* Set up LED GPIO. */ 296 if (sc->flags & RTSX_F_5209) { 297 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 298 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 299 } else { 300 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 301 /* Switch LDO3318 source from DV33 to 3V3. */ 302 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 303 RTSX_SET(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_3V3); 304 /* Set default OLT blink period. */ 305 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_PERIOD); 306 } 307 308 return (0); 309 } 310 311 int 312 rtsx_activate(struct device *self, int act) 313 { 314 struct rtsx_softc *sc = (struct rtsx_softc *)self; 315 int rv = 0; 316 317 switch (act) { 318 case DVACT_QUIESCE: 319 rv = config_activate_children(self, act); 320 break; 321 case DVACT_SUSPEND: 322 rv = config_activate_children(self, act); 323 rtsx_save_regs(sc); 324 break; 325 case DVACT_POWERDOWN: 326 rv = config_activate_children(self, act); 327 break; 328 case DVACT_RESUME: 329 rtsx_restore_regs(sc); 330 331 /* Handle cards ejected/inserted during suspend. */ 332 if (READ4(sc, RTSX_BIPR) & RTSX_SD_EXIST) 333 rtsx_card_insert(sc); 334 else 335 rtsx_card_eject(sc); 336 337 rv = config_activate_children(self, act); 338 break; 339 } 340 return (rv); 341 } 342 343 int 344 rtsx_led_enable(struct rtsx_softc *sc) 345 { 346 if (sc->flags & RTSX_F_5209) { 347 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 348 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 349 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 350 } else { 351 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 352 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 353 } 354 355 return 0; 356 } 357 358 int 359 rtsx_led_disable(struct rtsx_softc *sc) 360 { 361 if (sc->flags & RTSX_F_5209) { 362 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 363 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 364 } else { 365 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 366 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 367 } 368 369 return 0; 370 } 371 372 /* 373 * Reset the host controller. Called during initialization, when 374 * cards are removed, upon resume, and during error recovery. 375 */ 376 int 377 rtsx_host_reset(sdmmc_chipset_handle_t sch) 378 { 379 struct rtsx_softc *sc = sch; 380 int s; 381 382 DPRINTF(1,("%s: host reset\n", DEVNAME(sc))); 383 384 s = splsdmmc(); 385 386 if (ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 387 rtsx_soft_reset(sc); 388 389 if (rtsx_init(sc, 0)) { 390 splx(s); 391 return 1; 392 } 393 394 splx(s); 395 return 0; 396 } 397 398 u_int32_t 399 rtsx_host_ocr(sdmmc_chipset_handle_t sch) 400 { 401 return RTSX_SUPPORT_VOLTAGE; 402 } 403 404 int 405 rtsx_host_maxblklen(sdmmc_chipset_handle_t sch) 406 { 407 return 512; 408 } 409 410 /* 411 * Return non-zero if the card is currently inserted. 412 */ 413 int 414 rtsx_card_detect(sdmmc_chipset_handle_t sch) 415 { 416 struct rtsx_softc *sc = sch; 417 418 return ISSET(sc->flags, RTSX_F_CARD_PRESENT); 419 } 420 421 /* 422 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 423 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 424 * it is a mask of *enabled* gates. 425 */ 426 427 int 428 rtsx_bus_power_off(struct rtsx_softc *sc) 429 { 430 int error; 431 u_int8_t disable3; 432 433 error = rtsx_stop_sd_clock(sc); 434 if (error) 435 return error; 436 437 /* Disable SD output. */ 438 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_CARD_OUTPUT_EN); 439 440 /* Turn off power. */ 441 disable3 = RTSX_PULL_CTL_DISABLE3; 442 if (sc->flags & RTSX_F_5209) 443 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 444 else { 445 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1 | 446 RTSX_LDO3318_VCC2); 447 if (sc->flags & RTSX_F_5229_TYPE_C) 448 disable3 = RTSX_PULL_CTL_DISABLE3_TYPE_C; 449 } 450 451 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 452 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 453 454 /* Disable pull control. */ 455 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 456 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 457 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, disable3); 458 459 return 0; 460 } 461 462 int 463 rtsx_bus_power_on(struct rtsx_softc *sc) 464 { 465 u_int8_t enable3; 466 467 /* Select SD card. */ 468 RTSX_WRITE(sc, RTSX_CARD_SELECT, RTSX_SD_MOD_SEL); 469 RTSX_WRITE(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_48_SD); 470 RTSX_SET(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 471 472 /* Enable pull control. */ 473 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 474 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 475 if (sc->flags & RTSX_F_5229_TYPE_C) 476 enable3 = RTSX_PULL_CTL_ENABLE3_TYPE_C; 477 else 478 enable3 = RTSX_PULL_CTL_ENABLE3; 479 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, enable3); 480 481 /* 482 * To avoid a current peak, enable card power in two phases with a 483 * delay in between. 484 */ 485 486 /* Partial power. */ 487 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PARTIAL_PWR_ON); 488 if (sc->flags & RTSX_F_5229) 489 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC1); 490 else 491 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_SUSPEND); 492 493 delay(200); 494 495 /* Full power. */ 496 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 497 if (sc->flags & RTSX_F_5209) 498 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 499 else 500 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_VCC2); 501 502 /* Enable SD card output. */ 503 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 504 505 return 0; 506 } 507 508 int 509 rtsx_set_bus_width(struct rtsx_softc *sc, int w) 510 { 511 u_int32_t bus_width; 512 513 switch (w) { 514 case 8: 515 bus_width = RTSX_BUS_WIDTH_8; 516 break; 517 case 4: 518 bus_width = RTSX_BUS_WIDTH_4; 519 break; 520 case 1: 521 default: 522 bus_width = RTSX_BUS_WIDTH_1; 523 break; 524 } 525 526 if (bus_width == RTSX_BUS_WIDTH_1) 527 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK); 528 else 529 RTSX_SET(sc, RTSX_SD_CFG1, bus_width); 530 531 return 0; 532 } 533 534 int 535 rtsx_stop_sd_clock(struct rtsx_softc *sc) 536 { 537 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 538 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 539 540 return 0; 541 } 542 543 int 544 rtsx_switch_sd_clock(struct rtsx_softc *sc, u_int8_t n, int div, int mcu) 545 { 546 /* Enable SD 2.0 mode. */ 547 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK); 548 549 RTSX_SET(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 550 551 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 552 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 553 RTSX_CLR(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_SEL_MASK); 554 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 555 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 556 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 557 RTSX_CLR(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK); 558 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 559 RTSX_SET(sc, RTSX_SSC_CTL1, RTSX_RSTB); 560 delay(100); 561 562 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 563 564 return 0; 565 } 566 567 /* 568 * Set or change SD bus voltage and enable or disable SD bus power. 569 * Return zero on success. 570 */ 571 int 572 rtsx_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr) 573 { 574 struct rtsx_softc *sc = sch; 575 int s, error = 0; 576 577 DPRINTF(1,("%s: voltage change ocr=0x%x\n", DEVNAME(sc), ocr)); 578 579 s = splsdmmc(); 580 581 /* 582 * Disable bus power before voltage change. 583 */ 584 error = rtsx_bus_power_off(sc); 585 if (error) 586 goto ret; 587 588 delay(200); 589 590 /* If power is disabled, reset the host and return now. */ 591 if (ocr == 0) { 592 splx(s); 593 (void)rtsx_host_reset(sc); 594 return 0; 595 } 596 597 if (!ISSET(ocr, RTSX_SUPPORT_VOLTAGE)) { 598 /* Unsupported voltage level requested. */ 599 DPRINTF(1,("%s: unsupported voltage ocr=0x%x\n", 600 DEVNAME(sc), ocr)); 601 error = EINVAL; 602 goto ret; 603 } 604 605 error = rtsx_set_bus_width(sc, 1); 606 if (error) 607 goto ret; 608 609 error = rtsx_bus_power_on(sc); 610 ret: 611 splx(s); 612 return error; 613 } 614 615 /* 616 * Set or change SDCLK frequency or disable the SD clock. 617 * Return zero on success. 618 */ 619 int 620 rtsx_bus_clock(sdmmc_chipset_handle_t sch, int freq) 621 { 622 struct rtsx_softc *sc = sch; 623 int s; 624 u_int8_t n; 625 int div; 626 int mcu; 627 int error = 0; 628 629 s = splsdmmc(); 630 631 if (freq == SDMMC_SDCLK_OFF) { 632 error = rtsx_stop_sd_clock(sc); 633 goto ret; 634 } 635 636 /* 637 * Configure the clock frequency. 638 */ 639 switch (freq) { 640 case SDMMC_SDCLK_400KHZ: 641 n = 80; /* minimum */ 642 div = RTSX_CLK_DIV_8; 643 mcu = 7; 644 RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128); 645 break; 646 case SDMMC_SDCLK_25MHZ: 647 n = 100; 648 div = RTSX_CLK_DIV_4; 649 mcu = 7; 650 RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK); 651 break; 652 default: 653 error = EINVAL; 654 goto ret; 655 } 656 657 /* 658 * Enable SD clock. 659 */ 660 error = rtsx_switch_sd_clock(sc, n, div, mcu); 661 ret: 662 splx(s); 663 return error; 664 } 665 666 int 667 rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val) 668 { 669 int tries = 1024; 670 u_int32_t reg; 671 672 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 673 (u_int32_t)((addr & 0x3FFF) << 16)); 674 675 while (tries--) { 676 reg = READ4(sc, RTSX_HAIMR); 677 if (!(reg & RTSX_HAIMR_BUSY)) 678 break; 679 } 680 681 *val = (reg & 0xff); 682 return (tries == 0) ? ETIMEDOUT : 0; 683 } 684 685 int 686 rtsx_write(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t val) 687 { 688 int tries = 1024; 689 u_int32_t reg; 690 691 WRITE4(sc, RTSX_HAIMR, 692 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 693 (u_int32_t)(((addr & 0x3FFF) << 16) | 694 (mask << 8) | val)); 695 696 while (tries--) { 697 reg = READ4(sc, RTSX_HAIMR); 698 if (!(reg & RTSX_HAIMR_BUSY)) { 699 if (val != (reg & 0xff)) 700 return EIO; 701 return 0; 702 } 703 } 704 705 return ETIMEDOUT; 706 } 707 708 #ifdef notyet 709 int 710 rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val) 711 { 712 int timeout = 100000; 713 u_int8_t data0; 714 u_int8_t data1; 715 u_int8_t rwctl; 716 717 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 718 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_READ); 719 720 while (timeout--) { 721 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 722 if (!(rwctl & RTSX_PHY_BUSY)) 723 break; 724 } 725 726 if (timeout == 0) 727 return ETIMEDOUT; 728 729 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 730 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 731 *val = data0 | (data1 << 8); 732 733 return 0; 734 } 735 #endif 736 737 int 738 rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val) 739 { 740 int timeout = 100000; 741 u_int8_t rwctl; 742 743 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 744 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 745 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 746 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY|RTSX_PHY_WRITE); 747 748 while (timeout--) { 749 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 750 if (!(rwctl & RTSX_PHY_BUSY)) 751 break; 752 } 753 754 if (timeout == 0) 755 return ETIMEDOUT; 756 757 return 0; 758 } 759 760 int 761 rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 762 u_int32_t *val) 763 { 764 int tries = 1024; 765 u_int8_t data0, data1, data2, data3, rwctl; 766 767 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 768 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 769 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 770 771 while (tries--) { 772 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 773 if (!(rwctl & RTSX_CFG_BUSY)) 774 break; 775 } 776 777 if (tries == 0) 778 return EIO; 779 780 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 781 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 782 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 783 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 784 785 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 786 787 return 0; 788 } 789 790 #ifdef notyet 791 int 792 rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr, 793 u_int32_t mask, u_int32_t val) 794 { 795 int i, writemask = 0, tries = 1024; 796 u_int8_t rwctl; 797 798 for (i = 0; i < 4; i++) { 799 if (mask & 0xff) { 800 RTSX_WRITE(sc, RTSX_CFGDATA0 + i, val & mask & 0xff); 801 writemask |= (1 << i); 802 } 803 mask >>= 8; 804 val >>= 8; 805 } 806 807 if (writemask) { 808 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 809 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 810 RTSX_WRITE(sc, RTSX_CFGRWCTL, 811 RTSX_CFG_BUSY | writemask | (func & 0x03 << 4)); 812 } 813 814 while (tries--) { 815 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 816 if (!(rwctl & RTSX_CFG_BUSY)) 817 break; 818 } 819 820 if (tries == 0) 821 return EIO; 822 823 return 0; 824 } 825 #endif 826 827 /* Append a properly encoded host command to the host command buffer. */ 828 void 829 rtsx_hostcmd(u_int32_t *cmdbuf, int *n, u_int8_t cmd, u_int16_t reg, 830 u_int8_t mask, u_int8_t data) 831 { 832 KASSERT(*n < RTSX_HOSTCMD_MAX); 833 834 cmdbuf[(*n)++] = htole32((u_int32_t)(cmd & 0x3) << 30) | 835 ((u_int32_t)(reg & 0x3fff) << 16) | 836 ((u_int32_t)(mask) << 8) | 837 ((u_int32_t)data); 838 } 839 840 void 841 rtsx_save_regs(struct rtsx_softc *sc) 842 { 843 int s, i; 844 u_int16_t reg; 845 846 s = splsdmmc(); 847 848 i = 0; 849 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 850 (void)rtsx_read(sc, reg, &sc->regs[i++]); 851 for (reg = 0xFD52; reg < 0xFD69; reg++) 852 (void)rtsx_read(sc, reg, &sc->regs[i++]); 853 for (reg = 0xFE20; reg < 0xFE34; reg++) 854 (void)rtsx_read(sc, reg, &sc->regs[i++]); 855 856 sc->regs4[0] = READ4(sc, RTSX_HCBAR); 857 sc->regs4[1] = READ4(sc, RTSX_HCBCTLR); 858 sc->regs4[2] = READ4(sc, RTSX_HDBAR); 859 sc->regs4[3] = READ4(sc, RTSX_HDBCTLR); 860 sc->regs4[4] = READ4(sc, RTSX_HAIMR); 861 sc->regs4[5] = READ4(sc, RTSX_BIER); 862 /* Not saving RTSX_BIPR. */ 863 864 splx(s); 865 } 866 867 void 868 rtsx_restore_regs(struct rtsx_softc *sc) 869 { 870 int s, i; 871 u_int16_t reg; 872 873 s = splsdmmc(); 874 875 WRITE4(sc, RTSX_HCBAR, sc->regs4[0]); 876 WRITE4(sc, RTSX_HCBCTLR, sc->regs4[1]); 877 WRITE4(sc, RTSX_HDBAR, sc->regs4[2]); 878 WRITE4(sc, RTSX_HDBCTLR, sc->regs4[3]); 879 WRITE4(sc, RTSX_HAIMR, sc->regs4[4]); 880 WRITE4(sc, RTSX_BIER, sc->regs4[5]); 881 /* Not writing RTSX_BIPR since doing so would clear it. */ 882 883 i = 0; 884 for (reg = 0xFDA0; reg < 0xFDAE; reg++) 885 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 886 for (reg = 0xFD52; reg < 0xFD69; reg++) 887 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 888 for (reg = 0xFE20; reg < 0xFE34; reg++) 889 (void)rtsx_write(sc, reg, 0xff, sc->regs[i++]); 890 891 splx(s); 892 } 893 894 u_int8_t 895 rtsx_response_type(u_int16_t sdmmc_rsp) 896 { 897 int i; 898 struct rsp_type { 899 u_int16_t sdmmc_rsp; 900 u_int8_t rtsx_rsp; 901 } rsp_types[] = { 902 { SCF_RSP_R0, RTSX_SD_RSP_TYPE_R0 }, 903 { SCF_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 904 { SCF_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 905 { SCF_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 906 { SCF_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 907 { SCF_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 908 { SCF_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 909 { SCF_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 910 { SCF_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 911 }; 912 913 for (i = 0; i < nitems(rsp_types); i++) { 914 if (sdmmc_rsp == rsp_types[i].sdmmc_rsp) 915 return rsp_types[i].rtsx_rsp; 916 } 917 918 return 0; 919 } 920 921 int 922 rtsx_hostcmd_send(struct rtsx_softc *sc, int ncmd) 923 { 924 int s; 925 926 s = splsdmmc(); 927 928 /* Tell the chip where the command buffer is and run the commands. */ 929 WRITE4(sc, RTSX_HCBAR, sc->dmap_cmd->dm_segs[0].ds_addr); 930 WRITE4(sc, RTSX_HCBCTLR, 931 ((ncmd * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 932 933 splx(s); 934 935 return 0; 936 } 937 938 int 939 rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf) 940 { 941 caddr_t datakvap; 942 bus_dma_segment_t segs; 943 int ncmd, s, dma_dir, error, rsegs, tmode; 944 int read = ISSET(cmd->c_flags, SCF_CMD_READ); 945 u_int8_t cfg2; 946 947 DPRINTF(3,("%s: %s xfer: %d bytes with block size %d\n", DEVNAME(sc), 948 read ? "read" : "write", 949 cmd->c_datalen, cmd->c_blklen)); 950 951 if (cmd->c_datalen > RTSX_DMA_DATA_BUFSIZE) { 952 DPRINTF(3, ("%s: cmd->c_datalen too large: %d > %d\n", 953 DEVNAME(sc), cmd->c_datalen, RTSX_DMA_DATA_BUFSIZE)); 954 return ENOMEM; 955 } 956 957 /* Configure DMA transfer mode parameters. */ 958 cfg2 = RTSX_SD_NO_CHECK_WAIT_CRC_TO | RTSX_SD_CHECK_CRC16 | 959 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 960 if (read) { 961 dma_dir = RTSX_DMA_DIR_FROM_CARD; 962 /* Use transfer mode AUTO_READ3, which assumes we've already 963 * sent the read command and gotten the response, and will 964 * send CMD 12 manually after reading multiple blocks. */ 965 tmode = RTSX_TM_AUTO_READ3; 966 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 967 } else { 968 dma_dir = RTSX_DMA_DIR_TO_CARD; 969 /* Use transfer mode AUTO_WRITE3, which assumes we've already 970 * sent the write command and gotten the response, and will 971 * send CMD 12 manually after writing multiple blocks. */ 972 tmode = RTSX_TM_AUTO_WRITE3; 973 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 974 } 975 976 ncmd = 0; 977 978 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 979 0xff, cfg2); 980 981 /* Queue commands to configure data transfer size. */ 982 rtsx_hostcmd(cmdbuf, &ncmd, 983 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xff, 0); 984 rtsx_hostcmd(cmdbuf, &ncmd, 985 RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xff, 0x02); 986 rtsx_hostcmd(cmdbuf, &ncmd, 987 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xff, 988 ((cmd->c_datalen / cmd->c_blklen) & 0xff)); 989 rtsx_hostcmd(cmdbuf, &ncmd, 990 RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xff, 991 ((cmd->c_datalen / cmd->c_blklen) >> 8)); 992 993 /* Use the DMA ring buffer for commands which transfer data. */ 994 rtsx_hostcmd(cmdbuf, &ncmd, 995 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 0x01, RTSX_RING_BUFFER); 996 997 /* Configure DMA controller. */ 998 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 999 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 1000 rtsx_hostcmd(cmdbuf, &ncmd, 1001 RTSX_WRITE_REG_CMD, RTSX_DMATC3, 0xff, cmd->c_datalen >> 24); 1002 rtsx_hostcmd(cmdbuf, &ncmd, 1003 RTSX_WRITE_REG_CMD, RTSX_DMATC2, 0xff, cmd->c_datalen >> 16); 1004 rtsx_hostcmd(cmdbuf, &ncmd, 1005 RTSX_WRITE_REG_CMD, RTSX_DMATC1, 0xff, cmd->c_datalen >> 8); 1006 rtsx_hostcmd(cmdbuf, &ncmd, 1007 RTSX_WRITE_REG_CMD, RTSX_DMATC0, 0xff, cmd->c_datalen); 1008 rtsx_hostcmd(cmdbuf, &ncmd, 1009 RTSX_WRITE_REG_CMD, RTSX_DMACTL, 1010 0x03 | RTSX_DMA_PACK_SIZE_MASK, 1011 dma_dir | RTSX_DMA_EN | RTSX_DMA_512); 1012 1013 /* Queue commands to perform SD transfer. */ 1014 rtsx_hostcmd(cmdbuf, &ncmd, 1015 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1016 0xff, tmode | RTSX_SD_TRANSFER_START); 1017 rtsx_hostcmd(cmdbuf, &ncmd, 1018 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1019 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1020 1021 error = rtsx_hostcmd_send(sc, ncmd); 1022 if (error) 1023 goto ret; 1024 1025 /* Allocate and map DMA memory for data transfer. */ 1026 error = bus_dmamem_alloc(sc->dmat, cmd->c_datalen, 0, 0, &segs, 1, 1027 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1028 if (error) { 1029 DPRINTF(3, ("%s: could not allocate %d bytes\n", 1030 DEVNAME(sc), cmd->c_datalen)); 1031 goto ret; 1032 } 1033 error = bus_dmamem_map(sc->dmat, &segs, rsegs, cmd->c_datalen, 1034 &datakvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1035 if (error) { 1036 DPRINTF(3, ("%s: could not map data buffer\n", DEVNAME(sc))); 1037 goto free_databuf; 1038 } 1039 1040 /* If this is a write, copy data from sdmmc-provided buffer. */ 1041 if (!read) 1042 memcpy(datakvap, cmd->c_data, cmd->c_datalen); 1043 1044 /* Load the data buffer and sync it. */ 1045 error = bus_dmamap_load(sc->dmat, sc->dmap_data, datakvap, 1046 cmd->c_datalen, NULL, BUS_DMA_WAITOK); 1047 if (error) { 1048 DPRINTF(3, ("%s: could not load DMA map\n", DEVNAME(sc))); 1049 goto unmap_databuf; 1050 } 1051 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1052 BUS_DMASYNC_PREREAD); 1053 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1054 BUS_DMASYNC_PREWRITE); 1055 1056 s = splsdmmc(); 1057 1058 /* Tell the chip where the data buffer is and run the transfer. */ 1059 WRITE4(sc, RTSX_HDBAR, sc->dmap_data->dm_segs[0].ds_addr); 1060 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 1061 (sc->dmap_data->dm_segs[0].ds_len & 0x00ffffff)); 1062 1063 splx(s); 1064 1065 /* Wait for completion. */ 1066 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, 10*hz); 1067 if (error) 1068 goto unload_databuf; 1069 1070 /* Sync and unload data DMA buffer. */ 1071 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1072 BUS_DMASYNC_POSTREAD); 1073 bus_dmamap_sync(sc->dmat, sc->dmap_data, 0, cmd->c_datalen, 1074 BUS_DMASYNC_POSTWRITE); 1075 1076 unload_databuf: 1077 bus_dmamap_unload(sc->dmat, sc->dmap_data); 1078 1079 /* If this is a read, copy data into sdmmc-provided buffer. */ 1080 if (error == 0 && read) 1081 memcpy(cmd->c_data, datakvap, cmd->c_datalen); 1082 1083 /* Free DMA data buffer. */ 1084 unmap_databuf: 1085 bus_dmamem_unmap(sc->dmat, datakvap, cmd->c_datalen); 1086 free_databuf: 1087 bus_dmamem_free(sc->dmat, &segs, rsegs); 1088 ret: 1089 DPRINTF(3,("%s: xfer done, error=%d\n", DEVNAME(sc), error)); 1090 return error; 1091 } 1092 1093 void 1094 rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 1095 { 1096 struct rtsx_softc *sc = sch; 1097 bus_dma_segment_t segs; 1098 int rsegs; 1099 caddr_t cmdkvap; 1100 u_int32_t *cmdbuf; 1101 u_int8_t rsp_type; 1102 u_int16_t r; 1103 int ncmd; 1104 int error = 0; 1105 1106 DPRINTF(3,("%s: executing cmd %hu\n", DEVNAME(sc), cmd->c_opcode)); 1107 1108 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 1109 if (cmd->c_opcode == SD_IO_SEND_OP_COND && 1110 !ISSET(sc->flags, RTSX_F_SDIO_SUPPORT)) { 1111 error = ENOTSUP; 1112 goto ret; 1113 } 1114 1115 rsp_type = rtsx_response_type(cmd->c_flags & 0xff00); 1116 if (rsp_type == 0) { 1117 printf("%s: unknown response type 0x%x\n", DEVNAME(sc), 1118 (cmd->c_flags & 0xff00)); 1119 error = EINVAL; 1120 goto ret; 1121 } 1122 1123 /* Allocate and map the host command buffer. */ 1124 error = bus_dmamem_alloc(sc->dmat, RTSX_HOSTCMD_BUFSIZE, 0, 0, &segs, 1, 1125 &rsegs, BUS_DMA_WAITOK|BUS_DMA_ZERO); 1126 if (error) 1127 goto ret; 1128 error = bus_dmamem_map(sc->dmat, &segs, rsegs, RTSX_HOSTCMD_BUFSIZE, 1129 &cmdkvap, BUS_DMA_WAITOK|BUS_DMA_COHERENT); 1130 if (error) 1131 goto free_cmdbuf; 1132 1133 /* The command buffer queues commands the host controller will 1134 * run asynchronously. */ 1135 cmdbuf = (u_int32_t *)cmdkvap; 1136 ncmd = 0; 1137 1138 /* Queue commands to set SD command index and argument. */ 1139 rtsx_hostcmd(cmdbuf, &ncmd, 1140 RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode); 1141 rtsx_hostcmd(cmdbuf, &ncmd, 1142 RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24); 1143 rtsx_hostcmd(cmdbuf, &ncmd, 1144 RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xff, cmd->c_arg >> 16); 1145 rtsx_hostcmd(cmdbuf, &ncmd, 1146 RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 0xff, cmd->c_arg >> 8); 1147 rtsx_hostcmd(cmdbuf, &ncmd, 1148 RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 0xff, cmd->c_arg); 1149 1150 /* Queue command to set response type. */ 1151 rtsx_hostcmd(cmdbuf, &ncmd, 1152 RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 1153 1154 /* Use the ping-pong buffer for commands which do not transfer data. */ 1155 rtsx_hostcmd(cmdbuf, &ncmd, 1156 RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 1157 0x01, RTSX_PINGPONG_BUFFER); 1158 1159 /* Queue commands to perform SD transfer. */ 1160 rtsx_hostcmd(cmdbuf, &ncmd, 1161 RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1162 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 1163 rtsx_hostcmd(cmdbuf, &ncmd, 1164 RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1165 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 1166 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 1167 1168 /* Queue commands to read back card status response.*/ 1169 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 1170 for (r = RTSX_PPBUF_BASE2 + 15; r > RTSX_PPBUF_BASE2; r--) 1171 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1172 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, RTSX_SD_CMD5, 1173 0, 0); 1174 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 1175 for (r = RTSX_SD_CMD0; r <= RTSX_SD_CMD4; r++) 1176 rtsx_hostcmd(cmdbuf, &ncmd, RTSX_READ_REG_CMD, r, 0, 0); 1177 } 1178 1179 /* Load and sync command DMA buffer. */ 1180 error = bus_dmamap_load(sc->dmat, sc->dmap_cmd, cmdkvap, 1181 RTSX_HOSTCMD_BUFSIZE, NULL, BUS_DMA_WAITOK); 1182 if (error) 1183 goto unmap_cmdbuf; 1184 1185 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1186 BUS_DMASYNC_PREREAD); 1187 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1188 BUS_DMASYNC_PREWRITE); 1189 1190 /* Run the command queue and wait for completion. */ 1191 error = rtsx_hostcmd_send(sc, ncmd); 1192 if (error == 0) 1193 error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz); 1194 if (error) 1195 goto unload_cmdbuf; 1196 1197 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1198 BUS_DMASYNC_POSTREAD); 1199 bus_dmamap_sync(sc->dmat, sc->dmap_cmd, 0, RTSX_HOSTCMD_BUFSIZE, 1200 BUS_DMASYNC_POSTWRITE); 1201 1202 /* Copy card response into sdmmc response buffer. */ 1203 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 1204 /* Copy bytes like sdhc(4), which on little-endian uses 1205 * different byte order for short and long responses... */ 1206 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 1207 memcpy(cmd->c_resp, cmdkvap + 1, sizeof(cmd->c_resp)); 1208 } else { 1209 /* First byte is CHECK_REG_CMD return value, second 1210 * one is the command op code -- we skip those. */ 1211 cmd->c_resp[0] = 1212 ((betoh32(cmdbuf[0]) & 0x0000ffff) << 16) | 1213 ((betoh32(cmdbuf[1]) & 0xffff0000) >> 16); 1214 } 1215 } 1216 1217 if (cmd->c_data) { 1218 error = rtsx_xfer(sc, cmd, cmdbuf); 1219 if (error) { 1220 u_int8_t stat1; 1221 1222 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 1223 (stat1 & RTSX_SD_CRC_ERR)) 1224 printf("%s: CRC error\n", DEVNAME(sc)); 1225 } 1226 } 1227 1228 unload_cmdbuf: 1229 bus_dmamap_unload(sc->dmat, sc->dmap_cmd); 1230 unmap_cmdbuf: 1231 bus_dmamem_unmap(sc->dmat, cmdkvap, RTSX_HOSTCMD_BUFSIZE); 1232 free_cmdbuf: 1233 bus_dmamem_free(sc->dmat, &segs, rsegs); 1234 ret: 1235 SET(cmd->c_flags, SCF_ITSDONE); 1236 cmd->c_error = error; 1237 } 1238 1239 /* Prepare for another command. */ 1240 void 1241 rtsx_soft_reset(struct rtsx_softc *sc) 1242 { 1243 DPRINTF(1,("%s: soft reset\n", DEVNAME(sc))); 1244 1245 /* Stop command transfer. */ 1246 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 1247 1248 (void)rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP|RTSX_SD_CLR_ERR, 1249 RTSX_SD_STOP|RTSX_SD_CLR_ERR); 1250 1251 /* Stop DMA transfer. */ 1252 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 1253 (void)rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 1254 1255 (void)rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 1256 } 1257 1258 int 1259 rtsx_wait_intr(struct rtsx_softc *sc, int mask, int timo) 1260 { 1261 int status; 1262 int error = 0; 1263 int s; 1264 1265 mask |= RTSX_TRANS_FAIL_INT; 1266 1267 s = splsdmmc(); 1268 status = sc->intr_status & mask; 1269 while (status == 0) { 1270 if (tsleep(&sc->intr_status, PRIBIO, "rtsxintr", timo) 1271 == EWOULDBLOCK) { 1272 rtsx_soft_reset(sc); 1273 error = ETIMEDOUT; 1274 break; 1275 } 1276 status = sc->intr_status & mask; 1277 } 1278 sc->intr_status &= ~status; 1279 1280 /* Has the card disappeared? */ 1281 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1282 error = ENODEV; 1283 1284 splx(s); 1285 1286 if (error == 0 && (status & RTSX_TRANS_FAIL_INT)) 1287 error = EIO; 1288 1289 return error; 1290 } 1291 1292 void 1293 rtsx_card_insert(struct rtsx_softc *sc) 1294 { 1295 DPRINTF(1, ("%s: card inserted\n", DEVNAME(sc))); 1296 1297 sc->flags |= RTSX_F_CARD_PRESENT; 1298 (void)rtsx_led_enable(sc); 1299 1300 /* Schedule card discovery task. */ 1301 sdmmc_needs_discover(sc->sdmmc); 1302 } 1303 1304 void 1305 rtsx_card_eject(struct rtsx_softc *sc) 1306 { 1307 DPRINTF(1, ("%s: card ejected\n", DEVNAME(sc))); 1308 1309 sc->flags &= ~RTSX_F_CARD_PRESENT; 1310 (void)rtsx_led_disable(sc); 1311 1312 /* Schedule card discovery task. */ 1313 sdmmc_needs_discover(sc->sdmmc); 1314 } 1315 1316 /* 1317 * Established by attachment driver at interrupt priority IPL_SDMMC. 1318 */ 1319 int 1320 rtsx_intr(void *arg) 1321 { 1322 struct rtsx_softc *sc = arg; 1323 u_int32_t enabled, status; 1324 1325 enabled = READ4(sc, RTSX_BIER); 1326 status = READ4(sc, RTSX_BIPR); 1327 1328 /* Ack interrupts. */ 1329 WRITE4(sc, RTSX_BIPR, status); 1330 1331 if (((enabled & status) == 0) || status == 0xffffffff) 1332 return 0; 1333 1334 if (status & RTSX_SD_INT) { 1335 if (status & RTSX_SD_EXIST) { 1336 if (!ISSET(sc->flags, RTSX_F_CARD_PRESENT)) 1337 rtsx_card_insert(sc); 1338 } else { 1339 rtsx_card_eject(sc); 1340 } 1341 } 1342 1343 if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) { 1344 sc->intr_status |= status; 1345 wakeup(&sc->intr_status); 1346 } 1347 1348 return 1; 1349 } 1350