1*6b81be85Sjsg /* $OpenBSD: max2820reg.h,v 1.2 2009/08/16 18:21:57 jsg Exp $ */ 2e7dadcc5Sjsg /* $NetBSD: max2820reg.h,v 1.1 2004/09/26 02:29:15 dyoung Exp $ */ 3e7dadcc5Sjsg 4e7dadcc5Sjsg /* 5e7dadcc5Sjsg * Copyright (c) 2004 David Young. All rights reserved. 6e7dadcc5Sjsg * 7e7dadcc5Sjsg * This code was written by David Young. 8e7dadcc5Sjsg * 9e7dadcc5Sjsg * Redistribution and use in source and binary forms, with or without 10e7dadcc5Sjsg * modification, are permitted provided that the following conditions 11e7dadcc5Sjsg * are met: 12e7dadcc5Sjsg * 1. Redistributions of source code must retain the above copyright 13e7dadcc5Sjsg * notice, this list of conditions and the following disclaimer. 14e7dadcc5Sjsg * 2. Redistributions in binary form must reproduce the above copyright 15e7dadcc5Sjsg * notice, this list of conditions and the following disclaimer in the 16e7dadcc5Sjsg * documentation and/or other materials provided with the distribution. 17e7dadcc5Sjsg * 3. Neither the name of the author nor the names of any co-contributors 18e7dadcc5Sjsg * may be used to endorse or promote products derived from this software 19e7dadcc5Sjsg * without specific prior written permission. 20e7dadcc5Sjsg * 21e7dadcc5Sjsg * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 22e7dadcc5Sjsg * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 23e7dadcc5Sjsg * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 24e7dadcc5Sjsg * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 25e7dadcc5Sjsg * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 26e7dadcc5Sjsg * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 27e7dadcc5Sjsg * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28e7dadcc5Sjsg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29e7dadcc5Sjsg * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30e7dadcc5Sjsg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31e7dadcc5Sjsg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32e7dadcc5Sjsg * OF SUCH DAMAGE. 33e7dadcc5Sjsg */ 34e7dadcc5Sjsg 35e7dadcc5Sjsg #ifndef _DEV_IC_MAX2820REG_H_ 36e7dadcc5Sjsg #define _DEV_IC_MAX2820REG_H_ 37e7dadcc5Sjsg 38e7dadcc5Sjsg /* 39e7dadcc5Sjsg * Serial bus format for Maxim MAX2820/MAX2820A/MAX2821/MAX2821A 40e7dadcc5Sjsg * 2.4GHz 802.11b Zero-IF Transceivers 41e7dadcc5Sjsg */ 42*6b81be85Sjsg #define MAX2820_TWI_ADDR_MASK 0xf000 43*6b81be85Sjsg #define MAX2820_TWI_DATA_MASK 0xfff 44e7dadcc5Sjsg 45e7dadcc5Sjsg /* 46e7dadcc5Sjsg * Registers for Maxim MAX2820/MAX2820A/MAX2821/MAX2821A 2.4GHz 47e7dadcc5Sjsg * 802.11b Zero-IF Transceivers 48e7dadcc5Sjsg */ 49e7dadcc5Sjsg #define MAX2820_TEST 0 /* Test Register */ 50*6b81be85Sjsg #define MAX2820_TEST_DEFAULT 0x7 /* Always set to this value. */ 51e7dadcc5Sjsg 52e7dadcc5Sjsg #define MAX2820_ENABLE 1 /* Block-Enable Register */ 53*6b81be85Sjsg #define MAX2820_ENABLE_RSVD1 (1<<11) /* reserved */ 54*6b81be85Sjsg #define MAX2820_ENABLE_PAB (1<<10) /* Transmit Baseband Filters 55e7dadcc5Sjsg * Enable 56e7dadcc5Sjsg * PAB_EN = SHDNB && 57e7dadcc5Sjsg * (MAX2820_ENABLE_PAB || 58e7dadcc5Sjsg * TX_ON) 59e7dadcc5Sjsg */ 60*6b81be85Sjsg #define MAX2820_ENABLE_TXFLT (1<<9) /* Transmit Baseband Filters 61e7dadcc5Sjsg * Enable 62e7dadcc5Sjsg * TXFLT_EN = SHDNB && 63e7dadcc5Sjsg * (MAX2820_ENABLE_TXFLT || 64e7dadcc5Sjsg * TX_ON) 65e7dadcc5Sjsg */ 66*6b81be85Sjsg #define MAX2820_ENABLE_TXUVD (1<<8) /* Tx Upconverter, VGA, and 67e7dadcc5Sjsg * Driver Amp Enable 68e7dadcc5Sjsg * TXUVD_EN = SHDNB && 69e7dadcc5Sjsg * (MAX2820_ENABLE_TXUVD || 70e7dadcc5Sjsg * TX_ON) 71e7dadcc5Sjsg */ 72*6b81be85Sjsg #define MAX2820_ENABLE_DET (1<<7) /* Receive Detector Enable 73e7dadcc5Sjsg * DET_EN = SHDNB && 74e7dadcc5Sjsg * (MAX2820_ENABLE_DET || 75e7dadcc5Sjsg * RX_ON) 76e7dadcc5Sjsg */ 77*6b81be85Sjsg #define MAX2820_ENABLE_RXDFA (1<<6) /* Rx Downconverter, Filters, 78e7dadcc5Sjsg * and AGC Amps Enable 79e7dadcc5Sjsg * RXDFA_EN = SHDNB && 80e7dadcc5Sjsg * (MAX2820_ENABLE_RXDFA || 81e7dadcc5Sjsg * RX_ON) 82e7dadcc5Sjsg */ 83*6b81be85Sjsg #define MAX2820_ENABLE_RXLNA (1<<5) /* Receive LNA Enable 84e7dadcc5Sjsg * AT_EN = SHDNB && 85e7dadcc5Sjsg * (MAX2820_ENABLE_RXLNA || 86e7dadcc5Sjsg * RX_ON) 87e7dadcc5Sjsg */ 88*6b81be85Sjsg #define MAX2820_ENABLE_AT (1<<4) /* Auto-tuner Enable 89e7dadcc5Sjsg * AT_EN = SHDNB && 90e7dadcc5Sjsg * (MAX2820_ENABLE_AT || 91e7dadcc5Sjsg * RX_ON || TX_ON) 92e7dadcc5Sjsg */ 93*6b81be85Sjsg #define MAX2820_ENABLE_CP (1<<3) /* PLL Charge-Pump Enable 94e7dadcc5Sjsg * CP_EN = SHDNB 95e7dadcc5Sjsg * && MAX2820_ENABLE_CP 96e7dadcc5Sjsg */ 97*6b81be85Sjsg #define MAX2820_ENABLE_PLL (1<<2) /* PLL Enable 98e7dadcc5Sjsg * PLL_EN = SHDNB 99e7dadcc5Sjsg * && MAX2820_ENABLE_PLL 100e7dadcc5Sjsg */ 101*6b81be85Sjsg #define MAX2820_ENABLE_VCO (1<<1) /* VCO Enable 102e7dadcc5Sjsg * VCO_EN = SHDNB 103e7dadcc5Sjsg * && MAX2820_ENABLE_VCO 104e7dadcc5Sjsg */ 105*6b81be85Sjsg #define MAX2820_ENABLE_RSVD0 (1<<0) /* reserved */ 106e7dadcc5Sjsg #define MAX2820_ENABLE_DEFAULT (MAX2820_ENABLE_AT|MAX2820_ENABLE_CP|\ 107e7dadcc5Sjsg MAX2820_ENABLE_PLL|MAX2820_ENABLE_VCO) 108e7dadcc5Sjsg 109e7dadcc5Sjsg #define MAX2820_SYNTH 2 /* Synthesizer Register */ 110*6b81be85Sjsg #define MAX2820_SYNTH_RSVD0 0xf80 /* reserved */ 111*6b81be85Sjsg #define MAX2820_SYNTH_ICP (1<<6) /* Charge-Pump Current Select 112e7dadcc5Sjsg * 0 = +/-1mA 113e7dadcc5Sjsg * 1 = +/-2mA 114e7dadcc5Sjsg */ 115*6b81be85Sjsg #define MAX2820_SYNTH_R_MASK 0x3f /* Reference Frequency Divider 116e7dadcc5Sjsg * 0 = 22MHz 117e7dadcc5Sjsg * 1 = 44MHz 118e7dadcc5Sjsg */ 119e7dadcc5Sjsg #define MAX2820_SYNTH_R_22MHZ LSHIFT(0, MAX2820_SYNTH_R_MASK) 120e7dadcc5Sjsg #define MAX2820_SYNTH_R_44MHZ LSHIFT(1, MAX2820_SYNTH_R_MASK) 121e7dadcc5Sjsg #define MAX2820_SYNTH_ICP_DEFAULT MAX2820_SYNTH_ICP 122e7dadcc5Sjsg #define MAX2820_SYNTH_R_DEFAULT LSHIFT(0, MAX2820_SYNTH_R_MASK) 123e7dadcc5Sjsg 124e7dadcc5Sjsg #define MAX2820_CHANNEL 3 /* Channel Frequency Register */ 125*6b81be85Sjsg #define MAX2820_CHANNEL_RSVD 0xf80 /* reserved */ 126*6b81be85Sjsg #define MAX2820_CHANNEL_CF_MASK 0x7f /* Channel Frequency Select 127e7dadcc5Sjsg * fLO = 2400MHz + CF * 1MHz 128e7dadcc5Sjsg */ 129e7dadcc5Sjsg #define MAX2820_CHANNEL_RSVD_DEFAULT LSHIFT(0, MAX2820_CHANNEL_RSVD) 130e7dadcc5Sjsg #define MAX2820_CHANNEL_CF_DEFAULT LSHIFT(37, MAX2820_CHANNEL_CF_MASK) 131e7dadcc5Sjsg 132e7dadcc5Sjsg #define MAX2820_RECEIVE 4 /* Receiver Settings Register 133e7dadcc5Sjsg * MAX2820/MAX2821 134e7dadcc5Sjsg */ 135*6b81be85Sjsg #define MAX2820_RECEIVE_2C_MASK 0xe00 /* VGA DC Offset Nulling 136e7dadcc5Sjsg * Parameter 2 137e7dadcc5Sjsg */ 138*6b81be85Sjsg #define MAX2820_RECEIVE_1C_MASK 0x1c0 /* VGA DC Offset Nulling 139e7dadcc5Sjsg * Parameter 1 140e7dadcc5Sjsg */ 141*6b81be85Sjsg #define MAX2820_RECEIVE_DL_MASK 0x30 /* Rx Level Detector Midpoint 142e7dadcc5Sjsg * Select 143e7dadcc5Sjsg * 11, 01 = 50.2mVp 144e7dadcc5Sjsg * 10 = 70.9mVp 145e7dadcc5Sjsg * 00 = 35.5mVp 146e7dadcc5Sjsg */ 147*6b81be85Sjsg #define MAX2820_RECEIVE_SF (1<<3) /* Special Function Select 148e7dadcc5Sjsg * 0 = OFF 149e7dadcc5Sjsg * 1 = ON 150e7dadcc5Sjsg */ 151*6b81be85Sjsg #define MAX2820_RECEIVE_BW_MASK 0x7 /* Receive Filter -3dB Frequency 152e7dadcc5Sjsg * Select (all frequencies are 153e7dadcc5Sjsg * approximate) 154e7dadcc5Sjsg */ 155e7dadcc5Sjsg /* 8.5MHz */ 156e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_8_5MHZ LSHIFT(0, MAX2820_RECEIVE_BW_MASK) 157e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_8MHZ LSHIFT(1, MAX2820_RECEIVE_BW_MASK) 158e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_7_5MHZ LSHIFT(2, MAX2820_RECEIVE_BW_MASK) 159e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_7MHZ LSHIFT(3, MAX2820_RECEIVE_BW_MASK) 160e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_6_5MHZ LSHIFT(4, MAX2820_RECEIVE_BW_MASK) 161e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_6MHZ LSHIFT(5, MAX2820_RECEIVE_BW_MASK) 162e7dadcc5Sjsg #define MAX2820_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_2C_MASK) 163e7dadcc5Sjsg #define MAX2820_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_1C_MASK) 164e7dadcc5Sjsg #define MAX2820_RECEIVE_DL_DEFAULT LSHIFT(1, MAX2820_RECEIVE_DL_MASK) 165e7dadcc5Sjsg #define MAX2820_RECEIVE_SF_DEFAULT LSHIFT(0, MAX2820_RECEIVE_SF) 166e7dadcc5Sjsg #define MAX2820_RECEIVE_BW_DEFAULT MAX2820_RECEIVE_BW_7_5MHZ 167e7dadcc5Sjsg 168e7dadcc5Sjsg #define MAX2820A_RECEIVE 4 /* Receiver Settings Register, 169e7dadcc5Sjsg * MAX2820A/MAX2821A 170e7dadcc5Sjsg */ 171e7dadcc5Sjsg /* VGA DC Offset Nulling Parameter 2 */ 172*6b81be85Sjsg #define MAX2820A_RECEIVE_2C_MASK 0xe00 173e7dadcc5Sjsg #define MAX2820A_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_2C_MASK) 174e7dadcc5Sjsg /* VGA DC Offset Nulling Parameter 1 */ 175*6b81be85Sjsg #define MAX2820A_RECEIVE_1C_MASK 0x1c0 176e7dadcc5Sjsg #define MAX2820A_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_1C_MASK) 177*6b81be85Sjsg #define MAX2820A_RECEIVE_RSVD0_MASK 0x38 178e7dadcc5Sjsg #define MAX2820A_RECEIVE_RSVD0_DEFAULT LSHIFT(2, MAX2820A_RECEIVE_RSVD0_MASK) 179*6b81be85Sjsg #define MAX2820A_RECEIVE_RSVD1_MASK 0x7 180e7dadcc5Sjsg #define MAX2820A_RECEIVE_RSVD1_DEFAULT LSHIFT(2,MAX2820_RECEIVE_RSVD1_MASK) 181e7dadcc5Sjsg 182e7dadcc5Sjsg #define MAX2820_TRANSMIT 5 /* Transmitter Settings Reg. */ 183*6b81be85Sjsg #define MAX2820_TRANSMIT_RSVD_MASK 0xff0 /* reserved */ 184*6b81be85Sjsg #define MAX2820_TRANSMIT_PA_MASK 0xf /* PA Bias Select 185e7dadcc5Sjsg * 15 = Highest 186e7dadcc5Sjsg * 0 = Lowest 187e7dadcc5Sjsg */ 188e7dadcc5Sjsg #define MAX2820_TRANSMIT_PA_DEFAULT LSHIFT(0, MAX2820_TRANSMIT_PA_MASK) 189e7dadcc5Sjsg 190e7dadcc5Sjsg #endif /* _DEV_IC_MAX2820REG_H_ */ 191