1*d874cce4Sray /* $OpenBSD: lsi64854reg.h,v 1.4 2008/06/26 05:42:15 ray Exp $ */ 28f375c82Sjason /* $NetBSD: lsi64854reg.h,v 1.5 2001/03/29 02:58:39 petrov Exp $ */ 38f375c82Sjason 48f375c82Sjason /*- 58f375c82Sjason * Copyright (c) 1998 The NetBSD Foundation, Inc. 68f375c82Sjason * All rights reserved. 78f375c82Sjason * 88f375c82Sjason * This code is derived from software contributed to The NetBSD Foundation 98f375c82Sjason * by Paul Kranenburg. 108f375c82Sjason * 118f375c82Sjason * Redistribution and use in source and binary forms, with or without 128f375c82Sjason * modification, are permitted provided that the following conditions 138f375c82Sjason * are met: 148f375c82Sjason * 1. Redistributions of source code must retain the above copyright 158f375c82Sjason * notice, this list of conditions and the following disclaimer. 168f375c82Sjason * 2. Redistributions in binary form must reproduce the above copyright 178f375c82Sjason * notice, this list of conditions and the following disclaimer in the 188f375c82Sjason * documentation and/or other materials provided with the distribution. 198f375c82Sjason * 208f375c82Sjason * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 218f375c82Sjason * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 228f375c82Sjason * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 238f375c82Sjason * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 248f375c82Sjason * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 258f375c82Sjason * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 268f375c82Sjason * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 278f375c82Sjason * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 288f375c82Sjason * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 298f375c82Sjason * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 308f375c82Sjason * POSSIBILITY OF SUCH DAMAGE. 318f375c82Sjason */ 328f375c82Sjason 338f375c82Sjason /* 348f375c82Sjason * LSI 64854 DMA engine. Contains three independent channels 358f375c82Sjason * designed to interface with (a) a NCR539X SCSI controller, 368f375c82Sjason * (b) a AM7990 Ethernet controller, (c) Parallel port hardware.. 378f375c82Sjason */ 388f375c82Sjason 398f375c82Sjason /* 408f375c82Sjason * Register offsets to bus handle. 418f375c82Sjason */ 428f375c82Sjason #define L64854_REG_CSR 0 /* Control bits */ 438f375c82Sjason #define L64854_REG_ADDR 4 /* DMA Address */ 448f375c82Sjason #define L64854_REG_CNT 8 /* DMA count */ 458f375c82Sjason #define L64854_REG_CNT_MASK 0x00ffffff /* only 24 bits */ 468f375c82Sjason #define L64854_REG_ENBAR 12 /* ENET Base register */ 478f375c82Sjason #define L64854_REG_TEST 12 /* SCSI Test register */ 488f375c82Sjason #define L64854_REG_HCR 16 /* PP Hardware Configuration */ 498f375c82Sjason #define L64854_REG_OCR 18 /* PP Operation Configuration */ 508f375c82Sjason #define L64854_REG_DR 20 /* PP Data register */ 518f375c82Sjason #define L64854_REG_TCR 21 /* PP Transfer Control */ 528f375c82Sjason #define L64854_REG_OR 22 /* PP Output register */ 538f375c82Sjason #define L64854_REG_IR 23 /* PP Input register */ 548f375c82Sjason #define L64854_REG_ICR 24 /* PP Interrupt Control */ 558f375c82Sjason 568f375c82Sjason 578f375c82Sjason /* 588f375c82Sjason * Control bits common to all three channels. 598f375c82Sjason */ 608f375c82Sjason #define L64854_INT_PEND 0x00000001 /* Interrupt pending */ 618f375c82Sjason #define L64854_ERR_PEND 0x00000002 /* Error pending */ 628f375c82Sjason #define L64854_DRAINING 0x0000000c /* FIFO draining */ 638f375c82Sjason #define L64854_INT_EN 0x00000010 /* Interrupt enable */ 648f375c82Sjason #define L64854_INVALIDATE 0x00000020 /* Invalidate FIFO */ 658f375c82Sjason #define L64854_SLAVE_ERR 0x00000040 /* Slave access size error */ 668f375c82Sjason #define L64854_RESET 0x00000080 /* Reset device */ 678f375c82Sjason #define L64854_WRITE 0x00000100 /* 1: xfer to memory */ 688f375c82Sjason #define L64854_EN_DMA 0x00000200 /* enable DMA transfers */ 698f375c82Sjason 708f375c82Sjason #define L64854_BURST_SIZE 0x000c0000 /* Read/write burst size */ 718f375c82Sjason #define L64854_BURST_0 0x00080000 /* no bursts (SCSI-only) */ 728f375c82Sjason #define L64854_BURST_16 0x00000000 /* 16-byte bursts */ 738f375c82Sjason #define L64854_BURST_32 0x00040000 /* 32-byte bursts */ 748f375c82Sjason #define L64854_BURST_64 0x000c0000 /* 64-byte bursts (fas) */ 758f375c82Sjason 768f375c82Sjason #define L64854_RST_FAS366 0x08000000 /* FAS366 hardware reset */ 778f375c82Sjason 788f375c82Sjason #define L64854_DEVID 0xf0000000 /* device ID bits */ 798f375c82Sjason 808f375c82Sjason /* 818f375c82Sjason * SCSI DMA control bits. 828f375c82Sjason */ 838f375c82Sjason #define D_INT_PEND L64854_INT_PEND /* interrupt pending */ 848f375c82Sjason #define D_ERR_PEND L64854_ERR_PEND /* error pending */ 858f375c82Sjason #define D_DRAINING L64854_DRAINING /* fifo draining */ 868f375c82Sjason #define D_INT_EN L64854_INT_EN /* interrupt enable */ 878f375c82Sjason #define D_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 888f375c82Sjason #define D_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 898f375c82Sjason #define D_RESET L64854_RESET /* reset scsi */ 908f375c82Sjason #define D_WRITE L64854_WRITE /* 1 = dev -> mem */ 918f375c82Sjason #define D_EN_DMA L64854_EN_DMA /* enable DMA requests */ 928f375c82Sjason #define D_EN_CNT 0x00002000 /* enable byte counter */ 938f375c82Sjason #define D_TC 0x00004000 /* terminal count */ 948f375c82Sjason #define D_WIDE_EN 0x00008000 /* enable wide mode SBUS DMA (fas) */ 958f375c82Sjason #define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */ 968f375c82Sjason #define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */ 978f375c82Sjason 988f375c82Sjason #define D_DIAG 0x00100000 /* disable fifo drain on addr */ 998f375c82Sjason #define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */ 1008f375c82Sjason #define D_FASTER 0x00400000 /* 3 clocks per transfer */ 1018f375c82Sjason #define D_TCI_DIS 0x00800000 /* disable intr on D_TC */ 1028f375c82Sjason #define D_EN_NEXT 0x01000000 /* enable auto next address */ 1038f375c82Sjason #define D_DMA_ON 0x02000000 /* enable dma from scsi XXX */ 1048f375c82Sjason #define D_DSBL_PARITY_CHK \ 1058f375c82Sjason 0x02000000 /* disable checking for parity on bus (default 1:fas) */ 1068f375c82Sjason #define D_A_LOADED 0x04000000 /* address loaded */ 1078f375c82Sjason #define D_NA_LOADED 0x08000000 /* next address loaded */ 1088f375c82Sjason #define D_HW_RESET_FAS366 \ 1098f375c82Sjason 0x08000000 /* hardware reset FAS366 (fas) */ 1108f375c82Sjason #define D_DEV_ID L64854_DEVID /* device ID */ 1118f375c82Sjason #define DMAREV_0 0x00000000 /* Sunray DMA */ 1128f375c82Sjason #define DMAREV_ESC 0x40000000 /* DMA ESC array */ 1138f375c82Sjason #define DMAREV_1 0x80000000 /* 'DMA' */ 1148f375c82Sjason #define DMAREV_PLUS 0x90000000 /* 'DMA+' */ 1158f375c82Sjason #define DMAREV_2 0xa0000000 /* 'DMA2' */ 1168f375c82Sjason #define DMAREV_HME 0xb0000000 /* 'HME' */ 1178f375c82Sjason 1188f375c82Sjason /* 1198f375c82Sjason * revisions 0,1 and ESC have different bits. 1208f375c82Sjason */ 1218f375c82Sjason #define D_ESC_DRAIN 0x00000040 /* rev0,1,esc: drain fifo */ 1228f375c82Sjason #define D_ESC_R_PEND 0x00000400 /* rev0,1: request pending */ 1238f375c82Sjason #define D_ESC_BURST 0x00000800 /* DMA ESC: 16 byte bursts */ 1248f375c82Sjason #define D_ESC_AUTODRAIN 0x00040000 /* DMA ESC: Auto-drain */ 1258f375c82Sjason 126a4c960dbSmiod #define DDMACSR_BITS "\020" \ 127a4c960dbSmiod "\01INT\02ERR\03DR1\04DR2\05IEN" \ 128a4c960dbSmiod "\07SLVERR\010RST\011WRITE\012ENDMA" \ 129a4c960dbSmiod "\016ENCNT\017TC\021DSBL_CSR_DRN" \ 130a4c960dbSmiod "\022DSBL_SCSI_DRN\026TWOCYCLE" \ 131a4c960dbSmiod "\027FASTER\030TCIDIS\031ENNXT\032DMAON" \ 132a4c960dbSmiod "\033ALOADED\034NALOADED" 1338f375c82Sjason 1348f375c82Sjason 1358f375c82Sjason /* 1368f375c82Sjason * ENET DMA control bits. 1378f375c82Sjason */ 1388f375c82Sjason #define E_INT_PEND L64854_INT_PEND /* interrupt pending */ 1398f375c82Sjason #define E_ERR_PEND L64854_ERR_PEND /* error pending */ 1408f375c82Sjason #define E_DRAINING L64854_DRAINING /* fifo draining */ 1418f375c82Sjason #define E_INT_EN L64854_INT_EN /* interrupt enable */ 1428f375c82Sjason #define E_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 1438f375c82Sjason #define E_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 1448f375c82Sjason #define E_RESET L64854_RESET /* reset ENET */ 1458f375c82Sjason #define E_reserved1 0x00000300 /* */ 1468f375c82Sjason #define E_DRAIN 0x00000400 /* force Ecache drain */ 1478f375c82Sjason #define E_DSBL_WR_DRN 0x00000800 /* disable Ecache drain on .. */ 1488f375c82Sjason #define E_DSBL_RD_DRN 0x00001000 /* disable Ecache drain on .. */ 1498f375c82Sjason #define E_reserved2 0x00006000 /* */ 1508f375c82Sjason #define E_ILACC 0x00008000 /* ... */ 1518f375c82Sjason #define E_DSBL_BUF_WR 0x00010000 /* no buffering of slave writes */ 1528f375c82Sjason #define E_DSBL_WR_INVAL 0x00020000 /* no Ecache invalidate on slave writes */ 1538f375c82Sjason 1548f375c82Sjason #define E_reserved3 0x00100000 /* */ 1558f375c82Sjason #define E_LOOP_TEST 0x00200000 /* loopback mode */ 1568f375c82Sjason #define E_TP_AUI 0x00400000 /* 1 for TP, 0 for AUI */ 1578f375c82Sjason #define E_reserved4 0x0c800000 /* */ 1588f375c82Sjason #define E_DEV_ID L64854_DEVID /* ID bits */ 1598f375c82Sjason 160a4c960dbSmiod #define EDMACSR_BITS "\020" \ 161a4c960dbSmiod "\01INT\02ERR\05IEN" \ 162a4c960dbSmiod "\07SLVERR\010RST\011WRITE\013DRAIN" \ 163a4c960dbSmiod "\014DSBL_WR_DRN\015DSBL_RD_DRN\020ILACC" \ 164a4c960dbSmiod "\021DSBL_BUF_WR\022DSBL_WR_INVAL" \ 165a4c960dbSmiod "\026LOOPTEST\027TP" 1668f375c82Sjason 1678f375c82Sjason /* 1688f375c82Sjason * PP DMA control bits. 1698f375c82Sjason */ 1708f375c82Sjason #define P_INT_PEND L64854_INT_PEND /* interrupt pending */ 1718f375c82Sjason #define P_ERR_PEND L64854_ERR_PEND /* error pending */ 1728f375c82Sjason #define P_DRAINING L64854_DRAINING /* fifo draining */ 1738f375c82Sjason #define P_INT_EN L64854_INT_EN /* interrupt enable */ 1748f375c82Sjason #define P_INVALIDATE L64854_INVALIDATE/* invalidate fifo */ 1758f375c82Sjason #define P_SLAVE_ERR L64854_SLAVE_ERR/* slave access size error */ 1768f375c82Sjason #define P_RESET L64854_RESET /* reset PP */ 1778f375c82Sjason #define P_WRITE L64854_WRITE /* 1: xfer to memory */ 1788f375c82Sjason #define P_EN_DMA L64854_EN_DMA /* enable DMA transfers */ 1798f375c82Sjason #define P_reserved1 0x00001c00 /* */ 1808f375c82Sjason #define P_EN_CNT 0x00002000 /* enable counter */ 1818f375c82Sjason #define P_TC 0x00004000 /* terminal count */ 1828f375c82Sjason #define P_reserved2 0x00038000 /* */ 1838f375c82Sjason 1848f375c82Sjason #define P_DIAG 0x00100000 /* ... */ 1858f375c82Sjason #define P_reserved3 0x00600000 /* */ 1868f375c82Sjason #define P_TCI_DIS 0x00800000 /* no interrupt on terminal count */ 1878f375c82Sjason #define P_EN_NEXT 0x01000000 /* enable DMA chaining */ 1888f375c82Sjason #define P_DMA_ON 0x02000000 /* DMA xfers enabled */ 1898f375c82Sjason #define P_A_LOADED 0x04000000 /* addr and byte count valid */ 1908f375c82Sjason #define P_NA_LOADED 0x08000000 /* next addr & count valid but not used */ 1918f375c82Sjason #define P_DEV_ID L64854_DEVID /* ID bits */ 1928f375c82Sjason 193a4c960dbSmiod #define PDMACSR_BITS "\020" \ 194a4c960dbSmiod "\01INT\02ERR\05IEN" \ 195a4c960dbSmiod "\07SLVERR\010RST\011WRITE\012ENDMA" \ 196a4c960dbSmiod "\016ENCNT\017TC\025DIAG\030TCIDIS" \ 197a4c960dbSmiod "\031ENNXT\032DMAON\033ALOADED\034NALOADED" 198