1 /* $OpenBSD: gem.c,v 1.43 2005/08/01 05:45:03 brad Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/timeout.h> 42 #include <sys/mbuf.h> 43 #include <sys/syslog.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 struct cfdriver gem_cd = { 79 NULL, "gem", DV_IFNET 80 }; 81 82 void gem_start(struct ifnet *); 83 void gem_stop(struct ifnet *, int); 84 int gem_ioctl(struct ifnet *, u_long, caddr_t); 85 void gem_tick(void *); 86 void gem_watchdog(struct ifnet *); 87 void gem_shutdown(void *); 88 int gem_init(struct ifnet *); 89 void gem_init_regs(struct gem_softc *sc); 90 static int gem_ringsize(int sz); 91 int gem_meminit(struct gem_softc *); 92 void gem_mifinit(struct gem_softc *); 93 void gem_reset(struct gem_softc *); 94 int gem_reset_rx(struct gem_softc *sc); 95 int gem_reset_tx(struct gem_softc *sc); 96 int gem_disable_rx(struct gem_softc *sc); 97 int gem_disable_tx(struct gem_softc *sc); 98 void gem_rxdrain(struct gem_softc *sc); 99 int gem_add_rxbuf(struct gem_softc *sc, int idx); 100 void gem_setladrf(struct gem_softc *); 101 int gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *); 102 103 /* MII methods & callbacks */ 104 static int gem_mii_readreg(struct device *, int, int); 105 static void gem_mii_writereg(struct device *, int, int, int); 106 static void gem_mii_statchg(struct device *); 107 108 int gem_mediachange(struct ifnet *); 109 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 110 111 struct mbuf *gem_get(struct gem_softc *, int, int); 112 int gem_eint(struct gem_softc *, u_int); 113 int gem_rint(struct gem_softc *); 114 int gem_tint(struct gem_softc *, u_int32_t); 115 116 #ifdef GEM_DEBUG 117 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 118 printf x 119 #else 120 #define DPRINTF(sc, x) /* nothing */ 121 #endif 122 123 124 /* 125 * gem_config: 126 * 127 * Attach a Gem interface to the system. 128 */ 129 void 130 gem_config(sc) 131 struct gem_softc *sc; 132 { 133 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 134 struct mii_data *mii = &sc->sc_mii; 135 struct mii_softc *child; 136 int i, error; 137 struct ifmedia_entry *ifm; 138 139 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 140 141 /* Make sure the chip is stopped. */ 142 ifp->if_softc = sc; 143 gem_reset(sc); 144 145 /* 146 * Allocate the control data structures, and create and load the 147 * DMA map for it. 148 */ 149 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 150 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 151 1, &sc->sc_cdnseg, 0)) != 0) { 152 printf("\n%s: unable to allocate control data, error = %d\n", 153 sc->sc_dev.dv_xname, error); 154 goto fail_0; 155 } 156 157 /* XXX should map this in with correct endianness */ 158 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 159 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 160 BUS_DMA_COHERENT)) != 0) { 161 printf("\n%s: unable to map control data, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_1; 164 } 165 166 if ((error = bus_dmamap_create(sc->sc_dmatag, 167 sizeof(struct gem_control_data), 1, 168 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 169 printf("\n%s: unable to create control data DMA map, " 170 "error = %d\n", sc->sc_dev.dv_xname, error); 171 goto fail_2; 172 } 173 174 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 175 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 176 0)) != 0) { 177 printf("\n%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Create the receive buffer DMA maps. 184 */ 185 for (i = 0; i < GEM_NRXDESC; i++) { 186 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 187 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 188 printf("\n%s: unable to create rx DMA map %d, " 189 "error = %d\n", sc->sc_dev.dv_xname, i, error); 190 goto fail_5; 191 } 192 sc->sc_rxsoft[i].rxs_mbuf = NULL; 193 } 194 /* 195 * Create the transmit buffer DMA maps. 196 */ 197 for (i = 0; i < GEM_NTXDESC; i++) { 198 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 199 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 200 &sc->sc_txd[i].sd_map)) != 0) { 201 printf("\n%s: unable to create tx DMA map %d, " 202 "error = %d\n", sc->sc_dev.dv_xname, i, error); 203 goto fail_6; 204 } 205 sc->sc_txd[i].sd_mbuf = NULL; 206 } 207 208 /* 209 * From this point forward, the attachment cannot fail. A failure 210 * before this point releases all resources that may have been 211 * allocated. 212 */ 213 214 /* Announce ourselves. */ 215 printf(", address %s\n", ether_sprintf(sc->sc_enaddr)); 216 217 /* Get RX FIFO size */ 218 sc->sc_rxfifosize = 64 * 219 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 220 221 /* Initialize ifnet structure. */ 222 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 223 ifp->if_softc = sc; 224 ifp->if_flags = 225 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 226 ifp->if_start = gem_start; 227 ifp->if_ioctl = gem_ioctl; 228 ifp->if_watchdog = gem_watchdog; 229 IFQ_SET_READY(&ifp->if_snd); 230 231 ifp->if_capabilities = IFCAP_VLAN_MTU; 232 233 /* Initialize ifmedia structures and MII info */ 234 mii->mii_ifp = ifp; 235 mii->mii_readreg = gem_mii_readreg; 236 mii->mii_writereg = gem_mii_writereg; 237 mii->mii_statchg = gem_mii_statchg; 238 239 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 240 241 gem_mifinit(sc); 242 243 mii_attach(&sc->sc_dev, mii, 0xffffffff, 244 MII_PHY_ANY, MII_OFFSET_ANY, 0); 245 246 child = LIST_FIRST(&mii->mii_phys); 247 if (child == NULL) { 248 /* No PHY attached */ 249 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 250 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 251 } else { 252 /* 253 * Walk along the list of attached MII devices and 254 * establish an `MII instance' to `phy number' 255 * mapping. We'll use this mapping in media change 256 * requests to determine which phy to use to program 257 * the MIF configuration register. 258 */ 259 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 260 /* 261 * Note: we support just two PHYs: the built-in 262 * internal device and an external on the MII 263 * connector. 264 */ 265 if (child->mii_phy > 1 || child->mii_inst > 1) { 266 printf("%s: cannot accommodate MII device %s" 267 " at phy %d, instance %d\n", 268 sc->sc_dev.dv_xname, 269 child->mii_dev.dv_xname, 270 child->mii_phy, child->mii_inst); 271 continue; 272 } 273 274 sc->sc_phys[child->mii_inst] = child->mii_phy; 275 } 276 277 /* 278 * Now select and activate the PHY we will use. 279 * 280 * The order of preference is External (MDI1), 281 * Internal (MDI0), Serial Link (no MII). 282 */ 283 if (sc->sc_phys[1]) { 284 #ifdef DEBUG 285 printf("using external phy\n"); 286 #endif 287 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 288 } else { 289 #ifdef DEBUG 290 printf("using internal phy\n"); 291 #endif 292 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 293 } 294 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 295 sc->sc_mif_config); 296 297 /* 298 * XXX - we can really do the following ONLY if the 299 * phy indeed has the auto negotiation capability!! 300 */ 301 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 302 } 303 304 /* 305 * If we support GigE media, we support jumbo frames too. 306 * Unless we are Apple. 307 */ 308 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 309 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 310 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 311 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 312 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 313 #if 0 314 if (sc->sc_variant != GEM_APPLE_GMAC) 315 sc->sc_ethercom.ec_capabilities 316 |= ETHERCAP_JUMBO_MTU; 317 #endif 318 319 sc->sc_flags |= GEM_GIGABIT; 320 break; 321 } 322 } 323 324 /* Attach the interface. */ 325 if_attach(ifp); 326 ether_ifattach(ifp); 327 328 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 329 if (sc->sc_sh == NULL) 330 panic("gem_config: can't establish shutdownhook"); 331 332 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 333 return; 334 335 /* 336 * Free any resources we've allocated during the failed attach 337 * attempt. Do this in reverse order and fall through. 338 */ 339 fail_6: 340 for (i = 0; i < GEM_NTXDESC; i++) { 341 if (sc->sc_txd[i].sd_map != NULL) 342 bus_dmamap_destroy(sc->sc_dmatag, 343 sc->sc_txd[i].sd_map); 344 } 345 fail_5: 346 for (i = 0; i < GEM_NRXDESC; i++) { 347 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 348 bus_dmamap_destroy(sc->sc_dmatag, 349 sc->sc_rxsoft[i].rxs_dmamap); 350 } 351 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 352 fail_3: 353 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 354 fail_2: 355 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 356 sizeof(struct gem_control_data)); 357 fail_1: 358 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 359 fail_0: 360 return; 361 } 362 363 364 void 365 gem_tick(arg) 366 void *arg; 367 { 368 struct gem_softc *sc = arg; 369 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 370 bus_space_tag_t t = sc->sc_bustag; 371 bus_space_handle_t mac = sc->sc_h; 372 int s; 373 374 /* unload collisions counters */ 375 ifp->if_collisions += 376 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 377 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 378 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 379 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 380 381 /* clear the hardware counters */ 382 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 383 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 384 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 385 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 386 387 s = splimp(); 388 mii_tick(&sc->sc_mii); 389 splx(s); 390 391 timeout_add(&sc->sc_tick_ch, hz); 392 } 393 394 void 395 gem_reset(sc) 396 struct gem_softc *sc; 397 { 398 bus_space_tag_t t = sc->sc_bustag; 399 bus_space_handle_t h = sc->sc_h; 400 int i; 401 int s; 402 403 s = splimp(); 404 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 405 gem_reset_rx(sc); 406 gem_reset_tx(sc); 407 408 /* Do a full reset */ 409 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 410 for (i=TRIES; i--; delay(100)) 411 if ((bus_space_read_4(t, h, GEM_RESET) & 412 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 413 break; 414 if ((bus_space_read_4(t, h, GEM_RESET) & 415 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 416 printf("%s: cannot reset device\n", 417 sc->sc_dev.dv_xname); 418 } 419 splx(s); 420 } 421 422 423 /* 424 * gem_rxdrain: 425 * 426 * Drain the receive queue. 427 */ 428 void 429 gem_rxdrain(struct gem_softc *sc) 430 { 431 struct gem_rxsoft *rxs; 432 int i; 433 434 for (i = 0; i < GEM_NRXDESC; i++) { 435 rxs = &sc->sc_rxsoft[i]; 436 if (rxs->rxs_mbuf != NULL) { 437 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 438 m_freem(rxs->rxs_mbuf); 439 rxs->rxs_mbuf = NULL; 440 } 441 } 442 } 443 444 /* 445 * Reset the whole thing. 446 */ 447 void 448 gem_stop(struct ifnet *ifp, int disable) 449 { 450 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 451 struct gem_sxd *sd; 452 u_int32_t i; 453 454 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 455 456 timeout_del(&sc->sc_tick_ch); 457 458 /* 459 * Mark the interface down and cancel the watchdog timer. 460 */ 461 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 462 ifp->if_timer = 0; 463 464 mii_down(&sc->sc_mii); 465 466 gem_reset_rx(sc); 467 gem_reset_tx(sc); 468 469 /* 470 * Release any queued transmit buffers. 471 */ 472 for (i = 0; i < GEM_NTXDESC; i++) { 473 sd = &sc->sc_txd[i]; 474 if (sd->sd_mbuf != NULL) { 475 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 476 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 477 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 478 m_freem(sd->sd_mbuf); 479 sd->sd_mbuf = NULL; 480 } 481 } 482 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 483 484 if (disable) { 485 gem_rxdrain(sc); 486 } 487 } 488 489 490 /* 491 * Reset the receiver 492 */ 493 int 494 gem_reset_rx(struct gem_softc *sc) 495 { 496 bus_space_tag_t t = sc->sc_bustag; 497 bus_space_handle_t h = sc->sc_h; 498 int i; 499 500 /* 501 * Resetting while DMA is in progress can cause a bus hang, so we 502 * disable DMA first. 503 */ 504 gem_disable_rx(sc); 505 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 506 /* Wait till it finishes */ 507 for (i = TRIES; i--; delay(100)) 508 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 509 break; 510 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 511 printf("%s: cannot disable rx dma\n", 512 sc->sc_dev.dv_xname); 513 514 /* Wait 5ms extra. */ 515 delay(5000); 516 517 /* Finally, reset the ERX */ 518 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 519 /* Wait till it finishes */ 520 for (i = TRIES; i--; delay(100)) 521 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 522 break; 523 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 524 printf("%s: cannot reset receiver\n", 525 sc->sc_dev.dv_xname); 526 return (1); 527 } 528 return (0); 529 } 530 531 532 /* 533 * Reset the transmitter 534 */ 535 int 536 gem_reset_tx(struct gem_softc *sc) 537 { 538 bus_space_tag_t t = sc->sc_bustag; 539 bus_space_handle_t h = sc->sc_h; 540 int i; 541 542 /* 543 * Resetting while DMA is in progress can cause a bus hang, so we 544 * disable DMA first. 545 */ 546 gem_disable_tx(sc); 547 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 548 /* Wait till it finishes */ 549 for (i = TRIES; i--; delay(100)) 550 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 551 break; 552 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 553 printf("%s: cannot disable tx dma\n", 554 sc->sc_dev.dv_xname); 555 556 /* Wait 5ms extra. */ 557 delay(5000); 558 559 /* Finally, reset the ETX */ 560 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 561 /* Wait till it finishes */ 562 for (i = TRIES; i--; delay(100)) 563 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 564 break; 565 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 566 printf("%s: cannot reset transmitter\n", 567 sc->sc_dev.dv_xname); 568 return (1); 569 } 570 return (0); 571 } 572 573 /* 574 * disable receiver. 575 */ 576 int 577 gem_disable_rx(struct gem_softc *sc) 578 { 579 bus_space_tag_t t = sc->sc_bustag; 580 bus_space_handle_t h = sc->sc_h; 581 int i; 582 u_int32_t cfg; 583 584 /* Flip the enable bit */ 585 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 586 cfg &= ~GEM_MAC_RX_ENABLE; 587 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 588 589 /* Wait for it to finish */ 590 for (i = TRIES; i--; delay(100)) 591 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 592 GEM_MAC_RX_ENABLE) == 0) 593 return (0); 594 return (1); 595 } 596 597 /* 598 * disable transmitter. 599 */ 600 int 601 gem_disable_tx(struct gem_softc *sc) 602 { 603 bus_space_tag_t t = sc->sc_bustag; 604 bus_space_handle_t h = sc->sc_h; 605 int i; 606 u_int32_t cfg; 607 608 /* Flip the enable bit */ 609 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 610 cfg &= ~GEM_MAC_TX_ENABLE; 611 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 612 613 /* Wait for it to finish */ 614 for (i = TRIES; i--; delay(100)) 615 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 616 GEM_MAC_TX_ENABLE) == 0) 617 return (0); 618 return (1); 619 } 620 621 /* 622 * Initialize interface. 623 */ 624 int 625 gem_meminit(struct gem_softc *sc) 626 { 627 struct gem_rxsoft *rxs; 628 int i, error; 629 630 /* 631 * Initialize the transmit descriptor ring. 632 */ 633 for (i = 0; i < GEM_NTXDESC; i++) { 634 sc->sc_txdescs[i].gd_flags = 0; 635 sc->sc_txdescs[i].gd_addr = 0; 636 } 637 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 638 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 639 640 /* 641 * Initialize the receive descriptor and receive job 642 * descriptor rings. 643 */ 644 for (i = 0; i < GEM_NRXDESC; i++) { 645 rxs = &sc->sc_rxsoft[i]; 646 if (rxs->rxs_mbuf == NULL) { 647 if ((error = gem_add_rxbuf(sc, i)) != 0) { 648 printf("%s: unable to allocate or map rx " 649 "buffer %d, error = %d\n", 650 sc->sc_dev.dv_xname, i, error); 651 /* 652 * XXX Should attempt to run with fewer receive 653 * XXX buffers instead of just failing. 654 */ 655 gem_rxdrain(sc); 656 return (1); 657 } 658 } else 659 GEM_INIT_RXDESC(sc, i); 660 } 661 sc->sc_rxptr = 0; 662 663 return (0); 664 } 665 666 static int 667 gem_ringsize(int sz) 668 { 669 switch (sz) { 670 case 32: 671 return GEM_RING_SZ_32; 672 case 64: 673 return GEM_RING_SZ_64; 674 case 128: 675 return GEM_RING_SZ_128; 676 case 256: 677 return GEM_RING_SZ_256; 678 case 512: 679 return GEM_RING_SZ_512; 680 case 1024: 681 return GEM_RING_SZ_1024; 682 case 2048: 683 return GEM_RING_SZ_2048; 684 case 4096: 685 return GEM_RING_SZ_4096; 686 case 8192: 687 return GEM_RING_SZ_8192; 688 default: 689 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 690 return GEM_RING_SZ_32; 691 } 692 } 693 694 /* 695 * Initialization of interface; set up initialization block 696 * and transmit/receive descriptor rings. 697 */ 698 int 699 gem_init(struct ifnet *ifp) 700 { 701 702 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 703 bus_space_tag_t t = sc->sc_bustag; 704 bus_space_handle_t h = sc->sc_h; 705 int s; 706 u_int max_frame_size; 707 u_int32_t v; 708 709 s = splimp(); 710 711 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 712 /* 713 * Initialization sequence. The numbered steps below correspond 714 * to the sequence outlined in section 6.3.5.1 in the Ethernet 715 * Channel Engine manual (part of the PCIO manual). 716 * See also the STP2002-STQ document from Sun Microsystems. 717 */ 718 719 /* step 1 & 2. Reset the Ethernet Channel */ 720 gem_stop(ifp, 0); 721 gem_reset(sc); 722 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 723 724 /* Re-initialize the MIF */ 725 gem_mifinit(sc); 726 727 /* Call MI reset function if any */ 728 if (sc->sc_hwreset) 729 (*sc->sc_hwreset)(sc); 730 731 /* step 3. Setup data structures in host memory */ 732 gem_meminit(sc); 733 734 /* step 4. TX MAC registers & counters */ 735 gem_init_regs(sc); 736 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 737 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 738 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 739 740 /* step 5. RX MAC registers & counters */ 741 gem_setladrf(sc); 742 743 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 744 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 745 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 746 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 747 748 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 749 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 750 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 751 752 /* step 8. Global Configuration & Interrupt Mask */ 753 bus_space_write_4(t, h, GEM_INTMASK, 754 ~(GEM_INTR_TX_INTME| 755 GEM_INTR_TX_EMPTY| 756 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 757 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 758 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 759 GEM_INTR_BERR)); 760 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 761 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 762 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 763 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 764 765 /* step 9. ETX Configuration: use mostly default values */ 766 767 /* Enable DMA */ 768 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 769 bus_space_write_4(t, h, GEM_TX_CONFIG, 770 v|GEM_TX_CONFIG_TXDMA_EN| 771 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 772 bus_space_write_4(t, h, GEM_TX_KICK, 0); 773 774 /* step 10. ERX Configuration */ 775 776 /* Encode Receive Descriptor ring size: four possible values */ 777 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 778 779 /* Enable DMA */ 780 bus_space_write_4(t, h, GEM_RX_CONFIG, 781 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 782 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 783 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 784 /* 785 * The following value is for an OFF Threshold of about 3/4 full 786 * and an ON Threshold of 1/4 full. 787 */ 788 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 789 (3 * sc->sc_rxfifosize / 256) | 790 ( (sc->sc_rxfifosize / 256) << 12)); 791 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 792 793 /* step 11. Configure Media */ 794 mii_mediachg(&sc->sc_mii); 795 796 /* step 12. RX_MAC Configuration Register */ 797 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 798 v |= GEM_MAC_RX_ENABLE; 799 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 800 801 /* step 14. Issue Transmit Pending command */ 802 803 /* Call MI initialization function if any */ 804 if (sc->sc_hwinit) 805 (*sc->sc_hwinit)(sc); 806 807 808 /* step 15. Give the receiver a swift kick */ 809 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 810 811 /* Start the one second timer. */ 812 timeout_add(&sc->sc_tick_ch, hz); 813 814 ifp->if_flags |= IFF_RUNNING; 815 ifp->if_flags &= ~IFF_OACTIVE; 816 ifp->if_timer = 0; 817 splx(s); 818 819 return (0); 820 } 821 822 void 823 gem_init_regs(struct gem_softc *sc) 824 { 825 bus_space_tag_t t = sc->sc_bustag; 826 bus_space_handle_t h = sc->sc_h; 827 u_int32_t v; 828 829 /* These regs are not cleared on reset */ 830 sc->sc_inited = 0; 831 if (!sc->sc_inited) { 832 833 /* Wooo. Magic values. */ 834 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 835 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 836 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 837 838 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 839 /* Max frame and max burst size */ 840 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 841 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 842 843 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 844 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 845 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 846 /* Dunno.... */ 847 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 848 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 849 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 850 851 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 852 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 853 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 854 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 855 /* MAC control addr set to 0:1:c2:0:1:80 */ 856 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 857 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 858 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 859 860 /* MAC filter addr set to 0:0:0:0:0:0 */ 861 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 862 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 863 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 864 865 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 866 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 867 868 sc->sc_inited = 1; 869 } 870 871 /* Counters need to be zeroed */ 872 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 873 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 874 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 876 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 877 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 878 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 879 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 880 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 881 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 882 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 883 884 /* Un-pause stuff */ 885 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 886 887 /* 888 * Set the station address. 889 */ 890 bus_space_write_4(t, h, GEM_MAC_ADDR0, 891 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 892 bus_space_write_4(t, h, GEM_MAC_ADDR1, 893 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 894 bus_space_write_4(t, h, GEM_MAC_ADDR2, 895 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 896 897 898 /* 899 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 900 */ 901 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 902 v = GEM_MAC_XIF_TX_MII_ENA; 903 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 904 v |= GEM_MAC_XIF_FDPLX_LED; 905 if (sc->sc_flags & GEM_GIGABIT) 906 v |= GEM_MAC_XIF_GMII_MODE; 907 } 908 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 909 } 910 911 /* 912 * Receive interrupt. 913 */ 914 int 915 gem_rint(sc) 916 struct gem_softc *sc; 917 { 918 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 919 bus_space_tag_t t = sc->sc_bustag; 920 bus_space_handle_t h = sc->sc_h; 921 struct ether_header *eh; 922 struct gem_rxsoft *rxs; 923 struct mbuf *m; 924 u_int64_t rxstat; 925 int i, len; 926 927 for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) { 928 rxs = &sc->sc_rxsoft[i]; 929 930 GEM_CDRXSYNC(sc, i, 931 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 932 933 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 934 935 if (rxstat & GEM_RD_OWN) { 936 /* 937 * We have processed all of the receive buffers. 938 */ 939 break; 940 } 941 942 if (rxstat & GEM_RD_BAD_CRC) { 943 printf("%s: receive error: CRC error\n", 944 sc->sc_dev.dv_xname); 945 GEM_INIT_RXDESC(sc, i); 946 continue; 947 } 948 949 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 950 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 951 #ifdef GEM_DEBUG 952 if (ifp->if_flags & IFF_DEBUG) { 953 printf(" rxsoft %p descriptor %d: ", rxs, i); 954 printf("gd_flags: 0x%016llx\t", (long long) 955 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 956 printf("gd_addr: 0x%016llx\n", (long long) 957 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 958 } 959 #endif 960 961 /* 962 * No errors; receive the packet. Note the Gem 963 * includes the CRC with every packet. 964 */ 965 len = GEM_RD_BUFLEN(rxstat); 966 967 /* 968 * Allocate a new mbuf cluster. If that fails, we are 969 * out of memory, and must drop the packet and recycle 970 * the buffer that's already attached to this descriptor. 971 */ 972 m = rxs->rxs_mbuf; 973 if (gem_add_rxbuf(sc, i) != 0) { 974 ifp->if_ierrors++; 975 GEM_INIT_RXDESC(sc, i); 976 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 977 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 978 continue; 979 } 980 m->m_data += 2; /* We're already off by two */ 981 982 ifp->if_ipackets++; 983 eh = mtod(m, struct ether_header *); 984 m->m_pkthdr.rcvif = ifp; 985 m->m_pkthdr.len = m->m_len = len; 986 987 #if NBPFILTER > 0 988 /* 989 * Pass this up to any BPF listeners, but only 990 * pass it up the stack if its for us. 991 */ 992 if (ifp->if_bpf) 993 bpf_mtap(ifp->if_bpf, m); 994 #endif /* NPBFILTER > 0 */ 995 996 /* Pass it on. */ 997 ether_input_mbuf(ifp, m); 998 } 999 1000 /* Update the receive pointer. */ 1001 sc->sc_rxptr = i; 1002 bus_space_write_4(t, h, GEM_RX_KICK, i); 1003 1004 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1005 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1006 1007 return (1); 1008 } 1009 1010 1011 /* 1012 * gem_add_rxbuf: 1013 * 1014 * Add a receive buffer to the indicated descriptor. 1015 */ 1016 int 1017 gem_add_rxbuf(struct gem_softc *sc, int idx) 1018 { 1019 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1020 struct mbuf *m; 1021 int error; 1022 1023 MGETHDR(m, M_DONTWAIT, MT_DATA); 1024 if (m == NULL) 1025 return (ENOBUFS); 1026 1027 MCLGET(m, M_DONTWAIT); 1028 if ((m->m_flags & M_EXT) == 0) { 1029 m_freem(m); 1030 return (ENOBUFS); 1031 } 1032 1033 #ifdef GEM_DEBUG 1034 /* bzero the packet to check dma */ 1035 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1036 #endif 1037 1038 if (rxs->rxs_mbuf != NULL) 1039 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1040 1041 rxs->rxs_mbuf = m; 1042 1043 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1044 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1045 BUS_DMA_READ|BUS_DMA_NOWAIT); 1046 if (error) { 1047 printf("%s: can't load rx DMA map %d, error = %d\n", 1048 sc->sc_dev.dv_xname, idx, error); 1049 panic("gem_add_rxbuf"); /* XXX */ 1050 } 1051 1052 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1053 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1054 1055 GEM_INIT_RXDESC(sc, idx); 1056 1057 return (0); 1058 } 1059 1060 1061 int 1062 gem_eint(sc, status) 1063 struct gem_softc *sc; 1064 u_int status; 1065 { 1066 if ((status & GEM_INTR_MIF) != 0) { 1067 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1068 return (1); 1069 } 1070 1071 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1072 return (1); 1073 } 1074 1075 1076 int 1077 gem_intr(v) 1078 void *v; 1079 { 1080 struct gem_softc *sc = (struct gem_softc *)v; 1081 bus_space_tag_t t = sc->sc_bustag; 1082 bus_space_handle_t seb = sc->sc_h; 1083 u_int32_t status; 1084 int r = 0; 1085 1086 status = bus_space_read_4(t, seb, GEM_STATUS); 1087 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1088 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1089 1090 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1091 r |= gem_eint(sc, status); 1092 1093 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1094 r |= gem_tint(sc, status); 1095 1096 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1097 r |= gem_rint(sc); 1098 1099 /* We should eventually do more than just print out error stats. */ 1100 if (status & GEM_INTR_TX_MAC) { 1101 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1102 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1103 printf("%s: MAC tx fault, status %x\n", 1104 sc->sc_dev.dv_xname, txstat); 1105 } 1106 if (status & GEM_INTR_RX_MAC) { 1107 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1108 1109 rxstat &= ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1110 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1111 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1112 1113 gem_init(ifp); 1114 ifp->if_ierrors++; 1115 } else { 1116 /* 1117 * Leave this in here until I figure out what to do 1118 * about other errors. 1119 */ 1120 printf("%s: MAC rx fault, status %x\n", 1121 sc->sc_dev.dv_xname, rxstat); 1122 } 1123 } 1124 return (r); 1125 } 1126 1127 1128 void 1129 gem_watchdog(ifp) 1130 struct ifnet *ifp; 1131 { 1132 struct gem_softc *sc = ifp->if_softc; 1133 1134 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1135 "GEM_MAC_RX_CONFIG %x\n", 1136 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1137 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1138 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1139 1140 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1141 ++ifp->if_oerrors; 1142 1143 /* Try to get more packets going. */ 1144 gem_init(ifp); 1145 } 1146 1147 /* 1148 * Initialize the MII Management Interface 1149 */ 1150 void 1151 gem_mifinit(sc) 1152 struct gem_softc *sc; 1153 { 1154 bus_space_tag_t t = sc->sc_bustag; 1155 bus_space_handle_t mif = sc->sc_h; 1156 1157 /* Configure the MIF in frame mode */ 1158 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1159 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1160 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1161 } 1162 1163 /* 1164 * MII interface 1165 * 1166 * The GEM MII interface supports at least three different operating modes: 1167 * 1168 * Bitbang mode is implemented using data, clock and output enable registers. 1169 * 1170 * Frame mode is implemented by loading a complete frame into the frame 1171 * register and polling the valid bit for completion. 1172 * 1173 * Polling mode uses the frame register but completion is indicated by 1174 * an interrupt. 1175 * 1176 */ 1177 static int 1178 gem_mii_readreg(self, phy, reg) 1179 struct device *self; 1180 int phy, reg; 1181 { 1182 struct gem_softc *sc = (void *)self; 1183 bus_space_tag_t t = sc->sc_bustag; 1184 bus_space_handle_t mif = sc->sc_h; 1185 int n; 1186 u_int32_t v; 1187 1188 #ifdef GEM_DEBUG 1189 if (sc->sc_debug) 1190 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1191 #endif 1192 1193 /* Construct the frame command */ 1194 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1195 GEM_MIF_FRAME_READ; 1196 1197 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1198 for (n = 0; n < 100; n++) { 1199 DELAY(1); 1200 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1201 if (v & GEM_MIF_FRAME_TA0) 1202 return (v & GEM_MIF_FRAME_DATA); 1203 } 1204 1205 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1206 return (0); 1207 } 1208 1209 static void 1210 gem_mii_writereg(self, phy, reg, val) 1211 struct device *self; 1212 int phy, reg, val; 1213 { 1214 struct gem_softc *sc = (void *)self; 1215 bus_space_tag_t t = sc->sc_bustag; 1216 bus_space_handle_t mif = sc->sc_h; 1217 int n; 1218 u_int32_t v; 1219 1220 #ifdef GEM_DEBUG 1221 if (sc->sc_debug) 1222 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1223 phy, reg, val); 1224 #endif 1225 1226 #if 0 1227 /* Select the desired PHY in the MIF configuration register */ 1228 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1229 /* Clear PHY select bit */ 1230 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1231 if (phy == GEM_PHYAD_EXTERNAL) 1232 /* Set PHY select bit to get at external device */ 1233 v |= GEM_MIF_CONFIG_PHY_SEL; 1234 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1235 #endif 1236 /* Construct the frame command */ 1237 v = GEM_MIF_FRAME_WRITE | 1238 (phy << GEM_MIF_PHY_SHIFT) | 1239 (reg << GEM_MIF_REG_SHIFT) | 1240 (val & GEM_MIF_FRAME_DATA); 1241 1242 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1243 for (n = 0; n < 100; n++) { 1244 DELAY(1); 1245 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1246 if (v & GEM_MIF_FRAME_TA0) 1247 return; 1248 } 1249 1250 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1251 } 1252 1253 static void 1254 gem_mii_statchg(dev) 1255 struct device *dev; 1256 { 1257 struct gem_softc *sc = (void *)dev; 1258 #ifdef GEM_DEBUG 1259 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1260 #endif 1261 bus_space_tag_t t = sc->sc_bustag; 1262 bus_space_handle_t mac = sc->sc_h; 1263 u_int32_t v; 1264 1265 #ifdef GEM_DEBUG 1266 if (sc->sc_debug) 1267 printf("gem_mii_statchg: status change: phy = %d\n", 1268 sc->sc_phys[instance]); 1269 #endif 1270 1271 1272 /* Set tx full duplex options */ 1273 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1274 delay(10000); /* reg must be cleared and delay before changing. */ 1275 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1276 GEM_MAC_TX_ENABLE; 1277 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1278 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1279 } 1280 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1281 1282 /* XIF Configuration */ 1283 /* We should really calculate all this rather than rely on defaults */ 1284 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1285 v = GEM_MAC_XIF_LINK_LED; 1286 v |= GEM_MAC_XIF_TX_MII_ENA; 1287 /* If an external transceiver is connected, enable its MII drivers */ 1288 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1289 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1290 /* External MII needs echo disable if half duplex. */ 1291 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1292 /* turn on full duplex LED */ 1293 v |= GEM_MAC_XIF_FDPLX_LED; 1294 else 1295 /* half duplex -- disable echo */ 1296 v |= GEM_MAC_XIF_ECHO_DISABL; 1297 1298 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1299 case IFM_1000_T: /* Gigabit using GMII interface */ 1300 v |= GEM_MAC_XIF_GMII_MODE; 1301 break; 1302 default: 1303 v &= ~GEM_MAC_XIF_GMII_MODE; 1304 } 1305 } else 1306 /* Internal MII needs buf enable */ 1307 v |= GEM_MAC_XIF_MII_BUF_ENA; 1308 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1309 } 1310 1311 int 1312 gem_mediachange(ifp) 1313 struct ifnet *ifp; 1314 { 1315 struct gem_softc *sc = ifp->if_softc; 1316 struct mii_data *mii = &sc->sc_mii; 1317 1318 if (mii->mii_instance) { 1319 struct mii_softc *miisc; 1320 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1321 miisc = LIST_NEXT(miisc, mii_list)) 1322 mii_phy_reset(miisc); 1323 } 1324 1325 return (mii_mediachg(&sc->sc_mii)); 1326 } 1327 1328 void 1329 gem_mediastatus(ifp, ifmr) 1330 struct ifnet *ifp; 1331 struct ifmediareq *ifmr; 1332 { 1333 struct gem_softc *sc = ifp->if_softc; 1334 1335 mii_pollstat(&sc->sc_mii); 1336 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1337 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1338 } 1339 1340 /* 1341 * Process an ioctl request. 1342 */ 1343 int 1344 gem_ioctl(ifp, cmd, data) 1345 struct ifnet *ifp; 1346 u_long cmd; 1347 caddr_t data; 1348 { 1349 struct gem_softc *sc = ifp->if_softc; 1350 struct ifaddr *ifa = (struct ifaddr *)data; 1351 struct ifreq *ifr = (struct ifreq *)data; 1352 int s, error = 0; 1353 1354 s = splimp(); 1355 1356 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1357 splx(s); 1358 return (error); 1359 } 1360 1361 switch (cmd) { 1362 1363 case SIOCSIFADDR: 1364 ifp->if_flags |= IFF_UP; 1365 1366 switch (ifa->ifa_addr->sa_family) { 1367 #ifdef INET 1368 case AF_INET: 1369 gem_init(ifp); 1370 arp_ifinit(&sc->sc_arpcom, ifa); 1371 break; 1372 #endif 1373 default: 1374 gem_init(ifp); 1375 break; 1376 } 1377 break; 1378 1379 case SIOCSIFFLAGS: 1380 if ((ifp->if_flags & IFF_UP) == 0 && 1381 (ifp->if_flags & IFF_RUNNING) != 0) { 1382 /* 1383 * If interface is marked down and it is running, then 1384 * stop it. 1385 */ 1386 gem_stop(ifp, 1); 1387 ifp->if_flags &= ~IFF_RUNNING; 1388 } else if ((ifp->if_flags & IFF_UP) != 0 && 1389 (ifp->if_flags & IFF_RUNNING) == 0) { 1390 /* 1391 * If interface is marked up and it is stopped, then 1392 * start it. 1393 */ 1394 gem_init(ifp); 1395 } else if ((ifp->if_flags & IFF_UP) != 0) { 1396 /* 1397 * Reset the interface to pick up changes in any other 1398 * flags that affect hardware registers. 1399 */ 1400 /*gem_stop(sc);*/ 1401 gem_init(ifp); 1402 } 1403 #ifdef HMEDEBUG 1404 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1405 #endif 1406 break; 1407 1408 case SIOCADDMULTI: 1409 case SIOCDELMULTI: 1410 error = (cmd == SIOCADDMULTI) ? 1411 ether_addmulti(ifr, &sc->sc_arpcom) : 1412 ether_delmulti(ifr, &sc->sc_arpcom); 1413 1414 if (error == ENETRESET) { 1415 /* 1416 * Multicast list has changed; set the hardware filter 1417 * accordingly. 1418 */ 1419 if (ifp->if_flags & IFF_RUNNING) 1420 gem_init(ifp); 1421 error = 0; 1422 } 1423 break; 1424 1425 case SIOCGIFMEDIA: 1426 case SIOCSIFMEDIA: 1427 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1428 break; 1429 1430 default: 1431 error = EINVAL; 1432 break; 1433 } 1434 1435 splx(s); 1436 return (error); 1437 } 1438 1439 1440 void 1441 gem_shutdown(arg) 1442 void *arg; 1443 { 1444 struct gem_softc *sc = (struct gem_softc *)arg; 1445 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1446 1447 gem_stop(ifp, 1); 1448 } 1449 1450 /* 1451 * Set up the logical address filter. 1452 */ 1453 void 1454 gem_setladrf(sc) 1455 struct gem_softc *sc; 1456 { 1457 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1458 struct ether_multi *enm; 1459 struct ether_multistep step; 1460 struct arpcom *ac = &sc->sc_arpcom; 1461 bus_space_tag_t t = sc->sc_bustag; 1462 bus_space_handle_t h = sc->sc_h; 1463 u_int32_t crc, hash[16], v; 1464 int i; 1465 1466 /* Get current RX configuration */ 1467 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1468 1469 1470 /* 1471 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1472 * and hash filter. Depending on the case, the right bit will be 1473 * enabled. 1474 */ 1475 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1476 GEM_MAC_RX_PROMISC_GRP); 1477 1478 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1479 /* Turn on promiscuous mode */ 1480 v |= GEM_MAC_RX_PROMISCUOUS; 1481 ifp->if_flags |= IFF_ALLMULTI; 1482 goto chipit; 1483 } 1484 1485 /* 1486 * Set up multicast address filter by passing all multicast addresses 1487 * through a crc generator, and then using the high order 8 bits as an 1488 * index into the 256 bit logical address filter. The high order 4 1489 * bits select the word, while the other 4 bits select the bit within 1490 * the word (where bit 0 is the MSB). 1491 */ 1492 1493 /* Clear hash table */ 1494 for (i = 0; i < 16; i++) 1495 hash[i] = 0; 1496 1497 1498 ETHER_FIRST_MULTI(step, ac, enm); 1499 while (enm != NULL) { 1500 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1501 /* 1502 * We must listen to a range of multicast addresses. 1503 * For now, just accept all multicasts, rather than 1504 * trying to set only those filter bits needed to match 1505 * the range. (At this time, the only use of address 1506 * ranges is for IP multicast routing, for which the 1507 * range is big enough to require all bits set.) 1508 * XXX use the addr filter for this 1509 */ 1510 ifp->if_flags |= IFF_ALLMULTI; 1511 v |= GEM_MAC_RX_PROMISC_GRP; 1512 goto chipit; 1513 } 1514 1515 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1516 1517 /* Just want the 8 most significant bits. */ 1518 crc >>= 24; 1519 1520 /* Set the corresponding bit in the filter. */ 1521 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1522 1523 ETHER_NEXT_MULTI(step, enm); 1524 } 1525 1526 v |= GEM_MAC_RX_HASH_FILTER; 1527 ifp->if_flags &= ~IFF_ALLMULTI; 1528 1529 /* Now load the hash table into the chip (if we are using it) */ 1530 for (i = 0; i < 16; i++) { 1531 bus_space_write_4(t, h, 1532 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1533 hash[i]); 1534 } 1535 1536 chipit: 1537 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1538 } 1539 1540 int 1541 gem_encap(sc, mhead, bixp) 1542 struct gem_softc *sc; 1543 struct mbuf *mhead; 1544 u_int32_t *bixp; 1545 { 1546 u_int64_t flags; 1547 u_int32_t cur, frag, i; 1548 bus_dmamap_t map; 1549 1550 cur = frag = *bixp; 1551 map = sc->sc_txd[cur].sd_map; 1552 1553 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1554 BUS_DMA_NOWAIT) != 0) { 1555 return (ENOBUFS); 1556 } 1557 1558 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) { 1559 bus_dmamap_unload(sc->sc_dmatag, map); 1560 return (ENOBUFS); 1561 } 1562 1563 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1564 BUS_DMASYNC_PREWRITE); 1565 1566 for (i = 0; i < map->dm_nsegs; i++) { 1567 sc->sc_txdescs[frag].gd_addr = 1568 GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr); 1569 flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) | 1570 (i == 0 ? GEM_TD_START_OF_PACKET : 0) | 1571 ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0); 1572 sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags); 1573 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1574 GEM_CDTXOFF(frag), sizeof(struct gem_desc), 1575 BUS_DMASYNC_PREWRITE); 1576 cur = frag; 1577 if (++frag == GEM_NTXDESC) 1578 frag = 0; 1579 } 1580 1581 sc->sc_tx_cnt += map->dm_nsegs; 1582 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1583 sc->sc_txd[cur].sd_map = map; 1584 sc->sc_txd[cur].sd_mbuf = mhead; 1585 1586 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, frag); 1587 1588 *bixp = frag; 1589 1590 /* sync descriptors */ 1591 1592 return (0); 1593 } 1594 1595 /* 1596 * Transmit interrupt. 1597 */ 1598 int 1599 gem_tint(sc, status) 1600 struct gem_softc *sc; 1601 u_int32_t status; 1602 { 1603 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1604 struct gem_sxd *sd; 1605 u_int32_t cons, hwcons; 1606 1607 hwcons = status >> 19; 1608 cons = sc->sc_tx_cons; 1609 while (cons != hwcons) { 1610 sd = &sc->sc_txd[cons]; 1611 if (sd->sd_mbuf != NULL) { 1612 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1613 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1614 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1615 m_freem(sd->sd_mbuf); 1616 sd->sd_mbuf = NULL; 1617 } 1618 sc->sc_tx_cnt--; 1619 ifp->if_opackets++; 1620 if (++cons == GEM_NTXDESC) 1621 cons = 0; 1622 } 1623 sc->sc_tx_cons = cons; 1624 1625 gem_start(ifp); 1626 1627 if (sc->sc_tx_cnt == 0) 1628 ifp->if_timer = 0; 1629 1630 return (1); 1631 } 1632 1633 void 1634 gem_start(ifp) 1635 struct ifnet *ifp; 1636 { 1637 struct gem_softc *sc = ifp->if_softc; 1638 struct mbuf *m; 1639 u_int32_t bix; 1640 1641 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1642 return; 1643 1644 bix = sc->sc_tx_prod; 1645 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1646 IFQ_POLL(&ifp->if_snd, m); 1647 if (m == NULL) 1648 break; 1649 1650 #if NBPFILTER > 0 1651 /* 1652 * If BPF is listening on this interface, let it see the 1653 * packet before we commit it to the wire. 1654 */ 1655 if (ifp->if_bpf) 1656 bpf_mtap(ifp->if_bpf, m); 1657 #endif 1658 1659 /* 1660 * Encapsulate this packet and start it going... 1661 * or fail... 1662 */ 1663 if (gem_encap(sc, m, &bix)) { 1664 ifp->if_timer = 2; 1665 break; 1666 } 1667 1668 IFQ_DEQUEUE(&ifp->if_snd, m); 1669 ifp->if_timer = 5; 1670 } 1671 1672 sc->sc_tx_prod = bix; 1673 } 1674