1 /* $OpenBSD: gem.c,v 1.50 2005/11/02 02:15:12 brad Exp $ */ 2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37 #include "bpfilter.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/timeout.h> 42 #include <sys/mbuf.h> 43 #include <sys/syslog.h> 44 #include <sys/malloc.h> 45 #include <sys/kernel.h> 46 #include <sys/socket.h> 47 #include <sys/ioctl.h> 48 #include <sys/errno.h> 49 #include <sys/device.h> 50 51 #include <machine/endian.h> 52 53 #include <net/if.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 #endif 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 struct cfdriver gem_cd = { 79 NULL, "gem", DV_IFNET 80 }; 81 82 void gem_start(struct ifnet *); 83 void gem_stop(struct ifnet *, int); 84 int gem_ioctl(struct ifnet *, u_long, caddr_t); 85 void gem_tick(void *); 86 void gem_watchdog(struct ifnet *); 87 void gem_shutdown(void *); 88 int gem_init(struct ifnet *); 89 void gem_init_regs(struct gem_softc *); 90 int gem_ringsize(int); 91 int gem_meminit(struct gem_softc *); 92 void gem_mifinit(struct gem_softc *); 93 int gem_bitwait(struct gem_softc *, int, u_int32_t, u_int32_t); 94 void gem_reset(struct gem_softc *); 95 int gem_reset_rx(struct gem_softc *); 96 int gem_reset_tx(struct gem_softc *); 97 int gem_disable_rx(struct gem_softc *); 98 int gem_disable_tx(struct gem_softc *); 99 void gem_rxdrain(struct gem_softc *); 100 int gem_add_rxbuf(struct gem_softc *, int idx); 101 void gem_setladrf(struct gem_softc *); 102 int gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *); 103 104 /* MII methods & callbacks */ 105 int gem_mii_readreg(struct device *, int, int); 106 void gem_mii_writereg(struct device *, int, int, int); 107 void gem_mii_statchg(struct device *); 108 109 int gem_mediachange(struct ifnet *); 110 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 111 112 struct mbuf *gem_get(struct gem_softc *, int, int); 113 int gem_eint(struct gem_softc *, u_int); 114 int gem_rint(struct gem_softc *); 115 int gem_tint(struct gem_softc *, u_int32_t); 116 117 #ifdef GEM_DEBUG 118 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \ 119 printf x 120 #else 121 #define DPRINTF(sc, x) /* nothing */ 122 #endif 123 124 125 /* 126 * gem_config: 127 * 128 * Attach a Gem interface to the system. 129 */ 130 void 131 gem_config(sc) 132 struct gem_softc *sc; 133 { 134 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 135 struct mii_data *mii = &sc->sc_mii; 136 struct mii_softc *child; 137 int i, error; 138 struct ifmedia_entry *ifm; 139 140 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); 141 142 /* Make sure the chip is stopped. */ 143 ifp->if_softc = sc; 144 gem_reset(sc); 145 146 /* 147 * Allocate the control data structures, and create and load the 148 * DMA map for it. 149 */ 150 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 151 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 152 1, &sc->sc_cdnseg, 0)) != 0) { 153 printf("\n%s: unable to allocate control data, error = %d\n", 154 sc->sc_dev.dv_xname, error); 155 goto fail_0; 156 } 157 158 /* XXX should map this in with correct endianness */ 159 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 160 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 161 BUS_DMA_COHERENT)) != 0) { 162 printf("\n%s: unable to map control data, error = %d\n", 163 sc->sc_dev.dv_xname, error); 164 goto fail_1; 165 } 166 167 if ((error = bus_dmamap_create(sc->sc_dmatag, 168 sizeof(struct gem_control_data), 1, 169 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 170 printf("\n%s: unable to create control data DMA map, " 171 "error = %d\n", sc->sc_dev.dv_xname, error); 172 goto fail_2; 173 } 174 175 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 176 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 177 0)) != 0) { 178 printf("\n%s: unable to load control data DMA map, error = %d\n", 179 sc->sc_dev.dv_xname, error); 180 goto fail_3; 181 } 182 183 /* 184 * Create the receive buffer DMA maps. 185 */ 186 for (i = 0; i < GEM_NRXDESC; i++) { 187 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 188 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 189 printf("\n%s: unable to create rx DMA map %d, " 190 "error = %d\n", sc->sc_dev.dv_xname, i, error); 191 goto fail_5; 192 } 193 sc->sc_rxsoft[i].rxs_mbuf = NULL; 194 } 195 /* 196 * Create the transmit buffer DMA maps. 197 */ 198 for (i = 0; i < GEM_NTXDESC; i++) { 199 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 200 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 201 &sc->sc_txd[i].sd_map)) != 0) { 202 printf("\n%s: unable to create tx DMA map %d, " 203 "error = %d\n", sc->sc_dev.dv_xname, i, error); 204 goto fail_6; 205 } 206 sc->sc_txd[i].sd_mbuf = NULL; 207 } 208 209 /* 210 * From this point forward, the attachment cannot fail. A failure 211 * before this point releases all resources that may have been 212 * allocated. 213 */ 214 215 /* Announce ourselves. */ 216 printf(", address %s\n", ether_sprintf(sc->sc_enaddr)); 217 218 /* Get RX FIFO size */ 219 sc->sc_rxfifosize = 64 * 220 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 221 222 /* Initialize ifnet structure. */ 223 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname); 224 ifp->if_softc = sc; 225 ifp->if_flags = 226 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 227 ifp->if_start = gem_start; 228 ifp->if_ioctl = gem_ioctl; 229 ifp->if_watchdog = gem_watchdog; 230 IFQ_SET_READY(&ifp->if_snd); 231 232 ifp->if_capabilities = IFCAP_VLAN_MTU; 233 234 /* Initialize ifmedia structures and MII info */ 235 mii->mii_ifp = ifp; 236 mii->mii_readreg = gem_mii_readreg; 237 mii->mii_writereg = gem_mii_writereg; 238 mii->mii_statchg = gem_mii_statchg; 239 240 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 241 242 gem_mifinit(sc); 243 244 if (sc->sc_tcvr == -1) 245 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 246 MII_OFFSET_ANY, 0); 247 else 248 mii_attach(&sc->sc_dev, mii, 0xffffffff, sc->sc_tcvr, 249 MII_OFFSET_ANY, 0); 250 251 child = LIST_FIRST(&mii->mii_phys); 252 if (child == NULL) { 253 /* No PHY attached */ 254 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 255 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 256 } else { 257 /* 258 * Walk along the list of attached MII devices and 259 * establish an `MII instance' to `phy number' 260 * mapping. We'll use this mapping in media change 261 * requests to determine which phy to use to program 262 * the MIF configuration register. 263 */ 264 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 265 /* 266 * Note: we support just two PHYs: the built-in 267 * internal device and an external on the MII 268 * connector. 269 */ 270 if (child->mii_phy > 1 || child->mii_inst > 1) { 271 printf("%s: cannot accommodate MII device %s" 272 " at phy %d, instance %d\n", 273 sc->sc_dev.dv_xname, 274 child->mii_dev.dv_xname, 275 child->mii_phy, child->mii_inst); 276 continue; 277 } 278 279 sc->sc_phys[child->mii_inst] = child->mii_phy; 280 } 281 282 /* 283 * Now select and activate the PHY we will use. 284 * 285 * The order of preference is External (MDI1), 286 * Internal (MDI0), Serial Link (no MII). 287 */ 288 if (sc->sc_phys[1]) { 289 #ifdef GEM_DEBUG 290 printf("using external phy\n"); 291 #endif 292 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 293 } else { 294 #ifdef GEM_DEBUG 295 printf("using internal phy\n"); 296 #endif 297 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 298 } 299 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 300 sc->sc_mif_config); 301 302 /* 303 * XXX - we can really do the following ONLY if the 304 * phy indeed has the auto negotiation capability!! 305 */ 306 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 307 } 308 309 /* 310 * If we support GigE media, we support jumbo frames too. 311 * Unless we are Apple. 312 */ 313 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 314 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 315 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 316 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 317 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 318 #if 0 319 if (sc->sc_variant != GEM_APPLE_GMAC) 320 sc->sc_ethercom.ec_capabilities 321 |= ETHERCAP_JUMBO_MTU; 322 #endif 323 324 sc->sc_flags |= GEM_GIGABIT; 325 break; 326 } 327 } 328 329 /* Attach the interface. */ 330 if_attach(ifp); 331 ether_ifattach(ifp); 332 333 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 334 if (sc->sc_sh == NULL) 335 panic("gem_config: can't establish shutdownhook"); 336 337 timeout_set(&sc->sc_tick_ch, gem_tick, sc); 338 return; 339 340 /* 341 * Free any resources we've allocated during the failed attach 342 * attempt. Do this in reverse order and fall through. 343 */ 344 fail_6: 345 for (i = 0; i < GEM_NTXDESC; i++) { 346 if (sc->sc_txd[i].sd_map != NULL) 347 bus_dmamap_destroy(sc->sc_dmatag, 348 sc->sc_txd[i].sd_map); 349 } 350 fail_5: 351 for (i = 0; i < GEM_NRXDESC; i++) { 352 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 353 bus_dmamap_destroy(sc->sc_dmatag, 354 sc->sc_rxsoft[i].rxs_dmamap); 355 } 356 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 357 fail_3: 358 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 359 fail_2: 360 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 361 sizeof(struct gem_control_data)); 362 fail_1: 363 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 364 fail_0: 365 return; 366 } 367 368 369 void 370 gem_tick(arg) 371 void *arg; 372 { 373 struct gem_softc *sc = arg; 374 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 375 bus_space_tag_t t = sc->sc_bustag; 376 bus_space_handle_t mac = sc->sc_h; 377 int s; 378 379 /* unload collisions counters */ 380 ifp->if_collisions += 381 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 382 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 383 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 384 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 385 386 /* clear the hardware counters */ 387 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 388 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 389 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 390 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 391 392 s = splimp(); 393 mii_tick(&sc->sc_mii); 394 splx(s); 395 396 timeout_add(&sc->sc_tick_ch, hz); 397 } 398 399 int 400 gem_bitwait(sc, r, clr, set) 401 struct gem_softc *sc; 402 int r; 403 u_int32_t clr; 404 u_int32_t set; 405 { 406 int i; 407 u_int32_t reg; 408 409 for (i = TRIES; i--; DELAY(100)) { 410 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 411 if ((r & clr) == 0 && (r & set) == set) 412 return (1); 413 } 414 415 return (0); 416 } 417 418 void 419 gem_reset(sc) 420 struct gem_softc *sc; 421 { 422 bus_space_tag_t t = sc->sc_bustag; 423 bus_space_handle_t h = sc->sc_h; 424 int s; 425 426 s = splimp(); 427 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 428 gem_reset_rx(sc); 429 gem_reset_tx(sc); 430 431 /* Do a full reset */ 432 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 433 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 434 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 435 splx(s); 436 } 437 438 439 /* 440 * gem_rxdrain: 441 * 442 * Drain the receive queue. 443 */ 444 void 445 gem_rxdrain(struct gem_softc *sc) 446 { 447 struct gem_rxsoft *rxs; 448 int i; 449 450 for (i = 0; i < GEM_NRXDESC; i++) { 451 rxs = &sc->sc_rxsoft[i]; 452 if (rxs->rxs_mbuf != NULL) { 453 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 454 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 455 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 456 m_freem(rxs->rxs_mbuf); 457 rxs->rxs_mbuf = NULL; 458 } 459 } 460 } 461 462 /* 463 * Reset the whole thing. 464 */ 465 void 466 gem_stop(struct ifnet *ifp, int disable) 467 { 468 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 469 struct gem_sxd *sd; 470 u_int32_t i; 471 472 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 473 474 timeout_del(&sc->sc_tick_ch); 475 476 /* 477 * Mark the interface down and cancel the watchdog timer. 478 */ 479 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 480 ifp->if_timer = 0; 481 482 mii_down(&sc->sc_mii); 483 484 gem_reset_rx(sc); 485 gem_reset_tx(sc); 486 487 /* 488 * Release any queued transmit buffers. 489 */ 490 for (i = 0; i < GEM_NTXDESC; i++) { 491 sd = &sc->sc_txd[i]; 492 if (sd->sd_mbuf != NULL) { 493 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 494 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 495 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 496 m_freem(sd->sd_mbuf); 497 sd->sd_mbuf = NULL; 498 } 499 } 500 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0; 501 502 if (disable) 503 gem_rxdrain(sc); 504 } 505 506 507 /* 508 * Reset the receiver 509 */ 510 int 511 gem_reset_rx(struct gem_softc *sc) 512 { 513 bus_space_tag_t t = sc->sc_bustag; 514 bus_space_handle_t h = sc->sc_h; 515 516 /* 517 * Resetting while DMA is in progress can cause a bus hang, so we 518 * disable DMA first. 519 */ 520 gem_disable_rx(sc); 521 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 522 /* Wait till it finishes */ 523 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) 524 printf("%s: cannot disable rx dma\n", sc->sc_dev.dv_xname); 525 /* Wait 5ms extra. */ 526 delay(5000); 527 528 /* Finally, reset the ERX */ 529 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 530 /* Wait till it finishes */ 531 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 532 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 533 return (1); 534 } 535 return (0); 536 } 537 538 539 /* 540 * Reset the transmitter 541 */ 542 int 543 gem_reset_tx(struct gem_softc *sc) 544 { 545 bus_space_tag_t t = sc->sc_bustag; 546 bus_space_handle_t h = sc->sc_h; 547 548 /* 549 * Resetting while DMA is in progress can cause a bus hang, so we 550 * disable DMA first. 551 */ 552 gem_disable_tx(sc); 553 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 554 /* Wait till it finishes */ 555 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 556 printf("%s: cannot disable tx dma\n", sc->sc_dev.dv_xname); 557 /* Wait 5ms extra. */ 558 delay(5000); 559 560 /* Finally, reset the ETX */ 561 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 562 /* Wait till it finishes */ 563 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 564 printf("%s: cannot reset transmitter\n", 565 sc->sc_dev.dv_xname); 566 return (1); 567 } 568 return (0); 569 } 570 571 /* 572 * disable receiver. 573 */ 574 int 575 gem_disable_rx(struct gem_softc *sc) 576 { 577 bus_space_tag_t t = sc->sc_bustag; 578 bus_space_handle_t h = sc->sc_h; 579 u_int32_t cfg; 580 581 /* Flip the enable bit */ 582 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 583 cfg &= ~GEM_MAC_RX_ENABLE; 584 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 585 586 /* Wait for it to finish */ 587 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 588 } 589 590 /* 591 * disable transmitter. 592 */ 593 int 594 gem_disable_tx(struct gem_softc *sc) 595 { 596 bus_space_tag_t t = sc->sc_bustag; 597 bus_space_handle_t h = sc->sc_h; 598 u_int32_t cfg; 599 600 /* Flip the enable bit */ 601 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 602 cfg &= ~GEM_MAC_TX_ENABLE; 603 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 604 605 /* Wait for it to finish */ 606 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 607 } 608 609 /* 610 * Initialize interface. 611 */ 612 int 613 gem_meminit(struct gem_softc *sc) 614 { 615 struct gem_rxsoft *rxs; 616 int i, error; 617 618 /* 619 * Initialize the transmit descriptor ring. 620 */ 621 for (i = 0; i < GEM_NTXDESC; i++) { 622 sc->sc_txdescs[i].gd_flags = 0; 623 sc->sc_txdescs[i].gd_addr = 0; 624 } 625 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 627 628 /* 629 * Initialize the receive descriptor and receive job 630 * descriptor rings. 631 */ 632 for (i = 0; i < GEM_NRXDESC; i++) { 633 rxs = &sc->sc_rxsoft[i]; 634 if (rxs->rxs_mbuf == NULL) { 635 if ((error = gem_add_rxbuf(sc, i)) != 0) { 636 printf("%s: unable to allocate or map rx " 637 "buffer %d, error = %d\n", 638 sc->sc_dev.dv_xname, i, error); 639 /* 640 * XXX Should attempt to run with fewer receive 641 * XXX buffers instead of just failing. 642 */ 643 gem_rxdrain(sc); 644 return (1); 645 } 646 } else 647 GEM_INIT_RXDESC(sc, i); 648 } 649 sc->sc_rxptr = 0; 650 651 return (0); 652 } 653 654 int 655 gem_ringsize(int sz) 656 { 657 switch (sz) { 658 case 32: 659 return GEM_RING_SZ_32; 660 case 64: 661 return GEM_RING_SZ_64; 662 case 128: 663 return GEM_RING_SZ_128; 664 case 256: 665 return GEM_RING_SZ_256; 666 case 512: 667 return GEM_RING_SZ_512; 668 case 1024: 669 return GEM_RING_SZ_1024; 670 case 2048: 671 return GEM_RING_SZ_2048; 672 case 4096: 673 return GEM_RING_SZ_4096; 674 case 8192: 675 return GEM_RING_SZ_8192; 676 default: 677 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 678 return GEM_RING_SZ_32; 679 } 680 } 681 682 /* 683 * Initialization of interface; set up initialization block 684 * and transmit/receive descriptor rings. 685 */ 686 int 687 gem_init(struct ifnet *ifp) 688 { 689 690 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 691 bus_space_tag_t t = sc->sc_bustag; 692 bus_space_handle_t h = sc->sc_h; 693 int s; 694 u_int max_frame_size; 695 u_int32_t v; 696 697 s = splimp(); 698 699 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 700 /* 701 * Initialization sequence. The numbered steps below correspond 702 * to the sequence outlined in section 6.3.5.1 in the Ethernet 703 * Channel Engine manual (part of the PCIO manual). 704 * See also the STP2002-STQ document from Sun Microsystems. 705 */ 706 707 /* step 1 & 2. Reset the Ethernet Channel */ 708 gem_stop(ifp, 0); 709 gem_reset(sc); 710 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 711 712 /* Re-initialize the MIF */ 713 gem_mifinit(sc); 714 715 /* Call MI reset function if any */ 716 if (sc->sc_hwreset) 717 (*sc->sc_hwreset)(sc); 718 719 /* step 3. Setup data structures in host memory */ 720 gem_meminit(sc); 721 722 /* step 4. TX MAC registers & counters */ 723 bcopy(sc->sc_arpcom.ac_enaddr, sc->sc_enaddr, ETHER_ADDR_LEN); 724 gem_init_regs(sc); 725 max_frame_size = ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN; 726 v = (max_frame_size) | (0x2000 << 16) /* Burst size */; 727 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 728 729 /* step 5. RX MAC registers & counters */ 730 gem_setladrf(sc); 731 732 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 733 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 734 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); 735 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 736 737 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 738 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); 739 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 740 741 /* step 8. Global Configuration & Interrupt Mask */ 742 bus_space_write_4(t, h, GEM_INTMASK, 743 ~(GEM_INTR_TX_INTME| 744 GEM_INTR_TX_EMPTY| 745 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 746 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 747 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 748 GEM_INTR_BERR)); 749 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 750 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 751 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 752 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 753 754 /* step 9. ETX Configuration: use mostly default values */ 755 756 /* Enable DMA */ 757 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 758 bus_space_write_4(t, h, GEM_TX_CONFIG, 759 v|GEM_TX_CONFIG_TXDMA_EN| 760 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 761 bus_space_write_4(t, h, GEM_TX_KICK, 0); 762 763 /* step 10. ERX Configuration */ 764 765 /* Encode Receive Descriptor ring size: four possible values */ 766 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 767 768 /* Enable DMA */ 769 bus_space_write_4(t, h, GEM_RX_CONFIG, 770 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 771 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 772 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 773 /* 774 * The following value is for an OFF Threshold of about 3/4 full 775 * and an ON Threshold of 1/4 full. 776 */ 777 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 778 (3 * sc->sc_rxfifosize / 256) | 779 ( (sc->sc_rxfifosize / 256) << 12)); 780 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 781 782 /* step 11. Configure Media */ 783 mii_mediachg(&sc->sc_mii); 784 785 /* step 12. RX_MAC Configuration Register */ 786 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 787 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 788 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 789 790 /* step 14. Issue Transmit Pending command */ 791 792 /* Call MI initialization function if any */ 793 if (sc->sc_hwinit) 794 (*sc->sc_hwinit)(sc); 795 796 797 /* step 15. Give the receiver a swift kick */ 798 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 799 800 /* Start the one second timer. */ 801 timeout_add(&sc->sc_tick_ch, hz); 802 803 ifp->if_flags |= IFF_RUNNING; 804 ifp->if_flags &= ~IFF_OACTIVE; 805 ifp->if_timer = 0; 806 splx(s); 807 808 return (0); 809 } 810 811 void 812 gem_init_regs(struct gem_softc *sc) 813 { 814 bus_space_tag_t t = sc->sc_bustag; 815 bus_space_handle_t h = sc->sc_h; 816 u_int32_t v; 817 818 /* These regs are not cleared on reset */ 819 sc->sc_inited = 0; 820 if (!sc->sc_inited) { 821 822 /* Wooo. Magic values. */ 823 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 824 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 825 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 826 827 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 828 /* Max frame and max burst size */ 829 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */; 830 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v); 831 832 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 833 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 834 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 835 /* Dunno.... */ 836 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 837 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 838 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 839 840 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 841 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 842 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 843 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 844 /* MAC control addr set to 0:1:c2:0:1:80 */ 845 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 846 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 847 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 848 849 /* MAC filter addr set to 0:0:0:0:0:0 */ 850 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 851 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 852 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 853 854 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 855 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 856 857 sc->sc_inited = 1; 858 } 859 860 /* Counters need to be zeroed */ 861 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 862 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 863 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 864 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 865 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 866 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 867 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 868 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 869 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 870 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 871 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 872 873 /* Un-pause stuff */ 874 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 875 876 /* 877 * Set the station address. 878 */ 879 bus_space_write_4(t, h, GEM_MAC_ADDR0, 880 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 881 bus_space_write_4(t, h, GEM_MAC_ADDR1, 882 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 883 bus_space_write_4(t, h, GEM_MAC_ADDR2, 884 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 885 886 887 /* 888 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 889 */ 890 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 891 v = GEM_MAC_XIF_TX_MII_ENA; 892 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 893 v |= GEM_MAC_XIF_FDPLX_LED; 894 if (sc->sc_flags & GEM_GIGABIT) 895 v |= GEM_MAC_XIF_GMII_MODE; 896 } 897 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 898 } 899 900 /* 901 * Receive interrupt. 902 */ 903 int 904 gem_rint(sc) 905 struct gem_softc *sc; 906 { 907 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 908 bus_space_tag_t t = sc->sc_bustag; 909 bus_space_handle_t h = sc->sc_h; 910 struct ether_header *eh; 911 struct gem_rxsoft *rxs; 912 struct mbuf *m; 913 u_int64_t rxstat; 914 int i, len; 915 916 for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) { 917 rxs = &sc->sc_rxsoft[i]; 918 919 GEM_CDRXSYNC(sc, i, 920 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 921 922 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 923 924 if (rxstat & GEM_RD_OWN) { 925 /* 926 * We have processed all of the receive buffers. 927 */ 928 break; 929 } 930 931 if (rxstat & GEM_RD_BAD_CRC) { 932 printf("%s: receive error: CRC error\n", 933 sc->sc_dev.dv_xname); 934 GEM_INIT_RXDESC(sc, i); 935 continue; 936 } 937 938 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 939 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 940 #ifdef GEM_DEBUG 941 if (ifp->if_flags & IFF_DEBUG) { 942 printf(" rxsoft %p descriptor %d: ", rxs, i); 943 printf("gd_flags: 0x%016llx\t", (long long) 944 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 945 printf("gd_addr: 0x%016llx\n", (long long) 946 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 947 } 948 #endif 949 950 /* No errors; receive the packet. */ 951 len = GEM_RD_BUFLEN(rxstat); 952 953 /* 954 * Allocate a new mbuf cluster. If that fails, we are 955 * out of memory, and must drop the packet and recycle 956 * the buffer that's already attached to this descriptor. 957 */ 958 m = rxs->rxs_mbuf; 959 if (gem_add_rxbuf(sc, i) != 0) { 960 ifp->if_ierrors++; 961 GEM_INIT_RXDESC(sc, i); 962 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 963 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 964 continue; 965 } 966 m->m_data += 2; /* We're already off by two */ 967 968 ifp->if_ipackets++; 969 eh = mtod(m, struct ether_header *); 970 m->m_pkthdr.rcvif = ifp; 971 m->m_pkthdr.len = m->m_len = len; 972 973 #if NBPFILTER > 0 974 /* 975 * Pass this up to any BPF listeners, but only 976 * pass it up the stack if its for us. 977 */ 978 if (ifp->if_bpf) 979 bpf_mtap(ifp->if_bpf, m); 980 #endif /* NPBFILTER > 0 */ 981 982 /* Pass it on. */ 983 ether_input_mbuf(ifp, m); 984 } 985 986 /* Update the receive pointer. */ 987 sc->sc_rxptr = i; 988 bus_space_write_4(t, h, GEM_RX_KICK, i); 989 990 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 991 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 992 993 return (1); 994 } 995 996 997 /* 998 * gem_add_rxbuf: 999 * 1000 * Add a receive buffer to the indicated descriptor. 1001 */ 1002 int 1003 gem_add_rxbuf(struct gem_softc *sc, int idx) 1004 { 1005 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1006 struct mbuf *m; 1007 int error; 1008 1009 MGETHDR(m, M_DONTWAIT, MT_DATA); 1010 if (m == NULL) 1011 return (ENOBUFS); 1012 1013 MCLGET(m, M_DONTWAIT); 1014 if ((m->m_flags & M_EXT) == 0) { 1015 m_freem(m); 1016 return (ENOBUFS); 1017 } 1018 1019 #ifdef GEM_DEBUG 1020 /* bzero the packet to check dma */ 1021 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1022 #endif 1023 1024 if (rxs->rxs_mbuf != NULL) 1025 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1026 1027 rxs->rxs_mbuf = m; 1028 1029 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1030 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1031 BUS_DMA_READ|BUS_DMA_NOWAIT); 1032 if (error) { 1033 printf("%s: can't load rx DMA map %d, error = %d\n", 1034 sc->sc_dev.dv_xname, idx, error); 1035 panic("gem_add_rxbuf"); /* XXX */ 1036 } 1037 1038 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1039 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1040 1041 GEM_INIT_RXDESC(sc, idx); 1042 1043 return (0); 1044 } 1045 1046 1047 int 1048 gem_eint(sc, status) 1049 struct gem_softc *sc; 1050 u_int status; 1051 { 1052 if ((status & GEM_INTR_MIF) != 0) { 1053 printf("%s: link status changed\n", sc->sc_dev.dv_xname); 1054 return (1); 1055 } 1056 1057 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS); 1058 return (1); 1059 } 1060 1061 1062 int 1063 gem_intr(v) 1064 void *v; 1065 { 1066 struct gem_softc *sc = (struct gem_softc *)v; 1067 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1068 bus_space_tag_t t = sc->sc_bustag; 1069 bus_space_handle_t seb = sc->sc_h; 1070 u_int32_t status; 1071 int r = 0; 1072 1073 status = bus_space_read_4(t, seb, GEM_STATUS); 1074 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n", 1075 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS)); 1076 1077 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1078 r |= gem_eint(sc, status); 1079 1080 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1081 r |= gem_tint(sc, status); 1082 1083 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1084 r |= gem_rint(sc); 1085 1086 /* We should eventually do more than just print out error stats. */ 1087 if (status & GEM_INTR_TX_MAC) { 1088 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1089 #ifdef GEM_DEBUG 1090 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1091 printf("%s: MAC tx fault, status %x\n", 1092 sc->sc_dev.dv_xname, txstat); 1093 #endif 1094 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1095 gem_init(ifp); 1096 } 1097 if (status & GEM_INTR_RX_MAC) { 1098 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1099 #ifdef GEM_DEBUG 1100 if (rxstat & ~GEM_MAC_RX_DONE) 1101 printf("%s: MAC rx fault, status %x\n", 1102 sc->sc_dev.dv_xname, rxstat); 1103 #endif 1104 /* 1105 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1106 * due to a silicon bug so handle them silently. 1107 */ 1108 if (rxstat & GEM_MAC_RX_OVERFLOW) { 1109 ifp->if_ierrors++; 1110 gem_init(ifp); 1111 } 1112 #ifdef GEM_DEBUG 1113 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1114 printf("%s: MAC rx fault, status %x\n", 1115 sc->sc_dev.dv_xname, rxstat); 1116 #endif 1117 } 1118 return (r); 1119 } 1120 1121 1122 void 1123 gem_watchdog(ifp) 1124 struct ifnet *ifp; 1125 { 1126 struct gem_softc *sc = ifp->if_softc; 1127 1128 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1129 "GEM_MAC_RX_CONFIG %x\n", 1130 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1131 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1132 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1133 1134 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1135 ++ifp->if_oerrors; 1136 1137 /* Try to get more packets going. */ 1138 gem_init(ifp); 1139 } 1140 1141 /* 1142 * Initialize the MII Management Interface 1143 */ 1144 void 1145 gem_mifinit(sc) 1146 struct gem_softc *sc; 1147 { 1148 bus_space_tag_t t = sc->sc_bustag; 1149 bus_space_handle_t mif = sc->sc_h; 1150 1151 if (GEM_IS_APPLE(sc)) { 1152 if (sc->sc_variant == GEM_APPLE_K2_GMAC) 1153 sc->sc_tcvr = 1; 1154 else 1155 sc->sc_tcvr = 0; 1156 } else { 1157 sc->sc_tcvr = -1; 1158 } 1159 1160 /* Configure the MIF in frame mode */ 1161 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1162 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1163 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1164 } 1165 1166 /* 1167 * MII interface 1168 * 1169 * The GEM MII interface supports at least three different operating modes: 1170 * 1171 * Bitbang mode is implemented using data, clock and output enable registers. 1172 * 1173 * Frame mode is implemented by loading a complete frame into the frame 1174 * register and polling the valid bit for completion. 1175 * 1176 * Polling mode uses the frame register but completion is indicated by 1177 * an interrupt. 1178 * 1179 */ 1180 int 1181 gem_mii_readreg(self, phy, reg) 1182 struct device *self; 1183 int phy, reg; 1184 { 1185 struct gem_softc *sc = (void *)self; 1186 bus_space_tag_t t = sc->sc_bustag; 1187 bus_space_handle_t mif = sc->sc_h; 1188 int n; 1189 u_int32_t v; 1190 1191 #ifdef GEM_DEBUG 1192 if (sc->sc_debug) 1193 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1194 #endif 1195 1196 /* Construct the frame command */ 1197 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1198 GEM_MIF_FRAME_READ; 1199 1200 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1201 for (n = 0; n < 100; n++) { 1202 DELAY(1); 1203 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1204 if (v & GEM_MIF_FRAME_TA0) 1205 return (v & GEM_MIF_FRAME_DATA); 1206 } 1207 1208 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1209 return (0); 1210 } 1211 1212 void 1213 gem_mii_writereg(self, phy, reg, val) 1214 struct device *self; 1215 int phy, reg, val; 1216 { 1217 struct gem_softc *sc = (void *)self; 1218 bus_space_tag_t t = sc->sc_bustag; 1219 bus_space_handle_t mif = sc->sc_h; 1220 int n; 1221 u_int32_t v; 1222 1223 #ifdef GEM_DEBUG 1224 if (sc->sc_debug) 1225 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1226 phy, reg, val); 1227 #endif 1228 1229 #if 0 1230 /* Select the desired PHY in the MIF configuration register */ 1231 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1232 /* Clear PHY select bit */ 1233 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1234 if (phy == GEM_PHYAD_EXTERNAL) 1235 /* Set PHY select bit to get at external device */ 1236 v |= GEM_MIF_CONFIG_PHY_SEL; 1237 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1238 #endif 1239 /* Construct the frame command */ 1240 v = GEM_MIF_FRAME_WRITE | 1241 (phy << GEM_MIF_PHY_SHIFT) | 1242 (reg << GEM_MIF_REG_SHIFT) | 1243 (val & GEM_MIF_FRAME_DATA); 1244 1245 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1246 for (n = 0; n < 100; n++) { 1247 DELAY(1); 1248 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1249 if (v & GEM_MIF_FRAME_TA0) 1250 return; 1251 } 1252 1253 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1254 } 1255 1256 void 1257 gem_mii_statchg(dev) 1258 struct device *dev; 1259 { 1260 struct gem_softc *sc = (void *)dev; 1261 #ifdef GEM_DEBUG 1262 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1263 #endif 1264 bus_space_tag_t t = sc->sc_bustag; 1265 bus_space_handle_t mac = sc->sc_h; 1266 u_int32_t v; 1267 1268 #ifdef GEM_DEBUG 1269 if (sc->sc_debug) 1270 printf("gem_mii_statchg: status change: phy = %d\n", 1271 sc->sc_phys[instance]); 1272 #endif 1273 1274 1275 /* Set tx full duplex options */ 1276 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1277 delay(10000); /* reg must be cleared and delay before changing. */ 1278 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1279 GEM_MAC_TX_ENABLE; 1280 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1281 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1282 } 1283 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1284 1285 /* XIF Configuration */ 1286 /* We should really calculate all this rather than rely on defaults */ 1287 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1288 v = GEM_MAC_XIF_LINK_LED; 1289 v |= GEM_MAC_XIF_TX_MII_ENA; 1290 /* If an external transceiver is connected, enable its MII drivers */ 1291 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1292 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1293 /* External MII needs echo disable if half duplex. */ 1294 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1295 /* turn on full duplex LED */ 1296 v |= GEM_MAC_XIF_FDPLX_LED; 1297 else 1298 /* half duplex -- disable echo */ 1299 v |= GEM_MAC_XIF_ECHO_DISABL; 1300 1301 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 1302 case IFM_1000_T: /* Gigabit using GMII interface */ 1303 v |= GEM_MAC_XIF_GMII_MODE; 1304 break; 1305 default: 1306 v &= ~GEM_MAC_XIF_GMII_MODE; 1307 } 1308 } else 1309 /* Internal MII needs buf enable */ 1310 v |= GEM_MAC_XIF_MII_BUF_ENA; 1311 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1312 } 1313 1314 int 1315 gem_mediachange(ifp) 1316 struct ifnet *ifp; 1317 { 1318 struct gem_softc *sc = ifp->if_softc; 1319 struct mii_data *mii = &sc->sc_mii; 1320 1321 if (mii->mii_instance) { 1322 struct mii_softc *miisc; 1323 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1324 miisc = LIST_NEXT(miisc, mii_list)) 1325 mii_phy_reset(miisc); 1326 } 1327 1328 return (mii_mediachg(&sc->sc_mii)); 1329 } 1330 1331 void 1332 gem_mediastatus(ifp, ifmr) 1333 struct ifnet *ifp; 1334 struct ifmediareq *ifmr; 1335 { 1336 struct gem_softc *sc = ifp->if_softc; 1337 1338 mii_pollstat(&sc->sc_mii); 1339 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1340 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1341 } 1342 1343 /* 1344 * Process an ioctl request. 1345 */ 1346 int 1347 gem_ioctl(ifp, cmd, data) 1348 struct ifnet *ifp; 1349 u_long cmd; 1350 caddr_t data; 1351 { 1352 struct gem_softc *sc = ifp->if_softc; 1353 struct ifaddr *ifa = (struct ifaddr *)data; 1354 struct ifreq *ifr = (struct ifreq *)data; 1355 int s, error = 0; 1356 1357 s = splimp(); 1358 1359 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) { 1360 splx(s); 1361 return (error); 1362 } 1363 1364 switch (cmd) { 1365 1366 case SIOCSIFADDR: 1367 ifp->if_flags |= IFF_UP; 1368 1369 switch (ifa->ifa_addr->sa_family) { 1370 #ifdef INET 1371 case AF_INET: 1372 gem_init(ifp); 1373 arp_ifinit(&sc->sc_arpcom, ifa); 1374 break; 1375 #endif 1376 default: 1377 gem_init(ifp); 1378 break; 1379 } 1380 break; 1381 1382 case SIOCSIFFLAGS: 1383 if ((ifp->if_flags & IFF_UP) == 0 && 1384 (ifp->if_flags & IFF_RUNNING) != 0) { 1385 /* 1386 * If interface is marked down and it is running, then 1387 * stop it. 1388 */ 1389 gem_stop(ifp, 1); 1390 ifp->if_flags &= ~IFF_RUNNING; 1391 } else if ((ifp->if_flags & IFF_UP) != 0 && 1392 (ifp->if_flags & IFF_RUNNING) == 0) { 1393 /* 1394 * If interface is marked up and it is stopped, then 1395 * start it. 1396 */ 1397 gem_init(ifp); 1398 } else if ((ifp->if_flags & IFF_UP) != 0) { 1399 /* 1400 * Reset the interface to pick up changes in any other 1401 * flags that affect hardware registers. 1402 */ 1403 /*gem_stop(sc);*/ 1404 gem_init(ifp); 1405 } 1406 #ifdef GEM_DEBUG 1407 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0; 1408 #endif 1409 break; 1410 1411 case SIOCADDMULTI: 1412 case SIOCDELMULTI: 1413 error = (cmd == SIOCADDMULTI) ? 1414 ether_addmulti(ifr, &sc->sc_arpcom) : 1415 ether_delmulti(ifr, &sc->sc_arpcom); 1416 1417 if (error == ENETRESET) { 1418 /* 1419 * Multicast list has changed; set the hardware filter 1420 * accordingly. 1421 */ 1422 if (ifp->if_flags & IFF_RUNNING) 1423 gem_init(ifp); 1424 error = 0; 1425 } 1426 break; 1427 1428 case SIOCGIFMEDIA: 1429 case SIOCSIFMEDIA: 1430 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1431 break; 1432 1433 default: 1434 error = EINVAL; 1435 break; 1436 } 1437 1438 splx(s); 1439 return (error); 1440 } 1441 1442 1443 void 1444 gem_shutdown(arg) 1445 void *arg; 1446 { 1447 struct gem_softc *sc = (struct gem_softc *)arg; 1448 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1449 1450 gem_stop(ifp, 1); 1451 } 1452 1453 /* 1454 * Set up the logical address filter. 1455 */ 1456 void 1457 gem_setladrf(sc) 1458 struct gem_softc *sc; 1459 { 1460 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1461 struct ether_multi *enm; 1462 struct ether_multistep step; 1463 struct arpcom *ac = &sc->sc_arpcom; 1464 bus_space_tag_t t = sc->sc_bustag; 1465 bus_space_handle_t h = sc->sc_h; 1466 u_int32_t crc, hash[16], v; 1467 int i; 1468 1469 /* Get current RX configuration */ 1470 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1471 1472 1473 /* 1474 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1475 * and hash filter. Depending on the case, the right bit will be 1476 * enabled. 1477 */ 1478 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1479 GEM_MAC_RX_PROMISC_GRP); 1480 1481 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1482 /* Turn on promiscuous mode */ 1483 v |= GEM_MAC_RX_PROMISCUOUS; 1484 ifp->if_flags |= IFF_ALLMULTI; 1485 goto chipit; 1486 } 1487 1488 /* 1489 * Set up multicast address filter by passing all multicast addresses 1490 * through a crc generator, and then using the high order 8 bits as an 1491 * index into the 256 bit logical address filter. The high order 4 1492 * bits selects the word, while the other 4 bits select the bit within 1493 * the word (where bit 0 is the MSB). 1494 */ 1495 1496 /* Clear hash table */ 1497 for (i = 0; i < 16; i++) 1498 hash[i] = 0; 1499 1500 1501 ETHER_FIRST_MULTI(step, ac, enm); 1502 while (enm != NULL) { 1503 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1504 /* 1505 * We must listen to a range of multicast addresses. 1506 * For now, just accept all multicasts, rather than 1507 * trying to set only those filter bits needed to match 1508 * the range. (At this time, the only use of address 1509 * ranges is for IP multicast routing, for which the 1510 * range is big enough to require all bits set.) 1511 * XXX use the addr filter for this 1512 */ 1513 ifp->if_flags |= IFF_ALLMULTI; 1514 v |= GEM_MAC_RX_PROMISC_GRP; 1515 goto chipit; 1516 } 1517 1518 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1519 1520 /* Just want the 8 most significant bits. */ 1521 crc >>= 24; 1522 1523 /* Set the corresponding bit in the filter. */ 1524 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1525 1526 ETHER_NEXT_MULTI(step, enm); 1527 } 1528 1529 v |= GEM_MAC_RX_HASH_FILTER; 1530 ifp->if_flags &= ~IFF_ALLMULTI; 1531 1532 /* Now load the hash table into the chip (if we are using it) */ 1533 for (i = 0; i < 16; i++) { 1534 bus_space_write_4(t, h, 1535 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1536 hash[i]); 1537 } 1538 1539 chipit: 1540 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1541 } 1542 1543 int 1544 gem_encap(sc, mhead, bixp) 1545 struct gem_softc *sc; 1546 struct mbuf *mhead; 1547 u_int32_t *bixp; 1548 { 1549 u_int64_t flags; 1550 u_int32_t cur, frag, i; 1551 bus_dmamap_t map; 1552 1553 cur = frag = *bixp; 1554 map = sc->sc_txd[cur].sd_map; 1555 1556 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead, 1557 BUS_DMA_NOWAIT) != 0) { 1558 return (ENOBUFS); 1559 } 1560 1561 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) { 1562 bus_dmamap_unload(sc->sc_dmatag, map); 1563 return (ENOBUFS); 1564 } 1565 1566 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize, 1567 BUS_DMASYNC_PREWRITE); 1568 1569 for (i = 0; i < map->dm_nsegs; i++) { 1570 sc->sc_txdescs[frag].gd_addr = 1571 GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr); 1572 flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) | 1573 (i == 0 ? GEM_TD_START_OF_PACKET : 0) | 1574 ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0); 1575 sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags); 1576 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap, 1577 GEM_CDTXOFF(frag), sizeof(struct gem_desc), 1578 BUS_DMASYNC_PREWRITE); 1579 cur = frag; 1580 if (++frag == GEM_NTXDESC) 1581 frag = 0; 1582 } 1583 1584 sc->sc_tx_cnt += map->dm_nsegs; 1585 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map; 1586 sc->sc_txd[cur].sd_map = map; 1587 sc->sc_txd[cur].sd_mbuf = mhead; 1588 1589 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, frag); 1590 1591 *bixp = frag; 1592 1593 /* sync descriptors */ 1594 1595 return (0); 1596 } 1597 1598 /* 1599 * Transmit interrupt. 1600 */ 1601 int 1602 gem_tint(sc, status) 1603 struct gem_softc *sc; 1604 u_int32_t status; 1605 { 1606 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1607 struct gem_sxd *sd; 1608 u_int32_t cons, hwcons; 1609 1610 hwcons = status >> 19; 1611 cons = sc->sc_tx_cons; 1612 while (cons != hwcons) { 1613 sd = &sc->sc_txd[cons]; 1614 if (sd->sd_mbuf != NULL) { 1615 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0, 1616 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1617 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map); 1618 m_freem(sd->sd_mbuf); 1619 sd->sd_mbuf = NULL; 1620 } 1621 sc->sc_tx_cnt--; 1622 ifp->if_opackets++; 1623 if (++cons == GEM_NTXDESC) 1624 cons = 0; 1625 } 1626 sc->sc_tx_cons = cons; 1627 1628 gem_start(ifp); 1629 1630 if (sc->sc_tx_cnt == 0) 1631 ifp->if_timer = 0; 1632 1633 return (1); 1634 } 1635 1636 void 1637 gem_start(ifp) 1638 struct ifnet *ifp; 1639 { 1640 struct gem_softc *sc = ifp->if_softc; 1641 struct mbuf *m; 1642 u_int32_t bix; 1643 1644 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1645 return; 1646 1647 bix = sc->sc_tx_prod; 1648 while (sc->sc_txd[bix].sd_mbuf == NULL) { 1649 IFQ_POLL(&ifp->if_snd, m); 1650 if (m == NULL) 1651 break; 1652 1653 #if NBPFILTER > 0 1654 /* 1655 * If BPF is listening on this interface, let it see the 1656 * packet before we commit it to the wire. 1657 */ 1658 if (ifp->if_bpf) 1659 bpf_mtap(ifp->if_bpf, m); 1660 #endif 1661 1662 /* 1663 * Encapsulate this packet and start it going... 1664 * or fail... 1665 */ 1666 if (gem_encap(sc, m, &bix)) { 1667 ifp->if_timer = 2; 1668 break; 1669 } 1670 1671 IFQ_DEQUEUE(&ifp->if_snd, m); 1672 ifp->if_timer = 5; 1673 } 1674 1675 sc->sc_tx_prod = bix; 1676 } 1677