1*a097e4f1Skettenis /* $OpenBSD: dwiicreg.h,v 1.2 2019/08/06 06:56:29 kettenis Exp $ */ 2c6df0db7Sjcs /* 3c6df0db7Sjcs * Synopsys DesignWare I2C controller 4c6df0db7Sjcs * 5c6df0db7Sjcs * Copyright (c) 2015, 2016 joshua stein <jcs@openbsd.org> 6c6df0db7Sjcs * 7c6df0db7Sjcs * Permission to use, copy, modify, and/or distribute this software for any 8c6df0db7Sjcs * purpose with or without fee is hereby granted, provided that the above 9c6df0db7Sjcs * copyright notice and this permission notice appear in all copies. 10c6df0db7Sjcs * 11c6df0db7Sjcs * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12c6df0db7Sjcs * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13c6df0db7Sjcs * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14c6df0db7Sjcs * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15c6df0db7Sjcs * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16c6df0db7Sjcs * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17c6df0db7Sjcs * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18c6df0db7Sjcs */ 19c6df0db7Sjcs 20c6df0db7Sjcs /* register offsets */ 21c6df0db7Sjcs #define DW_IC_CON 0x0 22c6df0db7Sjcs #define DW_IC_TAR 0x4 23c6df0db7Sjcs #define DW_IC_DATA_CMD 0x10 24c6df0db7Sjcs #define DW_IC_SS_SCL_HCNT 0x14 25c6df0db7Sjcs #define DW_IC_SS_SCL_LCNT 0x18 26c6df0db7Sjcs #define DW_IC_FS_SCL_HCNT 0x1c 27c6df0db7Sjcs #define DW_IC_FS_SCL_LCNT 0x20 28c6df0db7Sjcs #define DW_IC_INTR_STAT 0x2c 29c6df0db7Sjcs #define DW_IC_INTR_MASK 0x30 30c6df0db7Sjcs #define DW_IC_RAW_INTR_STAT 0x34 31c6df0db7Sjcs #define DW_IC_RX_TL 0x38 32c6df0db7Sjcs #define DW_IC_TX_TL 0x3c 33c6df0db7Sjcs #define DW_IC_CLR_INTR 0x40 34c6df0db7Sjcs #define DW_IC_CLR_RX_UNDER 0x44 35c6df0db7Sjcs #define DW_IC_CLR_RX_OVER 0x48 36c6df0db7Sjcs #define DW_IC_CLR_TX_OVER 0x4c 37c6df0db7Sjcs #define DW_IC_CLR_RD_REQ 0x50 38c6df0db7Sjcs #define DW_IC_CLR_TX_ABRT 0x54 39c6df0db7Sjcs #define DW_IC_CLR_RX_DONE 0x58 40c6df0db7Sjcs #define DW_IC_CLR_ACTIVITY 0x5c 41c6df0db7Sjcs #define DW_IC_CLR_STOP_DET 0x60 42c6df0db7Sjcs #define DW_IC_CLR_START_DET 0x64 43c6df0db7Sjcs #define DW_IC_CLR_GEN_CALL 0x68 44c6df0db7Sjcs #define DW_IC_ENABLE 0x6c 45c6df0db7Sjcs #define DW_IC_STATUS 0x70 46c6df0db7Sjcs #define DW_IC_TXFLR 0x74 47c6df0db7Sjcs #define DW_IC_RXFLR 0x78 48c6df0db7Sjcs #define DW_IC_SDA_HOLD 0x7c 49c6df0db7Sjcs #define DW_IC_TX_ABRT_SOURCE 0x80 50c6df0db7Sjcs #define DW_IC_ENABLE_STATUS 0x9c 51c6df0db7Sjcs #define DW_IC_COMP_PARAM_1 0xf4 52*a097e4f1Skettenis #define DW_IC_TX_FIFO_DEPTH(x) ((((x) >> 16) & 0xff) + 1) 53*a097e4f1Skettenis #define DW_IC_RX_FIFO_DEPTH(x) ((((x) >> 8) & 0xff) + 1) 54c6df0db7Sjcs #define DW_IC_COMP_VERSION 0xf8 55c6df0db7Sjcs #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A 56c6df0db7Sjcs #define DW_IC_COMP_TYPE 0xfc 57c6df0db7Sjcs #define DW_IC_COMP_TYPE_VALUE 0x44570140 58c6df0db7Sjcs 59c6df0db7Sjcs #define DW_IC_CON_MASTER 0x1 60c6df0db7Sjcs #define DW_IC_CON_SPEED_STD 0x2 61c6df0db7Sjcs #define DW_IC_CON_SPEED_FAST 0x4 62c6df0db7Sjcs #define DW_IC_CON_10BITADDR_MASTER 0x10 63c6df0db7Sjcs #define DW_IC_CON_RESTART_EN 0x20 64c6df0db7Sjcs #define DW_IC_CON_SLAVE_DISABLE 0x40 65c6df0db7Sjcs 66c6df0db7Sjcs #define DW_IC_DATA_CMD_READ 0x100 67c6df0db7Sjcs #define DW_IC_DATA_CMD_STOP 0x200 68c6df0db7Sjcs #define DW_IC_DATA_CMD_RESTART 0x400 69c6df0db7Sjcs 70c6df0db7Sjcs #define DW_IC_INTR_RX_UNDER 0x001 71c6df0db7Sjcs #define DW_IC_INTR_RX_OVER 0x002 72c6df0db7Sjcs #define DW_IC_INTR_RX_FULL 0x004 73c6df0db7Sjcs #define DW_IC_INTR_TX_OVER 0x008 74c6df0db7Sjcs #define DW_IC_INTR_TX_EMPTY 0x010 75c6df0db7Sjcs #define DW_IC_INTR_RD_REQ 0x020 76c6df0db7Sjcs #define DW_IC_INTR_TX_ABRT 0x040 77c6df0db7Sjcs #define DW_IC_INTR_RX_DONE 0x080 78c6df0db7Sjcs #define DW_IC_INTR_ACTIVITY 0x100 79c6df0db7Sjcs #define DW_IC_INTR_STOP_DET 0x200 80c6df0db7Sjcs #define DW_IC_INTR_START_DET 0x400 81c6df0db7Sjcs #define DW_IC_INTR_GEN_CALL 0x800 82c6df0db7Sjcs 83c6df0db7Sjcs #define DW_IC_STATUS_ACTIVITY 0x1 84c6df0db7Sjcs 85c6df0db7Sjcs /* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register */ 86c6df0db7Sjcs #define ABRT_7B_ADDR_NOACK 0 87c6df0db7Sjcs #define ABRT_10ADDR1_NOACK 1 88c6df0db7Sjcs #define ABRT_10ADDR2_NOACK 2 89c6df0db7Sjcs #define ABRT_TXDATA_NOACK 3 90c6df0db7Sjcs #define ABRT_GCALL_NOACK 4 91c6df0db7Sjcs #define ABRT_GCALL_READ 5 92c6df0db7Sjcs #define ABRT_SBYTE_ACKDET 7 93c6df0db7Sjcs #define ABRT_SBYTE_NORSTRT 9 94c6df0db7Sjcs #define ABRT_10B_RD_NORSTRT 10 95c6df0db7Sjcs #define ABRT_MASTER_DIS 11 96c6df0db7Sjcs #define ARB_LOST 12 97