1*829ae773Smiod /* $OpenBSD: atxxreg.h,v 1.1 2008/04/15 20:23:54 miod Exp $ */ 2*829ae773Smiod 3*829ae773Smiod /* 4*829ae773Smiod * Copyright (c) 2008 Miodrag Vallat. 5*829ae773Smiod * 6*829ae773Smiod * Permission to use, copy, modify, and distribute this software for any 7*829ae773Smiod * purpose with or without fee is hereby granted, provided that the above 8*829ae773Smiod * copyright notice and this permission notice appear in all copies. 9*829ae773Smiod * 10*829ae773Smiod * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11*829ae773Smiod * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12*829ae773Smiod * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13*829ae773Smiod * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14*829ae773Smiod * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15*829ae773Smiod * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16*829ae773Smiod * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17*829ae773Smiod */ 18*829ae773Smiod 19*829ae773Smiod /* 20*829ae773Smiod * Alliance Promotion AP6422, AT24 and AT3D extended register set definitions. 21*829ae773Smiod * 22*829ae773Smiod * This has been reconstructed from XFree86 ``apm'' driver, whose authors 23*829ae773Smiod * apparently do not believe in meaningful constants for numbers. See 24*829ae773Smiod * apm_regs.h for more madness. 25*829ae773Smiod */ 26*829ae773Smiod 27*829ae773Smiod /* 28*829ae773Smiod * Dual coordinates encoding 29*829ae773Smiod */ 30*829ae773Smiod 31*829ae773Smiod #define ATR_DUAL(y,x) (((y) << 16) | (x)) 32*829ae773Smiod 33*829ae773Smiod /* 34*829ae773Smiod * Clipping Control 35*829ae773Smiod */ 36*829ae773Smiod 37*829ae773Smiod #define ATR_CLIP_CONTROL 0x0030 /* byte access */ 38*829ae773Smiod #define ATR_CLIP_LEFT 0x0038 39*829ae773Smiod #define ATR_CLIP_TOP 0x003a 40*829ae773Smiod #define ATR_CLIP_LEFTTOP 0x0038 41*829ae773Smiod #define ATR_CLIP_RIGHT 0x003c 42*829ae773Smiod #define ATR_CLIP_BOTTOM 0x003e 43*829ae773Smiod #define ATR_CLIP_RIGHTBOTTOM 0x003c 44*829ae773Smiod 45*829ae773Smiod /* 46*829ae773Smiod * Drawing Engine 47*829ae773Smiod */ 48*829ae773Smiod 49*829ae773Smiod #define ATR_DEC 0x0040 50*829ae773Smiod #define ATR_ROP 0x0046 51*829ae773Smiod #define ATR_BYTEMASK 0x0047 52*829ae773Smiod #define ATR_PATTERN1 0x0048 53*829ae773Smiod #define ATR_PATTERN2 0x004c 54*829ae773Smiod #define ATR_SRC_X 0x0050 55*829ae773Smiod #define ATR_SRC_Y 0x0052 56*829ae773Smiod #define ATR_SRC_XY 0x0050 57*829ae773Smiod #define ATR_DST_X 0x0054 58*829ae773Smiod #define ATR_DST_Y 0x0056 59*829ae773Smiod #define ATR_DST_XY 0x0054 60*829ae773Smiod #define ATR_W 0x0058 61*829ae773Smiod #define ATR_H 0x005a 62*829ae773Smiod #define ATR_WH 0x0058 63*829ae773Smiod #define ATR_OFFSET 0x005c 64*829ae773Smiod #define ATR_SRC_OFFSET 0x005e 65*829ae773Smiod #define ATR_FG 0x0060 66*829ae773Smiod #define ATR_BG 0x0064 67*829ae773Smiod 68*829ae773Smiod /* DEC layout */ 69*829ae773Smiod #define DEC_COMMAND_MASK 0x0000003f 70*829ae773Smiod #define DEC_COMMAND_SHIFT 0 71*829ae773Smiod #define DEC_DIR_X_REVERSE 0x00000040 72*829ae773Smiod #define DEC_DIR_Y_REVERSE 0x00000080 73*829ae773Smiod #define DEC_DIR_Y_MAJOR 0x00000100 74*829ae773Smiod #define DEC_SRC_LINEAR 0x00000200 75*829ae773Smiod #define DEC_SRC_CONTIGUOUS 0x00000800 76*829ae773Smiod #define DEC_MONOCHROME 0x00001000 77*829ae773Smiod #define DEC_SRC_TRANSPARENT 0x00002000 78*829ae773Smiod #define DEC_DEPTH_MASK 0x0001c000 79*829ae773Smiod #define DEC_DEPTH_SHIFT 14 80*829ae773Smiod #define DEC_DST_LINEAR 0x00040000 81*829ae773Smiod #define DEC_DST_CONTIGUOUS 0x00080000 82*829ae773Smiod #define DEC_DST_TRANSPARENT 0x00100000 83*829ae773Smiod #define DEC_DST_TRANSPARENT_POLARITY 0x00200000 84*829ae773Smiod #define DEC_PATTERN_MASK 0x00c00000 85*829ae773Smiod #define DEC_PATTERN_SHIFT 22 86*829ae773Smiod #define DEC_WIDTH_MASK 0x07000000 87*829ae773Smiod #define DEC_WIDTH_SHIFT 24 88*829ae773Smiod #define DEC_UPDATE_MASK 0x18000000 89*829ae773Smiod #define DEC_UPDATE_SHIFT 27 90*829ae773Smiod #define DEC_START_MASK 0x60000000 91*829ae773Smiod #define DEC_START_SHIFT 29 92*829ae773Smiod #define DEC_START 0x80000000 93*829ae773Smiod 94*829ae773Smiod /* DEC commands */ 95*829ae773Smiod #define DEC_COMMAND_NOP 0x00 96*829ae773Smiod #define DEC_COMMAND_BLT 0x01 /* screen to screen blt */ 97*829ae773Smiod #define DEC_COMMAND_RECT 0x02 /* rectangle fill */ 98*829ae773Smiod #define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */ 99*829ae773Smiod #define DEC_COMMAND_STRIP 0x04 /* strip pattern */ 100*829ae773Smiod #define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */ 101*829ae773Smiod #define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */ 102*829ae773Smiod #define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */ 103*829ae773Smiod #define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */ 104*829ae773Smiod 105*829ae773Smiod /* depth */ 106*829ae773Smiod #define DEC_DEPTH_8 0x01 107*829ae773Smiod #define DEC_DEPTH_16 0x02 108*829ae773Smiod #define DEC_DEPTH_32 0x03 109*829ae773Smiod #define DEC_DEPTH_24 0x04 110*829ae773Smiod 111*829ae773Smiod /* width */ 112*829ae773Smiod #define DEC_WIDTH_LINEAR 0x00 113*829ae773Smiod #define DEC_WIDTH_640 0x01 114*829ae773Smiod #define DEC_WIDTH_800 0x02 115*829ae773Smiod #define DEC_WIDTH_1024 0x04 116*829ae773Smiod #define DEC_WIDTH_1152 0x05 117*829ae773Smiod #define DEC_WIDTH_1280 0x06 118*829ae773Smiod #define DEC_WIDTH_1600 0x07 119*829ae773Smiod 120*829ae773Smiod /* update mode */ 121*829ae773Smiod #define DEC_UPDATE_NONE 0x00 122*829ae773Smiod #define DEC_UPDATE_TOP_RIGHT 0x01 123*829ae773Smiod #define DEC_UPDATE_BOTTOM_LEFT 0x02 124*829ae773Smiod #define DEC_UPDATE_LASTPIX 0x03 125*829ae773Smiod 126*829ae773Smiod /* quickstart mode - operation starts as soon as given register is written to */ 127*829ae773Smiod #define DEC_START_DIMX 0x01 128*829ae773Smiod #define DEC_START_SRC 0x02 129*829ae773Smiod #define DEC_START_DST 0x03 130*829ae773Smiod 131*829ae773Smiod /* ROP */ 132*829ae773Smiod #define ROP_DST 0x66 133*829ae773Smiod #define ROP_SRC 0xcc 134*829ae773Smiod #define ROP_PATTERN 0xf0 135*829ae773Smiod 136*829ae773Smiod /* 137*829ae773Smiod * Configuration Registers 138*829ae773Smiod */ 139*829ae773Smiod 140*829ae773Smiod #define ATR_PIXEL 0x0080 /* byte access */ 141*829ae773Smiod #define PIXEL_DEPTH_MASK 0x0f 142*829ae773Smiod #define PIXEL_DEPTH_SHIFT 0 143*829ae773Smiod 144*829ae773Smiod /* pixel depth */ 145*829ae773Smiod #define PIXEL_4 0x01 146*829ae773Smiod #define PIXEL_8 0x02 147*829ae773Smiod #define PIXEL_15 0x0c 148*829ae773Smiod #define PIXEL_16 0x0d 149*829ae773Smiod #define PIXEL_24 0x0e 150*829ae773Smiod #define PIXEL_32 0x0f 151*829ae773Smiod 152*829ae773Smiod #define ATR_APERTURE 0x00c0 /* short access */ 153*829ae773Smiod 154*829ae773Smiod /* 155*829ae773Smiod * DPMS Control 156*829ae773Smiod */ 157*829ae773Smiod 158*829ae773Smiod #define ATR_DPMS 0x00d0 /* byte access */ 159*829ae773Smiod 160*829ae773Smiod #define DPMS_HSYNC_DISABLE 0x01 161*829ae773Smiod #define DPMS_VSYNC_DISABLE 0x02 162*829ae773Smiod 163*829ae773Smiod /* 164*829ae773Smiod * RAMDAC 165*829ae773Smiod */ 166*829ae773Smiod 167*829ae773Smiod #define ATR_COLOR_CORRECTION 0x00e0 168*829ae773Smiod #define ATR_MCLK 0x00e8 169*829ae773Smiod #define ATR_PCLK 0x00ec 170*829ae773Smiod 171*829ae773Smiod /* 172*829ae773Smiod * Hardware Cursor 173*829ae773Smiod * 174*829ae773Smiod * The position can not become negative; the offset register, encoded as 175*829ae773Smiod * (signed y delta << 8) | signed x delta, allow the cursor image to 176*829ae773Smiod * cross the upper-left corner. 177*829ae773Smiod */ 178*829ae773Smiod 179*829ae773Smiod #define ATR_CURSOR_ENABLE 0x0140 180*829ae773Smiod #define ATR_CURSOR_FG 0x0141 /* 3:3:2 */ 181*829ae773Smiod #define ATR_CURSOR_BG 0x0142 /* 3:3:2 */ 182*829ae773Smiod #define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */ 183*829ae773Smiod #define ATR_CURSOR_POSITION 0x0148 184*829ae773Smiod #define ATR_CURSOR_OFFSET 0x014c /* short access */ 185*829ae773Smiod 186*829ae773Smiod /* 187*829ae773Smiod * Identification Register 188*829ae773Smiod */ 189*829ae773Smiod 190*829ae773Smiod #define ATR_ID 0x0182 191*829ae773Smiod 192*829ae773Smiod #define ID_AP6422 0x6422 193*829ae773Smiod #define ID_AT24 0x6424 194*829ae773Smiod #define ID_AT3D 0x643d 195*829ae773Smiod 196*829ae773Smiod /* 197*829ae773Smiod * Status Registers 198*829ae773Smiod */ 199*829ae773Smiod 200*829ae773Smiod #define ATR_FIFO_STATUS 0x01fc 201*829ae773Smiod #define ATR_BLT_STATUS 0x01fd 202*829ae773Smiod 203*829ae773Smiod #define FIFO_MASK 0x0f 204*829ae773Smiod #define FIFO_SHIFT 0 205*829ae773Smiod #define FIFO_AP6422 4 206*829ae773Smiod #define FIFO_AT24 8 207*829ae773Smiod 208*829ae773Smiod #define BLT_HOST_BUSY 0x01 209*829ae773Smiod #define BLT_ENGINE_BUSY 0x04 210