1*ea5b165aSreyk /* $OpenBSD: ar5211reg.h,v 1.11 2007/03/12 01:04:52 reyk Exp $ */ 2f23d19fdSreyk 3f23d19fdSreyk /* 4*ea5b165aSreyk * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5f23d19fdSreyk * 6f23d19fdSreyk * Permission to use, copy, modify, and distribute this software for any 7f23d19fdSreyk * purpose with or without fee is hereby granted, provided that the above 8f23d19fdSreyk * copyright notice and this permission notice appear in all copies. 9f23d19fdSreyk * 10f23d19fdSreyk * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11f23d19fdSreyk * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12f23d19fdSreyk * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13f23d19fdSreyk * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14f23d19fdSreyk * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15f23d19fdSreyk * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16f23d19fdSreyk * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17f23d19fdSreyk */ 18f23d19fdSreyk 19f23d19fdSreyk /* 20f23d19fdSreyk * Known registers of the Atheros AR5001 Wireless LAN chipsets 21f23d19fdSreyk * (AR5211/AR5311). 22f23d19fdSreyk */ 23f23d19fdSreyk 24f23d19fdSreyk #ifndef _AR5K_AR5211_REG_H 25f23d19fdSreyk #define _AR5K_AR5211_REG_H 26f23d19fdSreyk 27f23d19fdSreyk /* 28f23d19fdSreyk * Command register 29f23d19fdSreyk */ 30f23d19fdSreyk #define AR5K_AR5211_CR 0x0008 31f23d19fdSreyk #define AR5K_AR5211_CR_RXE 0x00000004 32f23d19fdSreyk #define AR5K_AR5211_CR_RXD 0x00000020 33f23d19fdSreyk #define AR5K_AR5211_CR_SWI 0x00000040 34f23d19fdSreyk 35f23d19fdSreyk /* 36f23d19fdSreyk * Receive queue descriptor pointer register 37f23d19fdSreyk */ 38f23d19fdSreyk #define AR5K_AR5211_RXDP 0x000c 39f23d19fdSreyk 40f23d19fdSreyk /* 41f23d19fdSreyk * Configuration and status register 42f23d19fdSreyk */ 43f23d19fdSreyk #define AR5K_AR5211_CFG 0x0014 44f23d19fdSreyk #define AR5K_AR5211_CFG_SWTD 0x00000001 45f23d19fdSreyk #define AR5K_AR5211_CFG_SWTB 0x00000002 46f23d19fdSreyk #define AR5K_AR5211_CFG_SWRD 0x00000004 47f23d19fdSreyk #define AR5K_AR5211_CFG_SWRB 0x00000008 48f23d19fdSreyk #define AR5K_AR5211_CFG_SWRG 0x00000010 49f23d19fdSreyk #define AR5K_AR5211_CFG_ADHOC 0x00000020 50f23d19fdSreyk #define AR5K_AR5211_CFG_PHY_OK 0x00000100 51f23d19fdSreyk #define AR5K_AR5211_CFG_EEBS 0x00000200 52f23d19fdSreyk #define AR5K_AR5211_CFG_CLKGD 0x00000400 53f23d19fdSreyk #define AR5K_AR5211_CFG_PCI_THRES 0x00060000 54f23d19fdSreyk #define AR5K_AR5211_CFG_PCI_THRES_S 17 55f23d19fdSreyk 56f23d19fdSreyk /* 57f23d19fdSreyk * Interrupt enable register 58f23d19fdSreyk */ 59f23d19fdSreyk #define AR5K_AR5211_IER 0x0024 60f23d19fdSreyk #define AR5K_AR5211_IER_DISABLE 0x00000000 61f23d19fdSreyk #define AR5K_AR5211_IER_ENABLE 0x00000001 62f23d19fdSreyk 63f23d19fdSreyk /* 64f23d19fdSreyk * First RTS duration register 65f23d19fdSreyk */ 66f23d19fdSreyk #define AR5K_AR5211_RTSD0 0x0028 67f23d19fdSreyk #define AR5K_AR5211_RTSD0_6 0x000000ff 68f23d19fdSreyk #define AR5K_AR5211_RTSD0_6_S 0 69f23d19fdSreyk #define AR5K_AR5211_RTSD0_9 0x0000ff00 70f23d19fdSreyk #define AR5K_AR5211_RTSD0_9_S 8 71f23d19fdSreyk #define AR5K_AR5211_RTSD0_12 0x00ff0000 72f23d19fdSreyk #define AR5K_AR5211_RTSD0_12_S 16 73f23d19fdSreyk #define AR5K_AR5211_RTSD0_18 0xff000000 74f23d19fdSreyk #define AR5K_AR5211_RTSD0_18_S 24 75f23d19fdSreyk 76f23d19fdSreyk /* 77f23d19fdSreyk * Second RTS duration register 78f23d19fdSreyk */ 79f23d19fdSreyk #define AR5K_AR5211_RTSD1 0x002c 80f23d19fdSreyk #define AR5K_AR5211_RTSD1_24 0x000000ff 81f23d19fdSreyk #define AR5K_AR5211_RTSD1_24_S 0 82f23d19fdSreyk #define AR5K_AR5211_RTSD1_36 0x0000ff00 83f23d19fdSreyk #define AR5K_AR5211_RTSD1_36_S 8 84f23d19fdSreyk #define AR5K_AR5211_RTSD1_48 0x00ff0000 85f23d19fdSreyk #define AR5K_AR5211_RTSD1_48_S 16 86f23d19fdSreyk #define AR5K_AR5211_RTSD1_54 0xff000000 87f23d19fdSreyk #define AR5K_AR5211_RTSD1_54_S 24 88f23d19fdSreyk 89f23d19fdSreyk /* 90f23d19fdSreyk * Transmit configuration register 91f23d19fdSreyk */ 92f23d19fdSreyk #define AR5K_AR5211_TXCFG 0x0030 93f23d19fdSreyk #define AR5K_AR5211_TXCFG_SDMAMR 0x00000007 946eac2691Sreyk #define AR5K_AR5211_TXCFG_SDMAMR_S 0 95f23d19fdSreyk #define AR5K_AR5211_TXCFG_B_MODE 0x00000008 96f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL 0x000003f0 97f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_S 4 98f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_0B 0x00000000 99f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_64B 0x00000010 100f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_128B 0x00000020 101f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_192B 0x00000030 102f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXFULL_256B 0x00000040 103f23d19fdSreyk #define AR5K_AR5211_TXCFG_TXCONT_ENABLE 0x00000080 1046eac2691Sreyk #define AR5K_AR5211_TXCFG_DMASIZE 0x00000100 105f23d19fdSreyk #define AR5K_AR5211_TXCFG_JUMBO_TXE 0x00000400 106f23d19fdSreyk #define AR5K_AR5211_TXCFG_RTSRND 0x00001000 107f23d19fdSreyk #define AR5K_AR5211_TXCFG_FRMPAD_DIS 0x00002000 108f23d19fdSreyk #define AR5K_AR5211_TXCFG_RDY_DIS 0x00004000 109f23d19fdSreyk 110f23d19fdSreyk /* 111f23d19fdSreyk * Receive configuration register 112f23d19fdSreyk */ 113f23d19fdSreyk #define AR5K_AR5211_RXCFG 0x0034 114f23d19fdSreyk #define AR5K_AR5211_RXCFG_SDMAMW 0x00000007 1156eac2691Sreyk #define AR5K_AR5211_RXCFG_SDMAMW_S 0 116f23d19fdSreyk #define AR5K_AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008 117f23d19fdSreyk #define AR5K_AR5211_RXCFG_ZLFDMA 0x00000010 118f23d19fdSreyk #define AR5K_AR5211_RXCFG_JUMBO_RXE 0x00000020 119f23d19fdSreyk #define AR5K_AR5211_RXCFG_JUMBO_WRAP 0x00000040 120f23d19fdSreyk 121f23d19fdSreyk /* 122f23d19fdSreyk * Receive jumbo descriptor last address register 123f23d19fdSreyk */ 124f23d19fdSreyk #define AR5K_AR5211_RXJLA 0x0038 125f23d19fdSreyk 126f23d19fdSreyk /* 127f23d19fdSreyk * MIB control register 128f23d19fdSreyk */ 129f23d19fdSreyk #define AR5K_AR5211_MIBC 0x0040 130f23d19fdSreyk #define AR5K_AR5211_MIBC_COW 0x00000001 131f23d19fdSreyk #define AR5K_AR5211_MIBC_FMC 0x00000002 132f23d19fdSreyk #define AR5K_AR5211_MIBC_CMC 0x00000004 133f23d19fdSreyk #define AR5K_AR5211_MIBC_MCS 0x00000008 134f23d19fdSreyk 135f23d19fdSreyk /* 136f23d19fdSreyk * Timeout prescale register 137f23d19fdSreyk */ 138f23d19fdSreyk #define AR5K_AR5211_TOPS 0x0044 139f23d19fdSreyk #define AR5K_AR5211_TOPS_M 0x0000ffff 140f23d19fdSreyk 141f23d19fdSreyk /* 142f23d19fdSreyk * Receive timeout register (no frame received) 143f23d19fdSreyk */ 144f23d19fdSreyk #define AR5K_AR5211_RXNOFRM 0x0048 145f23d19fdSreyk #define AR5K_AR5211_RXNOFRM_M 0x000003ff 146f23d19fdSreyk 147f23d19fdSreyk /* 148f23d19fdSreyk * Transmit timeout register (no frame sent) 149f23d19fdSreyk */ 150f23d19fdSreyk #define AR5K_AR5211_TXNOFRM 0x004c 151f23d19fdSreyk #define AR5K_AR5211_TXNOFRM_M 0x000003ff 152f23d19fdSreyk #define AR5K_AR5211_TXNOFRM_QCU 0x000ffc00 153f23d19fdSreyk 154f23d19fdSreyk /* 155f23d19fdSreyk * Receive frame gap timeout register 156f23d19fdSreyk */ 157f23d19fdSreyk #define AR5K_AR5211_RPGTO 0x0050 158f23d19fdSreyk #define AR5K_AR5211_RPGTO_M 0x000003ff 159f23d19fdSreyk 160f23d19fdSreyk /* 161f23d19fdSreyk * Receive frame count limit register 162f23d19fdSreyk */ 163f23d19fdSreyk #define AR5K_AR5211_RFCNT 0x0054 164f23d19fdSreyk #define AR5K_AR5211_RFCNT_M 0x0000001f 165f23d19fdSreyk 166f23d19fdSreyk /* 167f23d19fdSreyk * Misc settings register 168f23d19fdSreyk */ 169f23d19fdSreyk #define AR5K_AR5211_MISC 0x0058 170f23d19fdSreyk #define AR5K_AR5211_MISC_DMA_OBS_M 0x000001e0 171f23d19fdSreyk #define AR5K_AR5211_MISC_DMA_OBS_S 5 172f23d19fdSreyk #define AR5K_AR5211_MISC_MISC_OBS_M 0x00000e00 173f23d19fdSreyk #define AR5K_AR5211_MISC_MISC_OBS_S 9 174f23d19fdSreyk #define AR5K_AR5211_MISC_MAC_OBS_LSB_M 0x00007000 175f23d19fdSreyk #define AR5K_AR5211_MISC_MAC_OBS_LSB_S 12 176f23d19fdSreyk #define AR5K_AR5211_MISC_MAC_OBS_MSB_M 0x00038000 177f23d19fdSreyk #define AR5K_AR5211_MISC_MAC_OBS_MSB_S 15 178f23d19fdSreyk 179f23d19fdSreyk /* 180f23d19fdSreyk * QCU/DCU clock gating register 181f23d19fdSreyk */ 182f23d19fdSreyk #define AR5K_AR5311_QCUDCU_CLKGT 183f23d19fdSreyk #define AR5K_AR5311_QCUDCU_CLKGT_QCU 0x0000ffff 184f23d19fdSreyk #define AR5K_AR5311_QCUDCU_CLKGT_DCU 0x07ff0000 185f23d19fdSreyk 186f23d19fdSreyk /* 187f23d19fdSreyk * Primary interrupt status register 188f23d19fdSreyk */ 189f23d19fdSreyk #define AR5K_AR5211_PISR 0x0080 190f23d19fdSreyk #define AR5K_AR5211_PISR_RXOK 0x00000001 191f23d19fdSreyk #define AR5K_AR5211_PISR_RXDESC 0x00000002 192f23d19fdSreyk #define AR5K_AR5211_PISR_RXERR 0x00000004 193f23d19fdSreyk #define AR5K_AR5211_PISR_RXNOFRM 0x00000008 194f23d19fdSreyk #define AR5K_AR5211_PISR_RXEOL 0x00000010 195f23d19fdSreyk #define AR5K_AR5211_PISR_RXORN 0x00000020 196f23d19fdSreyk #define AR5K_AR5211_PISR_TXOK 0x00000040 197f23d19fdSreyk #define AR5K_AR5211_PISR_TXDESC 0x00000080 198f23d19fdSreyk #define AR5K_AR5211_PISR_TXERR 0x00000100 199f23d19fdSreyk #define AR5K_AR5211_PISR_TXNOFRM 0x00000200 200f23d19fdSreyk #define AR5K_AR5211_PISR_TXEOL 0x00000400 201f23d19fdSreyk #define AR5K_AR5211_PISR_TXURN 0x00000800 202f23d19fdSreyk #define AR5K_AR5211_PISR_MIB 0x00001000 203f23d19fdSreyk #define AR5K_AR5211_PISR_SWI 0x00002000 204f23d19fdSreyk #define AR5K_AR5211_PISR_RXPHY 0x00004000 205f23d19fdSreyk #define AR5K_AR5211_PISR_RXKCM 0x00008000 206f23d19fdSreyk #define AR5K_AR5211_PISR_SWBA 0x00010000 207f23d19fdSreyk #define AR5K_AR5211_PISR_BRSSI 0x00020000 208f23d19fdSreyk #define AR5K_AR5211_PISR_BMISS 0x00040000 209f23d19fdSreyk #define AR5K_AR5211_PISR_HIUERR 0x00080000 210f23d19fdSreyk #define AR5K_AR5211_PISR_BNR 0x00100000 211f23d19fdSreyk #define AR5K_AR5211_PISR_TIM 0x00800000 212f23d19fdSreyk #define AR5K_AR5211_PISR_GPIO 0x01000000 213f23d19fdSreyk #define AR5K_AR5211_PISR_QCBRORN 0x02000000 214f23d19fdSreyk #define AR5K_AR5211_PISR_QCBRURN 0x04000000 215f23d19fdSreyk #define AR5K_AR5211_PISR_QTRIG 0x08000000 216f23d19fdSreyk 217f23d19fdSreyk /* 218f23d19fdSreyk * Secondary interrupt status registers (0 - 4) 219f23d19fdSreyk */ 220f23d19fdSreyk #define AR5K_AR5211_SISR0 0x0084 221f23d19fdSreyk #define AR5K_AR5211_SISR0_QCU_TXOK 0x000003ff 222f23d19fdSreyk #define AR5K_AR5211_SISR0_QCU_TXDESC 0x03ff0000 223f23d19fdSreyk 224f23d19fdSreyk #define AR5K_AR5211_SISR1 0x0088 225f23d19fdSreyk #define AR5K_AR5211_SISR1_QCU_TXERR 0x000003ff 226f23d19fdSreyk #define AR5K_AR5211_SISR1_QCU_TXEOL 0x03ff0000 227f23d19fdSreyk 228f23d19fdSreyk #define AR5K_AR5211_SISR2 0x008c 229f23d19fdSreyk #define AR5K_AR5211_SISR2_QCU_TXURN 0x000003ff 230f23d19fdSreyk #define AR5K_AR5211_SISR2_MCABT 0x00100000 231f23d19fdSreyk #define AR5K_AR5211_SISR2_SSERR 0x00200000 232f23d19fdSreyk #define AR5K_AR5211_SISR2_DPERR 0x00400000 233f23d19fdSreyk 234f23d19fdSreyk #define AR5K_AR5211_SISR3 0x0090 235f23d19fdSreyk #define AR5K_AR5211_SISR3_QCBRORN 0x000003ff 236f23d19fdSreyk #define AR5K_AR5211_SISR3_QCBRURN 0x03ff0000 237f23d19fdSreyk 238f23d19fdSreyk #define AR5K_AR5211_SISR4 0x0094 239f23d19fdSreyk #define AR5K_AR5211_SISR4_QTRIG 0x000003ff 240f23d19fdSreyk 241f23d19fdSreyk /* 242f23d19fdSreyk * Shadow read-and-clear interrupt status registers 243f23d19fdSreyk */ 244f23d19fdSreyk #define AR5K_AR5211_RAC_PISR 0x00c0 245f23d19fdSreyk #define AR5K_AR5211_RAC_SISR0 0x00c4 246f23d19fdSreyk #define AR5K_AR5211_RAC_SISR1 0x00c8 247f23d19fdSreyk #define AR5K_AR5211_RAC_SISR2 0x00cc 248f23d19fdSreyk #define AR5K_AR5211_RAC_SISR3 0c00d0 249f23d19fdSreyk #define AR5K_AR5211_RAC_SISR4 0c00d4 250f23d19fdSreyk 251f23d19fdSreyk /* 252f23d19fdSreyk * Primary interrupt mask register 253f23d19fdSreyk */ 254f23d19fdSreyk #define AR5K_AR5211_PIMR 0x00a0 255f23d19fdSreyk #define AR5K_AR5211_PIMR_RXOK 0x00000001 256f23d19fdSreyk #define AR5K_AR5211_PIMR_RXDESC 0x00000002 257f23d19fdSreyk #define AR5K_AR5211_PIMR_RXERR 0x00000004 258f23d19fdSreyk #define AR5K_AR5211_PIMR_RXNOFRM 0x00000008 259f23d19fdSreyk #define AR5K_AR5211_PIMR_RXEOL 0x00000010 260f23d19fdSreyk #define AR5K_AR5211_PIMR_RXORN 0x00000020 261f23d19fdSreyk #define AR5K_AR5211_PIMR_TXOK 0x00000040 262f23d19fdSreyk #define AR5K_AR5211_PIMR_TXDESC 0x00000080 263f23d19fdSreyk #define AR5K_AR5211_PIMR_TXERR 0x00000100 264f23d19fdSreyk #define AR5K_AR5211_PIMR_TXNOFRM 0x00000200 265f23d19fdSreyk #define AR5K_AR5211_PIMR_TXEOL 0x00000400 266f23d19fdSreyk #define AR5K_AR5211_PIMR_TXURN 0x00000800 267f23d19fdSreyk #define AR5K_AR5211_PIMR_MIB 0x00001000 268f23d19fdSreyk #define AR5K_AR5211_PIMR_SWI 0x00002000 269f23d19fdSreyk #define AR5K_AR5211_PIMR_RXPHY 0x00004000 270f23d19fdSreyk #define AR5K_AR5211_PIMR_RXKCM 0x00008000 271f23d19fdSreyk #define AR5K_AR5211_PIMR_SWBA 0x00010000 272f23d19fdSreyk #define AR5K_AR5211_PIMR_BRSSI 0x00020000 273f23d19fdSreyk #define AR5K_AR5211_PIMR_BMISS 0x00040000 274f23d19fdSreyk #define AR5K_AR5211_PIMR_HIUERR 0x00080000 275f23d19fdSreyk #define AR5K_AR5211_PIMR_BNR 0x00100000 276f23d19fdSreyk #define AR5K_AR5211_PIMR_TIM 0x00800000 277f23d19fdSreyk #define AR5K_AR5211_PIMR_GPIO 0x01000000 278f23d19fdSreyk #define AR5K_AR5211_PIMR_QCBRORN 0x02000000 279f23d19fdSreyk #define AR5K_AR5211_PIMR_QCBRURN 0x04000000 280f23d19fdSreyk #define AR5K_AR5211_PIMR_QTRIG 0x08000000 281f23d19fdSreyk 282f23d19fdSreyk /* 283f23d19fdSreyk * Secondary interrupt mask registers (0 - 4) 284f23d19fdSreyk */ 285f23d19fdSreyk #define AR5K_AR5211_SIMR0 0x00a4 286f23d19fdSreyk #define AR5K_AR5211_SIMR0_QCU_TXOK 0x000003ff 287f23d19fdSreyk #define AR5K_AR5211_SIMR0_QCU_TXOK_S 0 288f23d19fdSreyk #define AR5K_AR5211_SIMR0_QCU_TXDESC 0x03ff0000 289f23d19fdSreyk #define AR5K_AR5211_SIMR0_QCU_TXDESC_S 16 290f23d19fdSreyk 291f23d19fdSreyk #define AR5K_AR5211_SIMR1 0x00a8 292f23d19fdSreyk #define AR5K_AR5211_SIMR1_QCU_TXERR 0x000003ff 293f23d19fdSreyk #define AR5K_AR5211_SIMR1_QCU_TXERR_S 0 294f23d19fdSreyk #define AR5K_AR5211_SIMR1_QCU_TXEOL 0x03ff0000 295f23d19fdSreyk #define AR5K_AR5211_SIMR1_QCU_TXEOL_S 16 296f23d19fdSreyk 297f23d19fdSreyk #define AR5K_AR5211_SIMR2 0x00ac 298f23d19fdSreyk #define AR5K_AR5211_SIMR2_QCU_TXURN 0x000003ff 299f23d19fdSreyk #define AR5K_AR5211_SIMR2_QCU_TXURN_S 0 300f23d19fdSreyk #define AR5K_AR5211_SIMR2_MCABT 0x00100000 301f23d19fdSreyk #define AR5K_AR5211_SIMR2_SSERR 0x00200000 302f23d19fdSreyk #define AR5K_AR5211_SIMR2_DPERR 0x00400000 303f23d19fdSreyk 304f23d19fdSreyk #define AR5K_AR5211_SIMR3 0x00b0 305f23d19fdSreyk #define AR5K_AR5211_SIMR3_QCBRORN 0x000003ff 306f23d19fdSreyk #define AR5K_AR5211_SIMR3_QCBRORN_S 0 307f23d19fdSreyk #define AR5K_AR5211_SIMR3_QCBRURN 0x03ff0000 308f23d19fdSreyk #define AR5K_AR5211_SIMR3_QCBRURN_S 16 309f23d19fdSreyk 310f23d19fdSreyk #define AR5K_AR5211_SIMR4 0x00b4 311f23d19fdSreyk #define AR5K_AR5211_SIMR4_QTRIG 0x000003ff 312f23d19fdSreyk #define AR5K_AR5211_SIMR4_QTRIG_S 0 313f23d19fdSreyk 314f23d19fdSreyk /* 315f23d19fdSreyk * Queue control unit (QCU) registers (0 - 9) 316f23d19fdSreyk */ 317f23d19fdSreyk #define AR5K_AR5211_QCU(_n, _a) (((_n) << 2) + _a) 318f23d19fdSreyk 319f23d19fdSreyk /* 320f23d19fdSreyk * QCU Transmit descriptor pointer registers 321f23d19fdSreyk */ 322f23d19fdSreyk #define AR5K_AR5211_QCU_TXDP(_n) AR5K_AR5211_QCU(_n, 0x0800) 323f23d19fdSreyk 324f23d19fdSreyk /* 325f23d19fdSreyk * QCU Transmit enable register 326f23d19fdSreyk */ 327f23d19fdSreyk #define AR5K_AR5211_QCU_TXE 0x0840 328f23d19fdSreyk 329f23d19fdSreyk /* 330f23d19fdSreyk * QCU Transmit disable register 331f23d19fdSreyk */ 332f23d19fdSreyk #define AR5K_AR5211_QCU_TXD 0x0880 333f23d19fdSreyk 334f23d19fdSreyk /* 335f23d19fdSreyk * QCU CBR configuration registers 336f23d19fdSreyk */ 337f23d19fdSreyk #define AR5K_AR5211_QCU_CBRCFG(_n) AR5K_AR5211_QCU(_n, 0x08c0) 338f23d19fdSreyk #define AR5K_AR5211_QCU_CBRCFG_INTVAL 0x00ffffff 339f23d19fdSreyk #define AR5K_AR5211_QCU_CBRCFG_INTVAL_S 0 340f23d19fdSreyk #define AR5K_AR5211_QCU_CBRCFG_ORN_THRES 0xff000000 341f23d19fdSreyk #define AR5K_AR5211_QCU_CBRCFG_ORN_THRES_S 24 342f23d19fdSreyk 343f23d19fdSreyk /* 344f23d19fdSreyk * QCU Ready time configuration registers 345f23d19fdSreyk */ 346f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMECFG(_n) AR5K_AR5211_QCU(_n, 0x0900) 347f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL 0x00ffffff 348f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL_S 0 349f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMECFG_DURATION 0x00ffffff 350f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMECFG_ENABLE 0x01000000 351f23d19fdSreyk 352f23d19fdSreyk /* 353f23d19fdSreyk * QCU one shot arm set registers 354f23d19fdSreyk */ 355f23d19fdSreyk #define AR5K_AR5211_QCU_ONESHOTARMS(_n) AR5K_AR5211_QCU(_n, 0x0940) 356f23d19fdSreyk #define AR5K_AR5211_QCU_ONESHOTARMS_M 0x0000ffff 357f23d19fdSreyk 358f23d19fdSreyk /* 359f23d19fdSreyk * QCU one shot arm clear registers 360f23d19fdSreyk */ 361f23d19fdSreyk #define AR5K_AR5211_QCU_ONESHOTARMC(_n) AR5K_AR5211_QCU(_n, 0x0980) 362f23d19fdSreyk #define AR5K_AR5211_QCU_ONESHOTARMC_M 0x0000ffff 363f23d19fdSreyk 364f23d19fdSreyk /* 365f23d19fdSreyk * QCU misc registers 366f23d19fdSreyk */ 367f23d19fdSreyk #define AR5K_AR5211_QCU_MISC(_n) AR5K_AR5211_QCU(_n, 0x09c0) 368f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_M 0x0000000f 369f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_ASAP 0 370f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_CBR 1 371f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT 2 372f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_TIM_GT 3 373f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_FRSHED_BCN_SENT_GT 4 374f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_ONESHOT_ENABLE 0x00000010 375f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_CBREXP 0x00000020 376f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_CBREXP_BCN 0x00000040 377f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_BCN_ENABLE 0x00000080 378f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE 0x00000100 379f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_TXE 0x00000200 380f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_CBR 0x00000400 381f23d19fdSreyk #define AR5K_AR5211_QCU_MISC_DCU_EARLY 0x00000800 382f23d19fdSreyk 383f23d19fdSreyk /* 384f23d19fdSreyk * QCU status registers 385f23d19fdSreyk */ 386f23d19fdSreyk #define AR5K_AR5211_QCU_STS(_n) AR5K_AR5211_QCU(_n, 0x0a00) 387f23d19fdSreyk #define AR5K_AR5211_QCU_STS_FRMPENDCNT 0x00000003 388f23d19fdSreyk #define AR5K_AR5211_QCU_STS_CBREXPCNT 0x0000ff00 389f23d19fdSreyk 390f23d19fdSreyk /* 391f23d19fdSreyk * QCU ready time shutdown register 392f23d19fdSreyk */ 393f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMESHDN 0x0a40 394f23d19fdSreyk #define AR5K_AR5211_QCU_RDYTIMESHDN_M 0x000003ff 395f23d19fdSreyk 396f23d19fdSreyk /* 397f23d19fdSreyk * DCF control unit (DCU) registers (0 - 9) 398f23d19fdSreyk */ 399f23d19fdSreyk #define AR5K_AR5211_DCU(_n, _a) AR5K_AR5211_QCU(_n, _a) 400f23d19fdSreyk 401f23d19fdSreyk /* 402f23d19fdSreyk * DCU QCU mask registers 403f23d19fdSreyk */ 404f23d19fdSreyk #define AR5K_AR5211_DCU_QCUMASK(_n) AR5K_AR5211_DCU(_n, 0x1000) 405f23d19fdSreyk #define AR5K_AR5211_DCU_QCUMASK_M 0x000003ff 406f23d19fdSreyk 407f23d19fdSreyk /* 408f23d19fdSreyk * DCU local IFS settings register 409f23d19fdSreyk */ 410f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS(_n) AR5K_AR5211_DCU(_n, 0x1040) 411f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_CW_MIN 0x000003ff 412f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_CW_MIN_S 0 413f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_CW_MAX 0x000ffc00 414f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_CW_MAX_S 10 415f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_AIFS 0x0ff00000 416f23d19fdSreyk #define AR5K_AR5211_DCU_LCL_IFS_AIFS_S 20 417f23d19fdSreyk 418f23d19fdSreyk /* 419f23d19fdSreyk * DCU retry limit registers 420f23d19fdSreyk */ 421f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT(_n) AR5K_AR5211_DCU(_n, 0x1080) 422f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY 0x0000000f 423f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY_S 0 424f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY 0x000000f0 425f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY_S 4 426f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 427f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY_S 8 428f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 429f23d19fdSreyk #define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY_S 14 430f23d19fdSreyk 431f23d19fdSreyk /* 432f23d19fdSreyk * DCU channel time registers 433f23d19fdSreyk */ 434f23d19fdSreyk #define AR5K_AR5211_DCU_CHAN_TIME(_n) AR5K_AR5211_DCU(_n, 0x10c0) 435f23d19fdSreyk #define AR5K_AR5211_DCU_CHAN_TIME_ENABLE 0x00100000 436f23d19fdSreyk #define AR5K_AR5211_DCU_CHAN_TIME_DUR 0x000fffff 437f23d19fdSreyk #define AR5K_AR5211_DCU_CHAN_TIME_DUR_S 0 438f23d19fdSreyk 439f23d19fdSreyk /* 440f23d19fdSreyk * DCU misc registers 441f23d19fdSreyk */ 442f23d19fdSreyk #define AR5K_AR5211_DCU_MISC(_n) AR5K_AR5211_DCU(_n, 0x1100) 443f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_BACKOFF 0x000007ff 444f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_BACKOFF_FRAG 0x00000200 445f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_HCFPOLL_ENABLE 0x00000800 446f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_BACKOFF_PERSIST 0x00001000 447f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 448f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_VIRTCOL 0x0000c000 449f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_VIRTCOL_NORMAL 0 450f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_VIRTCOL_MODIFIED 1 451f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_VIRTCOL_IGNORE 2 452f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_BCN_ENABLE 0x00010000 453f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL 0x00060000 454f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_S 17 455f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_NONE 0 456f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_INTFRM 1 457f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 458f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_ARBLOCK_IGNORE 0x00080000 459f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 460f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 461f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_VIRT_COLL_POLICY 0x00400000 462f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 463f23d19fdSreyk #define AR5K_AR5211_DCU_MISC_SEQNUM_CTL 0x01000000 464f23d19fdSreyk 465f23d19fdSreyk /* 466f23d19fdSreyk * DCU frame sequence number registers 467f23d19fdSreyk */ 468f23d19fdSreyk #define AR5K_AR5211_DCU_SEQNUM(_n) AR5K_AR5211_DCU(_n, 0x1140) 469f23d19fdSreyk #define AR5K_AR5211_DCU_SEQNUM_M 0x00000fff 470f23d19fdSreyk /* 471f23d19fdSreyk * DCU global IFS SIFS registers 472f23d19fdSreyk */ 473f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_SIFS 0x1030 474f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_SIFS_M 0x0000ffff 475f23d19fdSreyk 476f23d19fdSreyk /* 477f23d19fdSreyk * DCU global IFS slot interval registers 478f23d19fdSreyk */ 479f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_SLOT 0x1070 480f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_SLOT_M 0x0000ffff 481f23d19fdSreyk 482f23d19fdSreyk /* 483f23d19fdSreyk * DCU global IFS EIFS registers 484f23d19fdSreyk */ 485f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_EIFS 0x10b0 486f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_EIFS_M 0x0000ffff 487f23d19fdSreyk 488f23d19fdSreyk /* 489f23d19fdSreyk * DCU global IFS misc registers 490f23d19fdSreyk */ 491f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC 0x10f0 492f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 493f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 494f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 495f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 496f23d19fdSreyk #define AR5K_AR5211_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 497f23d19fdSreyk 498f23d19fdSreyk /* 499f23d19fdSreyk * DCU frame prefetch control register 500f23d19fdSreyk */ 501f23d19fdSreyk #define AR5K_AR5211_DCU_FP 0x1230 502f23d19fdSreyk 503f23d19fdSreyk /* 504f23d19fdSreyk * DCU transmit pause control/status register 505f23d19fdSreyk */ 506f23d19fdSreyk #define AR5K_AR5211_DCU_TXP 0x1270 507f23d19fdSreyk #define AR5K_AR5211_DCU_TXP_M 0x000003ff 508f23d19fdSreyk #define AR5K_AR5211_DCU_TXP_STATUS 0x00010000 509f23d19fdSreyk 510f23d19fdSreyk /* 511f23d19fdSreyk * DCU transmit filter register 512f23d19fdSreyk */ 513f23d19fdSreyk #define AR5K_AR5211_DCU_TX_FILTER 0x1038 514f23d19fdSreyk 515f23d19fdSreyk /* 516f23d19fdSreyk * DCU clear transmit filter register 517f23d19fdSreyk */ 518f23d19fdSreyk #define AR5K_AR5211_DCU_TX_FILTER_CLR 0x143c 519f23d19fdSreyk 520f23d19fdSreyk /* 521f23d19fdSreyk * DCU set transmit filter register 522f23d19fdSreyk */ 523f23d19fdSreyk #define AR5K_AR5211_DCU_TX_FILTER_SET 0x147c 524f23d19fdSreyk 525f23d19fdSreyk /* 526f23d19fdSreyk * DMA size definitions 527f23d19fdSreyk */ 528f23d19fdSreyk typedef enum { 529f23d19fdSreyk AR5K_AR5211_DMASIZE_4B = 0, 5306eac2691Sreyk AR5K_AR5211_DMASIZE_8B = 1, 5316eac2691Sreyk AR5K_AR5211_DMASIZE_16B = 2, 5326eac2691Sreyk AR5K_AR5211_DMASIZE_32B = 3, 5336eac2691Sreyk AR5K_AR5211_DMASIZE_64B = 4, 5346eac2691Sreyk AR5K_AR5211_DMASIZE_128B = 5, 5356eac2691Sreyk AR5K_AR5211_DMASIZE_256B = 6, 5366eac2691Sreyk AR5K_AR5211_DMASIZE_512B = 7 537f23d19fdSreyk } ar5k_ar5211_dmasize_t; 538f23d19fdSreyk 539f23d19fdSreyk /* 540f23d19fdSreyk * Reset control register 541f23d19fdSreyk */ 542f23d19fdSreyk #define AR5K_AR5211_RC 0x4000 543f23d19fdSreyk #define AR5K_AR5211_RC_PCU 0x00000001 544f23d19fdSreyk #define AR5K_AR5211_RC_BB 0x00000002 545f23d19fdSreyk #define AR5K_AR5211_RC_PCI 0x00000010 546f23d19fdSreyk #define AR5K_AR5211_RC_CHIP ( \ 547f23d19fdSreyk AR5K_AR5211_RC_PCU | AR5K_AR5211_RC_BB | AR5K_AR5211_RC_PCI \ 548f23d19fdSreyk ) 549f23d19fdSreyk 550f23d19fdSreyk /* 551f23d19fdSreyk * Sleep control register 552f23d19fdSreyk */ 553f23d19fdSreyk #define AR5K_AR5211_SCR 0x4004 554f23d19fdSreyk #define AR5K_AR5211_SCR_SLDUR 0x0000ffff 555c6d5838dSreyk #define AR5K_AR5211_SCR_SLDUR_S 0 556f23d19fdSreyk #define AR5K_AR5211_SCR_SLE 0x00030000 557f23d19fdSreyk #define AR5K_AR5211_SCR_SLE_S 16 558f23d19fdSreyk #define AR5K_AR5211_SCR_SLE_WAKE 0x00000000 559f23d19fdSreyk #define AR5K_AR5211_SCR_SLE_SLP 0x00010000 560f23d19fdSreyk #define AR5K_AR5211_SCR_SLE_ALLOW 0x00020000 561f23d19fdSreyk #define AR5K_AR5211_SCR_SLE_UNITS 0x00000008 562f23d19fdSreyk 563f23d19fdSreyk /* 564f23d19fdSreyk * Interrupt pending register 565f23d19fdSreyk */ 566f23d19fdSreyk #define AR5K_AR5211_INTPEND 0x4008 567f23d19fdSreyk #define AR5K_AR5211_INTPEND_M 0x00000001 568f23d19fdSreyk 569f23d19fdSreyk /* 570f23d19fdSreyk * Sleep force register 571f23d19fdSreyk */ 572f23d19fdSreyk #define AR5K_AR5211_SFR 0x400c 573f23d19fdSreyk #define AR5K_AR5211_SFR_M 0x00000001 574f23d19fdSreyk 575f23d19fdSreyk /* 576f23d19fdSreyk * PCI configuration register 577f23d19fdSreyk */ 578f23d19fdSreyk #define AR5K_AR5211_PCICFG 0x4010 579f23d19fdSreyk #define AR5K_AR5211_PCICFG_CLKRUNEN 0x00000004 580f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE 0x00000018 581f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE_S 3 582f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE_4K 0 583f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE_8K 1 584f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE_16K 2 585f23d19fdSreyk #define AR5K_AR5211_PCICFG_EESIZE_FAIL 3 586f23d19fdSreyk #define AR5K_AR5211_PCICFG_LED 0x00000060 587f23d19fdSreyk #define AR5K_AR5211_PCICFG_LED_NONE 0x00000000 588f23d19fdSreyk #define AR5K_AR5211_PCICFG_LED_PEND 0x00000020 589f23d19fdSreyk #define AR5K_AR5211_PCICFG_LED_ASSOC 0x00000040 590f23d19fdSreyk #define AR5K_AR5211_PCICFG_BUS_SEL 0x00000380 591f23d19fdSreyk #define AR5K_AR5211_PCICFG_CBEFIX_DIS 0x00000400 592f23d19fdSreyk #define AR5K_AR5211_PCICFG_SL_INTEN 0x00000800 593f23d19fdSreyk #define AR5K_AR5211_PCICFG_SL_INPEN 0x00002800 594f23d19fdSreyk #define AR5K_AR5211_PCICFG_SPWR_DN 0x00010000 595f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDMODE 0x000e0000 596f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDMODE_PROP 0x00000000 597f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDMODE_PROM 0x00020000 598f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDMODE_PWR 0x00040000 599f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDMODE_RAND 0x00060000 600f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDBLINK 0x00700000 601f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDBLINK_S 20 602f23d19fdSreyk #define AR5K_AR5211_PCICFG_LEDSLOW 0x00800000 603e9147aabSreyk #define AR5K_AR5211_PCICFG_LEDSTATE \ 604e9147aabSreyk (AR5K_AR5211_PCICFG_LED | AR5K_AR5211_PCICFG_LEDMODE | \ 605e9147aabSreyk AR5K_AR5211_PCICFG_LEDBLINK | AR5K_AR5211_PCICFG_LEDSLOW) 606f23d19fdSreyk 607f23d19fdSreyk /* 608f23d19fdSreyk * "General Purpose Input/Output" (GPIO) control register 609f23d19fdSreyk */ 610f23d19fdSreyk #define AR5K_AR5211_GPIOCR 0x4014 611f23d19fdSreyk #define AR5K_AR5211_GPIOCR_INT_ENA 0x00008000 612f23d19fdSreyk #define AR5K_AR5211_GPIOCR_INT_SELL 0x00000000 613f23d19fdSreyk #define AR5K_AR5211_GPIOCR_INT_SELH 0x00010000 614f23d19fdSreyk #define AR5K_AR5211_GPIOCR_NONE(n) (0 << ((n) * 2)) 615f23d19fdSreyk #define AR5K_AR5211_GPIOCR_OUT0(n) (1 << ((n) * 2)) 616f23d19fdSreyk #define AR5K_AR5211_GPIOCR_OUT1(n) (2 << ((n) * 2)) 617f23d19fdSreyk #define AR5K_AR5211_GPIOCR_ALL(n) (3 << ((n) * 2)) 618f23d19fdSreyk #define AR5K_AR5211_GPIOCR_INT_SEL(n) ((n) << 12) 619f23d19fdSreyk 620f23d19fdSreyk #define AR5K_AR5211_NUM_GPIO 6 621f23d19fdSreyk 622f23d19fdSreyk /* 623f23d19fdSreyk * "General Purpose Input/Output" (GPIO) data output register 624f23d19fdSreyk */ 625f23d19fdSreyk #define AR5K_AR5211_GPIODO 0x4018 626f23d19fdSreyk 627f23d19fdSreyk /* 628f23d19fdSreyk * "General Purpose Input/Output" (GPIO) data input register 629f23d19fdSreyk */ 630f23d19fdSreyk #define AR5K_AR5211_GPIODI 0x401c 631f23d19fdSreyk #define AR5K_AR5211_GPIODI_M 0x0000002f 632f23d19fdSreyk 633f23d19fdSreyk /* 634f23d19fdSreyk * Silicon revision register 635f23d19fdSreyk */ 636f23d19fdSreyk #define AR5K_AR5211_SREV 0x4020 6375fb5cb47Sreyk #define AR5K_AR5211_SREV_REV 0x0000000f 6385fb5cb47Sreyk #define AR5K_AR5211_SREV_REV_S 0 6395fb5cb47Sreyk #define AR5K_AR5211_SREV_VER 0x000000ff 6405fb5cb47Sreyk #define AR5K_AR5211_SREV_VER_S 4 641f23d19fdSreyk 642f23d19fdSreyk /* 643f23d19fdSreyk * EEPROM access registers 644f23d19fdSreyk */ 645f23d19fdSreyk #define AR5K_AR5211_EEPROM_BASE 0x6000 646f23d19fdSreyk #define AR5K_AR5211_EEPROM_DATA 0x6004 647f23d19fdSreyk #define AR5K_AR5211_EEPROM_CMD 0x6008 648f23d19fdSreyk #define AR5K_AR5211_EEPROM_CMD_READ 0x00000001 649f23d19fdSreyk #define AR5K_AR5211_EEPROM_CMD_WRITE 0x00000002 650f23d19fdSreyk #define AR5K_AR5211_EEPROM_CMD_RESET 0x00000004 651f23d19fdSreyk #define AR5K_AR5211_EEPROM_STATUS 0x600c 652f23d19fdSreyk #define AR5K_AR5211_EEPROM_STAT_RDERR 0x00000001 653f23d19fdSreyk #define AR5K_AR5211_EEPROM_STAT_RDDONE 0x00000002 654f23d19fdSreyk #define AR5K_AR5211_EEPROM_STAT_WRERR 0x00000004 655f23d19fdSreyk #define AR5K_AR5211_EEPROM_STAT_WRDONE 0x00000008 656f23d19fdSreyk #define AR5K_AR5211_EEPROM_CFG 0x6010 657f23d19fdSreyk 658f23d19fdSreyk /* 659f23d19fdSreyk * AR5211 EEPROM data registers 660f23d19fdSreyk */ 661f23d19fdSreyk #define AR5K_AR5211_EEPROM_MAGIC 0x3d 662f23d19fdSreyk #define AR5K_AR5211_EEPROM_MAGIC_VALUE 0x5aa5 663f23d19fdSreyk #define AR5K_AR5211_EEPROM_PROTECT 0x3f 664f23d19fdSreyk #define AR5K_AR5211_EEPROM_PROTECT_128_191 0x80 665f23d19fdSreyk #define AR5K_AR5211_EEPROM_REG_DOMAIN 0xbf 666f23d19fdSreyk #define AR5K_AR5211_EEPROM_INFO_BASE 0xc0 667f23d19fdSreyk #define AR5K_AR5211_EEPROM_INFO_VERSION \ 668f23d19fdSreyk (AR5K_AR5211_EEPROM_INFO_BASE + 1) 669f23d19fdSreyk #define AR5K_AR5211_EEPROM_INFO_MAX \ 670f23d19fdSreyk (0x400 - AR5K_AR5211_EEPROM_INFO_BASE) 671f23d19fdSreyk 672f23d19fdSreyk /* 673f23d19fdSreyk * PCU registers 674f23d19fdSreyk */ 675f23d19fdSreyk 676f23d19fdSreyk #define AR5K_AR5211_PCU_MIN 0x8000 677f23d19fdSreyk #define AR5K_AR5211_PCU_MAX 0x8fff 678f23d19fdSreyk 679f23d19fdSreyk /* 680f23d19fdSreyk * First station id register (MAC address in lower 32 bits) 681f23d19fdSreyk */ 682f23d19fdSreyk #define AR5K_AR5211_STA_ID0 0x8000 683f23d19fdSreyk 684f23d19fdSreyk /* 685f23d19fdSreyk * Second station id register (MAC address in upper 16 bits) 686f23d19fdSreyk */ 687f23d19fdSreyk #define AR5K_AR5211_STA_ID1 0x8004 688f23d19fdSreyk #define AR5K_AR5211_STA_ID1_AP 0x00010000 689f23d19fdSreyk #define AR5K_AR5211_STA_ID1_ADHOC 0x00020000 690f23d19fdSreyk #define AR5K_AR5211_STA_ID1_PWR_SV 0x00040000 691f23d19fdSreyk #define AR5K_AR5211_STA_ID1_NO_KEYSRCH 0x00080000 692f23d19fdSreyk #define AR5K_AR5211_STA_ID1_PCF 0x00100000 693f23d19fdSreyk #define AR5K_AR5211_STA_ID1_DEFAULT_ANTENNA 0x00200000 694f23d19fdSreyk #define AR5K_AR5211_STA_ID1_DESC_ANTENNA 0x00400000 695f23d19fdSreyk #define AR5K_AR5211_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000 696f23d19fdSreyk #define AR5K_AR5211_STA_ID1_ACKCTS_6MB 0x01000000 697f23d19fdSreyk #define AR5K_AR5211_STA_ID1_BASE_RATE_11B 0x02000000 698f23d19fdSreyk 699f23d19fdSreyk /* 700f23d19fdSreyk * First BSSID register (MAC address, lower 32bits) 701f23d19fdSreyk */ 702f23d19fdSreyk #define AR5K_AR5211_BSS_ID0 0x8008 703f23d19fdSreyk 704f23d19fdSreyk /* 705f23d19fdSreyk * Second BSSID register (MAC address in upper 16 bits) 706f23d19fdSreyk * 707f23d19fdSreyk * AID: Association ID 708f23d19fdSreyk */ 709f23d19fdSreyk #define AR5K_AR5211_BSS_ID1 0x800c 710f23d19fdSreyk #define AR5K_AR5211_BSS_ID1_AID 0xffff0000 711f23d19fdSreyk #define AR5K_AR5211_BSS_ID1_AID_S 16 712f23d19fdSreyk 713f23d19fdSreyk /* 714f23d19fdSreyk * Backoff slot time register 715f23d19fdSreyk */ 716f23d19fdSreyk #define AR5K_AR5211_SLOT_TIME 0x8010 717f23d19fdSreyk 718f23d19fdSreyk /* 719f23d19fdSreyk * ACK/CTS timeout register 720f23d19fdSreyk */ 721f23d19fdSreyk #define AR5K_AR5211_TIME_OUT 0x8014 722f23d19fdSreyk #define AR5K_AR5211_TIME_OUT_ACK 0x00001fff 723f23d19fdSreyk #define AR5K_AR5211_TIME_OUT_ACK_S 0 724f23d19fdSreyk #define AR5K_AR5211_TIME_OUT_CTS 0x1fff0000 725f23d19fdSreyk #define AR5K_AR5211_TIME_OUT_CTS_S 16 726f23d19fdSreyk 727f23d19fdSreyk /* 728f23d19fdSreyk * RSSI threshold register 729f23d19fdSreyk */ 730f23d19fdSreyk #define AR5K_AR5211_RSSI_THR 0x8018 731f23d19fdSreyk #define AR5K_AR5211_RSSI_THR_M 0x000000ff 732f23d19fdSreyk #define AR5K_AR5211_RSSI_THR_BMISS 0x0000ff00 733f23d19fdSreyk #define AR5K_AR5211_RSSI_THR_BMISS_S 8 734f23d19fdSreyk 735f23d19fdSreyk /* 736f23d19fdSreyk * Transmit latency register 737f23d19fdSreyk */ 738f23d19fdSreyk #define AR5K_AR5211_USEC 0x801c 739f23d19fdSreyk #define AR5K_AR5211_USEC_1 0x0000007f 740f23d19fdSreyk #define AR5K_AR5211_USEC_1_S 0 741f23d19fdSreyk #define AR5K_AR5211_USEC_32 0x00003f80 742f23d19fdSreyk #define AR5K_AR5211_USEC_32_S 7 743f23d19fdSreyk #define AR5K_AR5211_USEC_TX_LATENCY 0x007fc000 744f23d19fdSreyk #define AR5K_AR5211_USEC_TX_LATENCY_S 14 745f23d19fdSreyk #define AR5K_AR5211_USEC_RX_LATENCY 0x1f800000 746f23d19fdSreyk #define AR5K_AR5211_USEC_RX_LATENCY_S 23 747f23d19fdSreyk #define AR5K_AR5311_USEC_TX_LATENCY 0x000fc000 748f23d19fdSreyk #define AR5K_AR5311_USEC_TX_LATENCY_S 14 749f23d19fdSreyk #define AR5K_AR5311_USEC_RX_LATENCY 0x03f00000 750f23d19fdSreyk #define AR5K_AR5311_USEC_RX_LATENCY_S 20 751f23d19fdSreyk 752f23d19fdSreyk /* 753f23d19fdSreyk * PCU beacon control register 754f23d19fdSreyk */ 755f23d19fdSreyk #define AR5K_AR5211_BEACON 0x8020 756f23d19fdSreyk #define AR5K_AR5211_BEACON_PERIOD 0x0000ffff 757f23d19fdSreyk #define AR5K_AR5211_BEACON_PERIOD_S 0 758f23d19fdSreyk #define AR5K_AR5211_BEACON_TIM 0x007f0000 759f23d19fdSreyk #define AR5K_AR5211_BEACON_TIM_S 16 760f23d19fdSreyk #define AR5K_AR5211_BEACON_ENABLE 0x00800000 761f23d19fdSreyk #define AR5K_AR5211_BEACON_RESET_TSF 0x01000000 762f23d19fdSreyk 763f23d19fdSreyk /* 764f23d19fdSreyk * CFP period register 765f23d19fdSreyk */ 766f23d19fdSreyk #define AR5K_AR5211_CFP_PERIOD 0x8024 767f23d19fdSreyk 768f23d19fdSreyk /* 769f23d19fdSreyk * Next beacon time register 770f23d19fdSreyk */ 771f23d19fdSreyk #define AR5K_AR5211_TIMER0 0x8028 772f23d19fdSreyk 773f23d19fdSreyk /* 774f23d19fdSreyk * Next DMA beacon alert register 775f23d19fdSreyk */ 776f23d19fdSreyk #define AR5K_AR5211_TIMER1 0x802c 777f23d19fdSreyk 778f23d19fdSreyk /* 779f23d19fdSreyk * Next software beacon alert register 780f23d19fdSreyk */ 781f23d19fdSreyk #define AR5K_AR5211_TIMER2 0x8030 782f23d19fdSreyk 783f23d19fdSreyk /* 784f23d19fdSreyk * Next ATIM window time register 785f23d19fdSreyk */ 786f23d19fdSreyk #define AR5K_AR5211_TIMER3 0x8034 787f23d19fdSreyk 788f23d19fdSreyk /* 789f23d19fdSreyk * CFP duration register 790f23d19fdSreyk */ 791f23d19fdSreyk #define AR5K_AR5211_CFP_DUR 0x8038 792f23d19fdSreyk 793f23d19fdSreyk /* 794f23d19fdSreyk * Receive filter register 795f23d19fdSreyk */ 796f23d19fdSreyk #define AR5K_AR5211_RX_FILTER 0x803c 797f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_UNICAST 0x00000001 798f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_MULTICAST 0x00000002 799f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_BROADCAST 0x00000004 800f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_CONTROL 0x00000008 801f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_BEACON 0x00000010 802f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_PROMISC 0x00000020 803f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_PHYERR 0x00000040 804f23d19fdSreyk #define AR5K_AR5211_RX_FILTER_RADARERR 0x00000080 805f23d19fdSreyk 806f23d19fdSreyk /* 807f23d19fdSreyk * Multicast filter register (lower 32 bits) 808f23d19fdSreyk */ 809f23d19fdSreyk #define AR5K_AR5211_MCAST_FIL0 0x8040 810f23d19fdSreyk 811f23d19fdSreyk /* 812f23d19fdSreyk * Multicast filter register (higher 16 bits) 813f23d19fdSreyk */ 814f23d19fdSreyk #define AR5K_AR5211_MCAST_FIL1 0x8044 815f23d19fdSreyk 816f23d19fdSreyk /* 817f23d19fdSreyk * PCU control register 818f23d19fdSreyk */ 819f23d19fdSreyk #define AR5K_AR5211_DIAG_SW 0x8048 820f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_WEP_ACK 0x00000001 821f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_ACK 0x00000002 822f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_CTS 0x00000004 823f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_ENC 0x00000008 824f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_DEC 0x00000010 825f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_DIS_RX 0x00000020 826f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_LOOP_BACK 0x00000040 827f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_CORR_FCS 0x00000080 828f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_CHAN_INFO 0x00000100 829f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_EN_SCRAM_SEED 0x00000200 830f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_ECO_ENABLE 0x00000400 831f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_SCRAM_SEED_M 0x0001fc00 832f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_SCRAM_SEED_S 10 833f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_FRAME_NV0 0x00020000 834f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_OBSPT_M 0x000c0000 835f23d19fdSreyk #define AR5K_AR5211_DIAG_SW_OBSPT_S 18 836f23d19fdSreyk 837f23d19fdSreyk /* 838f23d19fdSreyk * TSF (clock) register (lower 32 bits) 839f23d19fdSreyk */ 840f23d19fdSreyk #define AR5K_AR5211_TSF_L32 0x804c 841f23d19fdSreyk 842f23d19fdSreyk /* 843f23d19fdSreyk * TSF (clock) register (higher 32 bits) 844f23d19fdSreyk */ 845f23d19fdSreyk #define AR5K_AR5211_TSF_U32 0x8050 846f23d19fdSreyk 847f23d19fdSreyk /* 848f23d19fdSreyk * ADDAC test register 849f23d19fdSreyk */ 850f23d19fdSreyk #define AR5K_AR5211_ADDAC_TEST 0x8054 851f23d19fdSreyk 852f23d19fdSreyk /* 853f23d19fdSreyk * Default antenna register 854f23d19fdSreyk */ 855f23d19fdSreyk #define AR5K_AR5211_DEFAULT_ANTENNA 0x8058 856f23d19fdSreyk 857f23d19fdSreyk /* 858f23d19fdSreyk * Last beacon timestamp register 859f23d19fdSreyk */ 860f23d19fdSreyk #define AR5K_AR5211_LAST_TSTP 0x8080 861f23d19fdSreyk 862f23d19fdSreyk /* 863f23d19fdSreyk * NAV register (current) 864f23d19fdSreyk */ 865f23d19fdSreyk #define AR5K_AR5211_NAV 0x8084 866f23d19fdSreyk 867f23d19fdSreyk /* 868f23d19fdSreyk * RTS success register 869f23d19fdSreyk */ 870f23d19fdSreyk #define AR5K_AR5211_RTS_OK 0x8088 871f23d19fdSreyk 872f23d19fdSreyk /* 873f23d19fdSreyk * RTS failure register 874f23d19fdSreyk */ 875f23d19fdSreyk #define AR5K_AR5211_RTS_FAIL 0x808c 876f23d19fdSreyk 877f23d19fdSreyk /* 878f23d19fdSreyk * ACK failure register 879f23d19fdSreyk */ 880f23d19fdSreyk #define AR5K_AR5211_ACK_FAIL 0x8090 881f23d19fdSreyk 882f23d19fdSreyk /* 883f23d19fdSreyk * FCS failure register 884f23d19fdSreyk */ 885f23d19fdSreyk #define AR5K_AR5211_FCS_FAIL 0x8094 886f23d19fdSreyk 887f23d19fdSreyk /* 888f23d19fdSreyk * Beacon count register 889f23d19fdSreyk */ 890f23d19fdSreyk #define AR5K_AR5211_BEACON_CNT 0x8098 891f23d19fdSreyk 892f23d19fdSreyk /* 893f23d19fdSreyk * Key table (WEP) register 894f23d19fdSreyk */ 895f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_0 0x8800 896f23d19fdSreyk #define AR5K_AR5211_KEYTABLE(n) (AR5K_AR5211_KEYTABLE_0 + ((n) * 32)) 897958b4d3eSreyk #define AR5K_AR5211_KEYTABLE_OFF(_n, x) (AR5K_AR5211_KEYTABLE(_n) + (x << 2)) 898958b4d3eSreyk #define AR5K_AR5211_KEYTABLE_TYPE(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 5) 899f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_TYPE_40 0x00000000 900f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_TYPE_104 0x00000001 901f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_TYPE_128 0x00000003 902f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_TYPE_AES 0x00000005 903f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_TYPE_NULL 0x00000007 904958b4d3eSreyk #define AR5K_AR5211_KEYTABLE_MAC0(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 6) 905958b4d3eSreyk #define AR5K_AR5211_KEYTABLE_MAC1(_n) AR5K_AR5211_KEYTABLE_OFF(_n, 7) 906f23d19fdSreyk #define AR5K_AR5211_KEYTABLE_VALID 0x00008000 907f23d19fdSreyk 908958b4d3eSreyk #define AR5K_AR5211_KEYTABLE_SIZE 128 909f23d19fdSreyk #define AR5K_AR5211_KEYCACHE_SIZE 8 910f23d19fdSreyk 911f23d19fdSreyk /* 912f23d19fdSreyk * PHY register 913f23d19fdSreyk */ 914f23d19fdSreyk #define AR5K_AR5211_PHY(_n) (0x9800 + ((_n) << 2)) 915f23d19fdSreyk #define AR5K_AR5211_PHY_SHIFT_2GHZ 0x00004007 916f23d19fdSreyk #define AR5K_AR5211_PHY_SHIFT_5GHZ 0x00000007 917f23d19fdSreyk 918f23d19fdSreyk /* 919f23d19fdSreyk * PHY turbo mode register 920f23d19fdSreyk */ 921f23d19fdSreyk #define AR5K_AR5211_PHY_TURBO 0x9804 922f23d19fdSreyk #define AR5K_AR5211_PHY_TURBO_MODE 0x00000001 923f23d19fdSreyk #define AR5K_AR5211_PHY_TURBO_SHORT 0x00000002 924f23d19fdSreyk 925f23d19fdSreyk /* 926f23d19fdSreyk * PHY agility command register 927f23d19fdSreyk */ 928f23d19fdSreyk #define AR5K_AR5211_PHY_AGC 0x9808 929f23d19fdSreyk #define AR5K_AR5211_PHY_AGC_DISABLE 0x08000000 930f23d19fdSreyk 931f23d19fdSreyk /* 932f23d19fdSreyk * PHY chip revision register 933f23d19fdSreyk */ 934f23d19fdSreyk #define AR5K_AR5211_PHY_CHIP_ID 0x9818 935f23d19fdSreyk 936f23d19fdSreyk /* 937f23d19fdSreyk * PHY activation register 938f23d19fdSreyk */ 939f23d19fdSreyk #define AR5K_AR5211_PHY_ACTIVE 0x981c 940f23d19fdSreyk #define AR5K_AR5211_PHY_ENABLE 0x00000001 941f23d19fdSreyk #define AR5K_AR5211_PHY_DISABLE 0x00000002 942f23d19fdSreyk 943f23d19fdSreyk /* 944f23d19fdSreyk * PHY agility control register 945f23d19fdSreyk */ 946f23d19fdSreyk #define AR5K_AR5211_PHY_AGCCTL 0x9860 947f23d19fdSreyk #define AR5K_AR5211_PHY_AGCCTL_CAL 0x00000001 948f23d19fdSreyk #define AR5K_AR5211_PHY_AGCCTL_NF 0x00000002 949f23d19fdSreyk 950f23d19fdSreyk /* 951f23d19fdSreyk * PHY noise floor status register 952f23d19fdSreyk */ 953f23d19fdSreyk #define AR5K_AR5211_PHY_NF 0x9864 954f23d19fdSreyk #define AR5K_AR5211_PHY_NF_M 0x000001ff 955f23d19fdSreyk #define AR5K_AR5211_PHY_NF_ACTIVE 0x00000100 956f23d19fdSreyk #define AR5K_AR5211_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5211_PHY_NF_M) 957f23d19fdSreyk #define AR5K_AR5211_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5211_PHY_NF_M) + 1) 958f23d19fdSreyk #define AR5K_AR5211_PHY_NF_SVAL(_n) (((_n) & AR5K_AR5211_PHY_NF_M) | (1 << 9)) 959f23d19fdSreyk 960f23d19fdSreyk /* 961f23d19fdSreyk * PHY PLL control register 962f23d19fdSreyk */ 963f23d19fdSreyk #define AR5K_AR5211_PHY_PLL 0x987c 964f23d19fdSreyk #define AR5K_AR5211_PHY_PLL_20MHZ 0x13 965f23d19fdSreyk #define AR5K_AR5211_PHY_PLL_40MHZ 0x18 966f23d19fdSreyk #define AR5K_AR5211_PHY_PLL_44MHZ 0x19 967f23d19fdSreyk 968f23d19fdSreyk /* 969f23d19fdSreyk * PHY receiver delay register 970f23d19fdSreyk */ 971f23d19fdSreyk #define AR5K_AR5211_PHY_RX_DELAY 0x9914 972f23d19fdSreyk #define AR5K_AR5211_PHY_RX_DELAY_M 0x00003fff 973f23d19fdSreyk 974f23d19fdSreyk /* 975f23d19fdSreyk * PHY timing IQ control register 976f23d19fdSreyk */ 977f23d19fdSreyk #define AR5K_AR5211_PHY_IQ 0x9920 978f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CORR_Q_Q_COFF 0x0000001f 979f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF 0x000007e0 980f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CORR_Q_I_COFF_S 5 981f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CORR_ENABLE 0x00000800 982f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 983f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_CAL_NUM_LOG_MAX_S 12 984f23d19fdSreyk #define AR5K_AR5211_PHY_IQ_RUN 0x00010000 985f23d19fdSreyk 986f23d19fdSreyk /* 987f23d19fdSreyk * PHY PAPD probe register 988f23d19fdSreyk */ 989f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE 0x9930 990f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR 0x00007e00 991f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE_TX_PWR_S 9 992f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE_TX_NEXT 0x00008000 993f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE_GAINF 0xfe000000 994f23d19fdSreyk #define AR5K_AR5211_PHY_PAPD_PROBE_GAINF_S 25 995f23d19fdSreyk 996f23d19fdSreyk /* 997f23d19fdSreyk * PHY frame control register 998f23d19fdSreyk */ 999f23d19fdSreyk #define AR5K_AR5211_PHY_FC 0x9944 1000f23d19fdSreyk #define AR5K_AR5211_PHY_FC_TX_CLIP 0x00000038 1001f23d19fdSreyk #define AR5K_AR5211_PHY_FC_TX_CLIP_S 3 1002f23d19fdSreyk 1003f23d19fdSreyk /* 1004f23d19fdSreyk * PHY radar detection enable register 1005f23d19fdSreyk */ 1006f23d19fdSreyk #define AR5K_AR5211_PHY_RADAR 0x9954 1007f23d19fdSreyk #define AR5K_AR5211_PHY_RADAR_DISABLE 0x00000000 1008f23d19fdSreyk #define AR5K_AR5211_PHY_RADAR_ENABLE 0x00000001 1009f23d19fdSreyk 1010f23d19fdSreyk /* 1011f23d19fdSreyk * PHY antenna switch table registers 1012f23d19fdSreyk */ 1013f23d19fdSreyk #define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_0 0x9960 1014f23d19fdSreyk #define AR5K_AR5211_PHY_ANT_SWITCH_TABLE_1 0x9964 1015f23d19fdSreyk 1016f23d19fdSreyk /* 1017f23d19fdSreyk * PHY timing IQ calibration result register 1018f23d19fdSreyk */ 1019f23d19fdSreyk #define AR5K_AR5211_PHY_IQRES_CAL_PWR_I 0x9c10 1020f23d19fdSreyk #define AR5K_AR5211_PHY_IQRES_CAL_PWR_Q 0x9c14 1021f23d19fdSreyk #define AR5K_AR5211_PHY_IQRES_CAL_CORR 0x9c18 1022f23d19fdSreyk 1023f23d19fdSreyk /* 1024f23d19fdSreyk * PHY current RSSI register 1025f23d19fdSreyk */ 1026f23d19fdSreyk #define AR5K_AR5211_PHY_CURRENT_RSSI 0x9c1c 1027f23d19fdSreyk 1028f23d19fdSreyk /* 1029f23d19fdSreyk * PHY mode register 1030f23d19fdSreyk */ 1031f23d19fdSreyk #define AR5K_AR5211_PHY_MODE 0xa200 1032f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_MOD 0x00000001 1033f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_MOD_OFDM 0 1034f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_MOD_CCK 1 1035f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_FREQ 0x00000002 1036f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_FREQ_5GHZ 0 1037f23d19fdSreyk #define AR5K_AR5211_PHY_MODE_FREQ_2GHZ 2 1038f23d19fdSreyk 1039f23d19fdSreyk /* 1040f23d19fdSreyk * Misc PHY/radio registers 1041f23d19fdSreyk */ 1042f23d19fdSreyk #define AR5K_AR5211_BB_GAIN(_n) (0x9b00 + ((_n) << 2)) 1043f23d19fdSreyk #define AR5K_AR5211_RF_GAIN(_n) (0x9a00 + ((_n) << 2)) 1044f23d19fdSreyk 1045f23d19fdSreyk #endif 1046