xref: /openbsd-src/sys/dev/fdt/rkpcie.c (revision 56d02c00c34befa82f36a0070f336a6b39010607)
1*56d02c00Skettenis /*	$OpenBSD: rkpcie.c,v 1.18 2024/02/03 10:37:26 kettenis Exp $	*/
2727cb1a9Skettenis /*
3727cb1a9Skettenis  * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
4727cb1a9Skettenis  *
5727cb1a9Skettenis  * Permission to use, copy, modify, and distribute this software for any
6727cb1a9Skettenis  * purpose with or without fee is hereby granted, provided that the above
7727cb1a9Skettenis  * copyright notice and this permission notice appear in all copies.
8727cb1a9Skettenis  *
9727cb1a9Skettenis  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10727cb1a9Skettenis  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11727cb1a9Skettenis  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12727cb1a9Skettenis  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13727cb1a9Skettenis  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14727cb1a9Skettenis  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15727cb1a9Skettenis  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16727cb1a9Skettenis  */
17727cb1a9Skettenis 
18727cb1a9Skettenis #include <sys/param.h>
19727cb1a9Skettenis #include <sys/systm.h>
20727cb1a9Skettenis #include <sys/device.h>
21727cb1a9Skettenis #include <sys/extent.h>
22727cb1a9Skettenis #include <sys/malloc.h>
23727cb1a9Skettenis 
24727cb1a9Skettenis #include <machine/intr.h>
25727cb1a9Skettenis #include <machine/bus.h>
26727cb1a9Skettenis #include <machine/fdt.h>
27727cb1a9Skettenis 
28727cb1a9Skettenis #include <dev/pci/pcidevs.h>
29727cb1a9Skettenis #include <dev/pci/pcireg.h>
30727cb1a9Skettenis #include <dev/pci/pcivar.h>
31727cb1a9Skettenis 
32727cb1a9Skettenis #include <dev/ofw/openfirm.h>
33727cb1a9Skettenis #include <dev/ofw/ofw_clock.h>
34727cb1a9Skettenis #include <dev/ofw/ofw_gpio.h>
35727cb1a9Skettenis #include <dev/ofw/ofw_misc.h>
36b7c46c5dSpatrick #include <dev/ofw/ofw_regulator.h>
37727cb1a9Skettenis #include <dev/ofw/fdt.h>
38727cb1a9Skettenis 
39727cb1a9Skettenis #define PCIE_CLIENT_BASIC_STRAP_CONF	0x0000
40727cb1a9Skettenis #define  PCIE_CLIENT_PCIE_GEN_SEL_1	(((1 << 7) << 16) | (0 << 7))
41727cb1a9Skettenis #define  PCIE_CLIENT_PCIE_GEN_SEL_2	(((1 << 7) << 16) | (1 << 7))
42727cb1a9Skettenis #define  PCIE_CLIENT_MODE_SELECT_RC	(((1 << 6) << 16) | (1 << 6))
43727cb1a9Skettenis #define  PCIE_CLIENT_LINK_TRAIN_EN	(((1 << 1) << 16) | (1 << 1))
44727cb1a9Skettenis #define  PCIE_CLIENT_CONF_EN		(((1 << 0) << 16) | (1 << 0))
45820ef841Skurt #define PCIE_CLIENT_DEBUG_OUT_0		0x003c
46820ef841Skurt #define  PCIE_CLIENT_DEBUG_LTSSM_MASK	0x0000001f
47820ef841Skurt #define  PCIE_CLIENT_DEBUG_LTSSM_L0	0x00000010
48727cb1a9Skettenis #define PCIE_CLIENT_BASIC_STATUS1	0x0048
49727cb1a9Skettenis #define  PCIE_CLIENT_LINK_ST		(0x3 << 20)
50727cb1a9Skettenis #define  PCIE_CLIENT_LINK_ST_UP		(0x3 << 20)
51727cb1a9Skettenis #define PCIE_CLIENT_INT_MASK		0x004c
52727cb1a9Skettenis #define  PCIE_CLIENT_INTD_MASK		(((1 << 8) << 16) | (1 << 8))
53727cb1a9Skettenis #define  PCIE_CLIENT_INTD_UNMASK	(((1 << 8) << 16) | (0 << 8))
54727cb1a9Skettenis #define  PCIE_CLIENT_INTC_MASK		(((1 << 7) << 16) | (1 << 7))
55727cb1a9Skettenis #define  PCIE_CLIENT_INTC_UNMASK	(((1 << 7) << 16) | (0 << 7))
56727cb1a9Skettenis #define  PCIE_CLIENT_INTB_MASK		(((1 << 6) << 16) | (1 << 6))
57727cb1a9Skettenis #define  PCIE_CLIENT_INTB_UNMASK	(((1 << 6) << 16) | (0 << 6))
58727cb1a9Skettenis #define  PCIE_CLIENT_INTA_MASK		(((1 << 5) << 16) | (1 << 5))
59727cb1a9Skettenis #define  PCIE_CLIENT_INTA_UNMASK	(((1 << 5) << 16) | (0 << 5))
60727cb1a9Skettenis 
61727cb1a9Skettenis #define PCIE_RC_NORMAL_BASE		0x800000
62727cb1a9Skettenis 
63727cb1a9Skettenis #define PCIE_LM_BASE			0x900000
64727cb1a9Skettenis #define PCIE_LM_VENDOR_ID		(PCIE_LM_BASE + 0x44)
65727cb1a9Skettenis #define PCIE_LM_RCBAR			(PCIE_LM_BASE + 0x300)
66727cb1a9Skettenis #define  PCIE_LM_RCBARPIE		(1 << 19)
67727cb1a9Skettenis #define  PCIE_LM_RCBARPIS		(1 << 20)
68727cb1a9Skettenis 
69727cb1a9Skettenis #define PCIE_RC_BASE			0xa00000
705f9b80c0Skettenis #define PCIE_RC_PCIE_LCAP		(PCIE_RC_BASE + 0x0cc)
715f9b80c0Skettenis #define  PCIE_RC_PCIE_LCAP_APMS_L0S	(1 << 10)
72820ef841Skurt #define PCIE_RC_LCSR			(PCIE_RC_BASE + 0x0d0)
73820ef841Skurt #define PCIE_RC_LCSR2			(PCIE_RC_BASE + 0x0f0)
74727cb1a9Skettenis 
75727cb1a9Skettenis #define PCIE_ATR_BASE			0xc00000
76727cb1a9Skettenis #define PCIE_ATR_OB_ADDR0(i)		(PCIE_ATR_BASE + 0x000 + (i) * 0x20)
77727cb1a9Skettenis #define PCIE_ATR_OB_ADDR1(i)		(PCIE_ATR_BASE + 0x004 + (i) * 0x20)
78727cb1a9Skettenis #define PCIE_ATR_OB_DESC0(i)		(PCIE_ATR_BASE + 0x008 + (i) * 0x20)
79727cb1a9Skettenis #define PCIE_ATR_OB_DESC1(i)		(PCIE_ATR_BASE + 0x00c + (i) * 0x20)
80727cb1a9Skettenis #define PCIE_ATR_IB_ADDR0(i)		(PCIE_ATR_BASE + 0x800 + (i) * 0x8)
81727cb1a9Skettenis #define PCIE_ATR_IB_ADDR1(i)		(PCIE_ATR_BASE + 0x804 + (i) * 0x8)
82727cb1a9Skettenis #define  PCIE_ATR_HDR_MEM		0x2
83727cb1a9Skettenis #define  PCIE_ATR_HDR_IO		0x6
84727cb1a9Skettenis #define  PCIE_ATR_HDR_CFG_TYPE0		0xa
85727cb1a9Skettenis #define  PCIE_ATR_HDR_CFG_TYPE1		0xb
86727cb1a9Skettenis #define  PCIE_ATR_HDR_RID		(1 << 23)
87727cb1a9Skettenis 
885f9b80c0Skettenis #define PCIE_ATR_OB_REGION0_SIZE	(32 * 1024 * 1024)
895f9b80c0Skettenis #define PCIE_ATR_OB_REGION_SIZE		(1 * 1024 * 1024)
905f9b80c0Skettenis 
91727cb1a9Skettenis #define HREAD4(sc, reg)							\
92727cb1a9Skettenis 	(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
93727cb1a9Skettenis #define HWRITE4(sc, reg, val)						\
94727cb1a9Skettenis 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
95727cb1a9Skettenis 
96727cb1a9Skettenis struct rkpcie_softc {
97727cb1a9Skettenis 	struct device		sc_dev;
98727cb1a9Skettenis 	bus_space_tag_t		sc_iot;
99727cb1a9Skettenis 	bus_space_handle_t	sc_ioh;
100727cb1a9Skettenis 	bus_space_handle_t	sc_axi_ioh;
1015f9b80c0Skettenis 	bus_addr_t		sc_axi_addr;
1025f9b80c0Skettenis 	bus_addr_t		sc_apb_addr;
103727cb1a9Skettenis 	int			sc_node;
104727cb1a9Skettenis 	int			sc_phy_node;
105727cb1a9Skettenis 
1062b0be198Skettenis 	struct machine_pci_chipset sc_pc;
107727cb1a9Skettenis 	struct extent		*sc_busex;
108727cb1a9Skettenis 	struct extent		*sc_memex;
109727cb1a9Skettenis 	struct extent		*sc_ioex;
1105f9b80c0Skettenis 	int			sc_bus;
111727cb1a9Skettenis };
112727cb1a9Skettenis 
113727cb1a9Skettenis int rkpcie_match(struct device *, void *, void *);
114727cb1a9Skettenis void rkpcie_attach(struct device *, struct device *, void *);
115727cb1a9Skettenis 
1169fdf0c62Smpi const struct cfattach	rkpcie_ca = {
117727cb1a9Skettenis 	sizeof (struct rkpcie_softc), rkpcie_match, rkpcie_attach
118727cb1a9Skettenis };
119727cb1a9Skettenis 
120727cb1a9Skettenis struct cfdriver rkpcie_cd = {
121727cb1a9Skettenis 	NULL, "rkpcie", DV_DULL
122727cb1a9Skettenis };
123727cb1a9Skettenis 
124727cb1a9Skettenis int
rkpcie_match(struct device * parent,void * match,void * aux)125727cb1a9Skettenis rkpcie_match(struct device *parent, void *match, void *aux)
126727cb1a9Skettenis {
127727cb1a9Skettenis 	struct fdt_attach_args *faa = aux;
128727cb1a9Skettenis 
129727cb1a9Skettenis 	return OF_is_compatible(faa->fa_node, "rockchip,rk3399-pcie");
130727cb1a9Skettenis }
131727cb1a9Skettenis 
132727cb1a9Skettenis void	rkpcie_atr_init(struct rkpcie_softc *);
133727cb1a9Skettenis void	rkpcie_phy_init(struct rkpcie_softc *);
134727cb1a9Skettenis void	rkpcie_phy_poweron(struct rkpcie_softc *);
135727cb1a9Skettenis 
136727cb1a9Skettenis void	rkpcie_attach_hook(struct device *, struct device *,
137727cb1a9Skettenis 	    struct pcibus_attach_args *);
138727cb1a9Skettenis int	rkpcie_bus_maxdevs(void *, int);
139727cb1a9Skettenis pcitag_t rkpcie_make_tag(void *, int, int, int);
140727cb1a9Skettenis void	rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
141727cb1a9Skettenis int	rkpcie_conf_size(void *, pcitag_t);
142727cb1a9Skettenis pcireg_t rkpcie_conf_read(void *, pcitag_t, int);
143727cb1a9Skettenis void	rkpcie_conf_write(void *, pcitag_t, int, pcireg_t);
144619b146dSpatrick int	rkpcie_probe_device_hook(void *, struct pci_attach_args *);
145727cb1a9Skettenis 
146727cb1a9Skettenis int	rkpcie_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
147727cb1a9Skettenis const char *rkpcie_intr_string(void *, pci_intr_handle_t);
148727cb1a9Skettenis void	*rkpcie_intr_establish(void *, pci_intr_handle_t, int,
149d67371fdSpatrick 	    struct cpu_info *, int (*)(void *), void *, char *);
150727cb1a9Skettenis void	rkpcie_intr_disestablish(void *, void *);
151727cb1a9Skettenis 
152820ef841Skurt /*
153820ef841Skurt  * When link training, the LTSSM configuration state exits to L0 state upon
154820ef841Skurt  * success. Wait for L0 state before proceeding after link training has been
155820ef841Skurt  * initiated either by PCIE_CLIENT_LINK_TRAIN_EN or when triggered via
156820ef841Skurt  * LCSR Retrain Link bit. See PCIE 2.0 Base Specification, 4.2.6.3.6
157820ef841Skurt  * Configuration.Idle.
158820ef841Skurt  *
159820ef841Skurt  * Checking link up alone is not sufficient for checking for L0 state. LTSSM
160820ef841Skurt  * state L0 can be detected when link up is set and link training is cleared.
161820ef841Skurt  * See PCIE 2.0 Base Specification, 4.2.6 Link Training and Status State Rules,
162820ef841Skurt  * Table 4-8 Link Status Mapped to the LTSSM.
163820ef841Skurt  *
164820ef841Skurt  * However, RC doesn't set the link training bit when initially training via
165820ef841Skurt  * PCIE_CLIENT_LINK_TRAIN_EN. Fortunately, RC has provided a debug register
166820ef841Skurt  * that has the LTSSM state which can be checked instead.
167820ef841Skurt  *
168820ef841Skurt  * It is important to have reached L0 state before beginning Gen 2 training,
169820ef841Skurt  * as it is documented that setting the Retrain Link bit while currently
170820ef841Skurt  * in Recovery or Configuration states is a race condition that may result
171b3af768dSjsg  * in missing the retraining. See PCIE 2.0 Base Specification, 7.8.7
172820ef841Skurt  * Link Control Register implementation notes on Retrain Link bit.
173820ef841Skurt  */
174820ef841Skurt 
175820ef841Skurt static int
rkpcie_link_training_wait(struct rkpcie_softc * sc)176820ef841Skurt rkpcie_link_training_wait(struct rkpcie_softc *sc)
177820ef841Skurt {
178820ef841Skurt 	uint32_t status;
179820ef841Skurt 	int timo;
180820ef841Skurt 	for (timo = 500; timo > 0; timo--) {
181820ef841Skurt 		status = HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0);
182820ef841Skurt 		if ((status & PCIE_CLIENT_DEBUG_LTSSM_MASK) ==
183820ef841Skurt 		    PCIE_CLIENT_DEBUG_LTSSM_L0)
184820ef841Skurt 			break;
185820ef841Skurt 		delay(1000);
186820ef841Skurt 	}
187820ef841Skurt 	return timo == 0;
188820ef841Skurt }
189820ef841Skurt 
190727cb1a9Skettenis void
rkpcie_attach(struct device * parent,struct device * self,void * aux)191727cb1a9Skettenis rkpcie_attach(struct device *parent, struct device *self, void *aux)
192727cb1a9Skettenis {
193727cb1a9Skettenis 	struct rkpcie_softc *sc = (struct rkpcie_softc *)self;
194727cb1a9Skettenis 	struct fdt_attach_args *faa = aux;
195727cb1a9Skettenis 	struct pcibus_attach_args pba;
196b7c46c5dSpatrick 	uint32_t *ep_gpio = NULL;
1975f9b80c0Skettenis 	uint32_t bus_range[2];
198727cb1a9Skettenis 	uint32_t status;
199820ef841Skurt 	uint32_t max_link_speed;
200820ef841Skurt 	int len;
201727cb1a9Skettenis 
202727cb1a9Skettenis 	if (faa->fa_nreg < 2) {
203727cb1a9Skettenis 		printf(": no registers\n");
204727cb1a9Skettenis 		return;
205727cb1a9Skettenis 	}
206727cb1a9Skettenis 
207727cb1a9Skettenis 	sc->sc_iot = faa->fa_iot;
208727cb1a9Skettenis 
209727cb1a9Skettenis 	if (bus_space_map(sc->sc_iot, faa->fa_reg[1].addr,
210727cb1a9Skettenis 	    faa->fa_reg[1].size, 0, &sc->sc_ioh)) {
211727cb1a9Skettenis 		printf(": can't map registers\n");
212727cb1a9Skettenis 		return;
213727cb1a9Skettenis 	}
214727cb1a9Skettenis 
215727cb1a9Skettenis 	if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr,
216727cb1a9Skettenis 	    faa->fa_reg[0].size, 0, &sc->sc_axi_ioh)) {
217727cb1a9Skettenis 		printf(": can't map AXI registers\n");
218727cb1a9Skettenis 		bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[1].size);
219727cb1a9Skettenis 		return;
220727cb1a9Skettenis 	}
221727cb1a9Skettenis 
2225f9b80c0Skettenis 	sc->sc_axi_addr = faa->fa_reg[0].addr;
2235f9b80c0Skettenis 	sc->sc_apb_addr = faa->fa_reg[1].addr;
224727cb1a9Skettenis 	sc->sc_node = faa->fa_node;
225727cb1a9Skettenis 	printf("\n");
226727cb1a9Skettenis 
227727cb1a9Skettenis 	len = OF_getproplen(sc->sc_node, "ep-gpios");
228b7c46c5dSpatrick 	if (len > 0) {
229727cb1a9Skettenis 		ep_gpio = malloc(len, M_TEMP, M_WAITOK);
230727cb1a9Skettenis 		OF_getpropintarray(sc->sc_node, "ep-gpios", ep_gpio, len);
231b7c46c5dSpatrick 	}
232727cb1a9Skettenis 
233820ef841Skurt 	max_link_speed = OF_getpropint(sc->sc_node, "max-link-speed", 1);
234820ef841Skurt 
235727cb1a9Skettenis 	clock_enable_all(sc->sc_node);
236727cb1a9Skettenis 
237b7c46c5dSpatrick 	regulator_enable(OF_getpropint(sc->sc_node, "vpcie12v-supply", 0));
238b7c46c5dSpatrick 	regulator_enable(OF_getpropint(sc->sc_node, "vpcie3v3-supply", 0));
239b7c46c5dSpatrick 	regulator_enable(OF_getpropint(sc->sc_node, "vpcie1v8-supply", 0));
240b7c46c5dSpatrick 	regulator_enable(OF_getpropint(sc->sc_node, "vpcie0v9-supply", 0));
241b7c46c5dSpatrick 
242b7c46c5dSpatrick 	if (ep_gpio) {
243727cb1a9Skettenis 		gpio_controller_config_pin(ep_gpio, GPIO_CONFIG_OUTPUT);
244727cb1a9Skettenis 		gpio_controller_set_pin(ep_gpio, 0);
245b7c46c5dSpatrick 	}
246727cb1a9Skettenis 
247727cb1a9Skettenis 	reset_assert(sc->sc_node, "aclk");
248727cb1a9Skettenis 	reset_assert(sc->sc_node, "pclk");
249727cb1a9Skettenis 	reset_assert(sc->sc_node, "pm");
250727cb1a9Skettenis 
251727cb1a9Skettenis 	rkpcie_phy_init(sc);
252727cb1a9Skettenis 
253727cb1a9Skettenis 	reset_assert(sc->sc_node, "core");
254727cb1a9Skettenis 	reset_assert(sc->sc_node, "mgmt");
255727cb1a9Skettenis 	reset_assert(sc->sc_node, "mgmt-sticky");
256727cb1a9Skettenis 	reset_assert(sc->sc_node, "pipe");
257727cb1a9Skettenis 
258727cb1a9Skettenis 	delay(10);
259727cb1a9Skettenis 
260727cb1a9Skettenis 	reset_deassert(sc->sc_node, "pm");
261727cb1a9Skettenis 	reset_deassert(sc->sc_node, "aclk");
262727cb1a9Skettenis 	reset_deassert(sc->sc_node, "pclk");
263727cb1a9Skettenis 
264820ef841Skurt 	if (max_link_speed > 1)
265820ef841Skurt 		status = PCIE_CLIENT_PCIE_GEN_SEL_2;
266820ef841Skurt 	else
267820ef841Skurt 		status = PCIE_CLIENT_PCIE_GEN_SEL_1;
268727cb1a9Skettenis 
269727cb1a9Skettenis 	/* Switch into Root Complex mode. */
270820ef841Skurt 	HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_MODE_SELECT_RC
271820ef841Skurt 	    | PCIE_CLIENT_CONF_EN | status);
272727cb1a9Skettenis 
273727cb1a9Skettenis 	rkpcie_phy_poweron(sc);
274727cb1a9Skettenis 
275727cb1a9Skettenis 	reset_deassert(sc->sc_node, "core");
276727cb1a9Skettenis 	reset_deassert(sc->sc_node, "mgmt");
277727cb1a9Skettenis 	reset_deassert(sc->sc_node, "mgmt-sticky");
278727cb1a9Skettenis 	reset_deassert(sc->sc_node, "pipe");
279727cb1a9Skettenis 
280820ef841Skurt 	/*
281820ef841Skurt 	 * Workaround RC bug where Target Link Speed is not set by GEN_SEL_2
282820ef841Skurt 	 */
283820ef841Skurt 	if (max_link_speed > 1) {
284820ef841Skurt 		status = HREAD4(sc, PCIE_RC_LCSR2);
285820ef841Skurt 		status &= ~PCI_PCIE_LCSR2_TLS;
286820ef841Skurt 		status |= PCI_PCIE_LCSR2_TLS_5;
287820ef841Skurt 		HWRITE4(sc, PCIE_RC_LCSR2, status);
288820ef841Skurt 	}
289820ef841Skurt 
290727cb1a9Skettenis 	/* Start link training. */
291727cb1a9Skettenis 	HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCIE_CLIENT_LINK_TRAIN_EN);
292727cb1a9Skettenis 
293727cb1a9Skettenis 	/* XXX Advertise power limits? */
294727cb1a9Skettenis 
295b7c46c5dSpatrick 	if (ep_gpio) {
296727cb1a9Skettenis 		gpio_controller_set_pin(ep_gpio, 1);
297727cb1a9Skettenis 		free(ep_gpio, M_TEMP, len);
298b7c46c5dSpatrick 	}
299727cb1a9Skettenis 
300820ef841Skurt 	if (rkpcie_link_training_wait(sc)) {
301ede3fb81Skettenis 		printf("%s: link training timeout\n", sc->sc_dev.dv_xname);
302ede3fb81Skettenis 		return;
303ede3fb81Skettenis 	}
304727cb1a9Skettenis 
305820ef841Skurt 	if (max_link_speed > 1) {
306820ef841Skurt 		status = HREAD4(sc, PCIE_RC_LCSR);
307820ef841Skurt 		if ((status & PCI_PCIE_LCSR_CLS) == PCI_PCIE_LCSR_CLS_2_5) {
308820ef841Skurt 			HWRITE4(sc, PCIE_RC_LCSR, HREAD4(sc, PCIE_RC_LCSR) |
309820ef841Skurt 			    PCI_PCIE_LCSR_RL);
310820ef841Skurt 
311820ef841Skurt 			if (rkpcie_link_training_wait(sc)) {
312820ef841Skurt 				/* didn't make it back to L0 state */
313820ef841Skurt 				printf("%s: gen2 link training timeout\n",
314820ef841Skurt 				    sc->sc_dev.dv_xname);
315820ef841Skurt 				return;
316820ef841Skurt 			}
317820ef841Skurt 		}
318820ef841Skurt 	}
319820ef841Skurt 
3209857dee3Skurt 	/*
3219857dee3Skurt 	 * XXX On at least the RockPro64, many cards will panic when first
3229857dee3Skurt 	 * accessing PCIe config space during bus scanning. A delay after
3239857dee3Skurt 	 * link training allows some of these cards to function.
3249857dee3Skurt 	 */
3259857dee3Skurt 	delay(2000000);
3269857dee3Skurt 
327727cb1a9Skettenis 	/* Initialize Root Complex registers. */
328727cb1a9Skettenis 	HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP);
329727cb1a9Skettenis 	HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG,
330727cb1a9Skettenis 	    PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT |
331727cb1a9Skettenis 	    PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT);
332727cb1a9Skettenis 	HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS);
333727cb1a9Skettenis 
3345f9b80c0Skettenis 	if (OF_getproplen(sc->sc_node, "aspm-no-l0s") == 0) {
3355f9b80c0Skettenis 		status = HREAD4(sc, PCIE_RC_PCIE_LCAP);
3365f9b80c0Skettenis 		status &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;
3375f9b80c0Skettenis 		HWRITE4(sc, PCIE_RC_PCIE_LCAP, status);
3385f9b80c0Skettenis 	}
3395f9b80c0Skettenis 
3405f9b80c0Skettenis 	/* Create extents for our address spaces. */
3415f9b80c0Skettenis 	sc->sc_busex = extent_create("pcibus", 0, 255,
3425f9b80c0Skettenis 	    M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
3435f9b80c0Skettenis 	sc->sc_memex = extent_create("pcimem", 0, (u_long)-1,
3445f9b80c0Skettenis 	    M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
3455f9b80c0Skettenis 	sc->sc_ioex = extent_create("pciio", 0, 0xffffffff,
3465f9b80c0Skettenis 	    M_DEVBUF, NULL, 0, EX_WAITOK | EX_FILLED);
3475f9b80c0Skettenis 
3485f9b80c0Skettenis 	/* Set up bus range. */
3495f9b80c0Skettenis 	if (OF_getpropintarray(sc->sc_node, "bus-range", bus_range,
3505f9b80c0Skettenis 	    sizeof(bus_range)) != sizeof(bus_range) ||
3515f9b80c0Skettenis 	    bus_range[0] >= 32 || bus_range[1] >= 32) {
3525f9b80c0Skettenis 		bus_range[0] = 0;
3535f9b80c0Skettenis 		bus_range[1] = 31;
3545f9b80c0Skettenis 	}
3555f9b80c0Skettenis 	sc->sc_bus = bus_range[0];
3565f9b80c0Skettenis 	extent_free(sc->sc_busex, bus_range[0],
3575f9b80c0Skettenis 	    bus_range[1] - bus_range[0] + 1, EX_WAITOK);
3585f9b80c0Skettenis 
359727cb1a9Skettenis 	/* Configure Address Translation. */
360727cb1a9Skettenis 	rkpcie_atr_init(sc);
361727cb1a9Skettenis 
362727cb1a9Skettenis 	sc->sc_pc.pc_conf_v = sc;
363727cb1a9Skettenis 	sc->sc_pc.pc_attach_hook = rkpcie_attach_hook;
364727cb1a9Skettenis 	sc->sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs;
365727cb1a9Skettenis 	sc->sc_pc.pc_make_tag = rkpcie_make_tag;
366727cb1a9Skettenis 	sc->sc_pc.pc_decompose_tag = rkpcie_decompose_tag;
367727cb1a9Skettenis 	sc->sc_pc.pc_conf_size = rkpcie_conf_size;
368727cb1a9Skettenis 	sc->sc_pc.pc_conf_read = rkpcie_conf_read;
369727cb1a9Skettenis 	sc->sc_pc.pc_conf_write = rkpcie_conf_write;
370619b146dSpatrick 	sc->sc_pc.pc_probe_device_hook = rkpcie_probe_device_hook;
371727cb1a9Skettenis 
372727cb1a9Skettenis 	sc->sc_pc.pc_intr_v = sc;
373727cb1a9Skettenis 	sc->sc_pc.pc_intr_map = rkpcie_intr_map;
374e410b95bSkettenis 	sc->sc_pc.pc_intr_map_msi = _pci_intr_map_msi;
375*56d02c00Skettenis 	sc->sc_pc.pc_intr_map_msivec = _pci_intr_map_msivec;
376e410b95bSkettenis 	sc->sc_pc.pc_intr_map_msix = _pci_intr_map_msix;
377727cb1a9Skettenis 	sc->sc_pc.pc_intr_string = rkpcie_intr_string;
378727cb1a9Skettenis 	sc->sc_pc.pc_intr_establish = rkpcie_intr_establish;
379727cb1a9Skettenis 	sc->sc_pc.pc_intr_disestablish = rkpcie_intr_disestablish;
380727cb1a9Skettenis 
381727cb1a9Skettenis 	memset(&pba, 0, sizeof(pba));
382727cb1a9Skettenis 	pba.pba_busname = "pci";
383727cb1a9Skettenis 	pba.pba_iot = faa->fa_iot;
384727cb1a9Skettenis 	pba.pba_memt = faa->fa_iot;
385727cb1a9Skettenis 	pba.pba_dmat = faa->fa_dmat;
386727cb1a9Skettenis 	pba.pba_pc = &sc->sc_pc;
387727cb1a9Skettenis 	pba.pba_busex = sc->sc_busex;
388727cb1a9Skettenis 	pba.pba_memex = sc->sc_memex;
389727cb1a9Skettenis 	pba.pba_ioex = sc->sc_ioex;
390727cb1a9Skettenis 	pba.pba_domain = pci_ndomains++;
3915f9b80c0Skettenis 	pba.pba_bus = sc->sc_bus;
392f0a2ac19Skettenis 	pba.pba_flags |= PCI_FLAGS_MSI_ENABLED;
393727cb1a9Skettenis 
394727cb1a9Skettenis 	config_found(self, &pba, NULL);
395727cb1a9Skettenis }
396727cb1a9Skettenis 
397727cb1a9Skettenis void
rkpcie_atr_init(struct rkpcie_softc * sc)398727cb1a9Skettenis rkpcie_atr_init(struct rkpcie_softc *sc)
399727cb1a9Skettenis {
400a945a7c7Sjsg 	uint32_t *ranges = NULL;
4015f9b80c0Skettenis 	struct extent *ex;
4025f9b80c0Skettenis 	bus_addr_t addr;
4035f9b80c0Skettenis 	bus_size_t size, offset;
4045f9b80c0Skettenis 	uint32_t type;
4055f9b80c0Skettenis 	int len, region;
406727cb1a9Skettenis 	int i;
407727cb1a9Skettenis 
408727cb1a9Skettenis 	/* Use region 0 to map PCI configuration space. */
409727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1);
410727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0);
411727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_OB_DESC0(0),
412727cb1a9Skettenis 	    PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID);
413727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0);
414727cb1a9Skettenis 
4155f9b80c0Skettenis 	len = OF_getproplen(sc->sc_node, "ranges");
4165f9b80c0Skettenis 	if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0)
4175f9b80c0Skettenis 		goto fail;
4185f9b80c0Skettenis 	ranges = malloc(len, M_TEMP, M_WAITOK);
4195f9b80c0Skettenis 	OF_getpropintarray(sc->sc_node, "ranges", ranges, len);
4205f9b80c0Skettenis 
4215f9b80c0Skettenis 	for (i = 0; i < len / sizeof(uint32_t); i += 7) {
4225f9b80c0Skettenis 		/* Handle IO and MMIO. */
4235f9b80c0Skettenis 		switch (ranges[i] & 0x03000000) {
4245f9b80c0Skettenis 		case 0x01000000:
4255f9b80c0Skettenis 			type = PCIE_ATR_HDR_IO;
4265f9b80c0Skettenis 			ex = sc->sc_ioex;
4275f9b80c0Skettenis 			break;
4285f9b80c0Skettenis 		case 0x02000000:
4295f9b80c0Skettenis 		case 0x03000000:
4305f9b80c0Skettenis 			type = PCIE_ATR_HDR_MEM;
4315f9b80c0Skettenis 			ex = sc->sc_memex;
4325f9b80c0Skettenis 			break;
4335f9b80c0Skettenis 		default:
4345f9b80c0Skettenis 			continue;
435727cb1a9Skettenis 		}
436727cb1a9Skettenis 
4375f9b80c0Skettenis 		/* Only support identity mappings. */
4385f9b80c0Skettenis 		if (ranges[i + 1] != ranges[i + 3] ||
4395f9b80c0Skettenis 		    ranges[i + 2] != ranges[i + 4])
4405f9b80c0Skettenis 			goto fail;
4415f9b80c0Skettenis 
4425f9b80c0Skettenis 		/* Only support mappings aligned on a region boundary. */
4435f9b80c0Skettenis 		addr = ((uint64_t)ranges[i + 1] << 32) + ranges[i + 2];
4445f9b80c0Skettenis 		if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))
4455f9b80c0Skettenis 			goto fail;
4465f9b80c0Skettenis 
4475f9b80c0Skettenis 		/* Mappings should lie between AXI and APB regions. */
4485f9b80c0Skettenis 		size = ranges[i + 6];
4495f9b80c0Skettenis 		if (addr < sc->sc_axi_addr + PCIE_ATR_OB_REGION0_SIZE)
4505f9b80c0Skettenis 			goto fail;
4515f9b80c0Skettenis 		if (addr + size > sc->sc_apb_addr)
4525f9b80c0Skettenis 			goto fail;
4535f9b80c0Skettenis 
4545f9b80c0Skettenis 		offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE;
4555f9b80c0Skettenis 		region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);
4565f9b80c0Skettenis 		while (size > 0) {
4575f9b80c0Skettenis 			HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1);
4585f9b80c0Skettenis 			HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0);
4595f9b80c0Skettenis 			HWRITE4(sc, PCIE_ATR_OB_DESC0(region),
4605f9b80c0Skettenis 			    type | PCIE_ATR_HDR_RID);
4615f9b80c0Skettenis 			HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0);
4625f9b80c0Skettenis 
4635f9b80c0Skettenis 			extent_free(ex, addr, PCIE_ATR_OB_REGION_SIZE,
4645f9b80c0Skettenis 			    EX_WAITOK);
4655f9b80c0Skettenis 			addr += PCIE_ATR_OB_REGION_SIZE;
4665f9b80c0Skettenis 			size -= PCIE_ATR_OB_REGION_SIZE;
4675f9b80c0Skettenis 			region++;
4685f9b80c0Skettenis 		}
4695f9b80c0Skettenis 	}
470727cb1a9Skettenis 
4714b1a56afSjsg 	/* Passthrough inbound translations unmodified. */
472727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1);
473727cb1a9Skettenis 	HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0);
474727cb1a9Skettenis 
4755f9b80c0Skettenis 	free(ranges, M_TEMP, len);
4765f9b80c0Skettenis 	return;
4775f9b80c0Skettenis 
4785f9b80c0Skettenis fail:
4795f9b80c0Skettenis 	printf("%s: can't map ranges\n", sc->sc_dev.dv_xname);
4805f9b80c0Skettenis 	free(ranges, M_TEMP, len);
481727cb1a9Skettenis }
482727cb1a9Skettenis 
483727cb1a9Skettenis void
rkpcie_attach_hook(struct device * parent,struct device * self,struct pcibus_attach_args * pba)484727cb1a9Skettenis rkpcie_attach_hook(struct device *parent, struct device *self,
485727cb1a9Skettenis     struct pcibus_attach_args *pba)
486727cb1a9Skettenis {
487727cb1a9Skettenis }
488727cb1a9Skettenis 
489727cb1a9Skettenis int
rkpcie_bus_maxdevs(void * v,int bus)4905f9b80c0Skettenis rkpcie_bus_maxdevs(void *v, int bus)
491727cb1a9Skettenis {
4925f9b80c0Skettenis 	struct rkpcie_softc *sc = v;
4935f9b80c0Skettenis 
4945f9b80c0Skettenis 	if (bus == sc->sc_bus || bus == sc->sc_bus + 1)
495727cb1a9Skettenis 		return 1;
4965f9b80c0Skettenis 	return 32;
497727cb1a9Skettenis }
498727cb1a9Skettenis 
499727cb1a9Skettenis pcitag_t
rkpcie_make_tag(void * v,int bus,int device,int function)500727cb1a9Skettenis rkpcie_make_tag(void *v, int bus, int device, int function)
501727cb1a9Skettenis {
502727cb1a9Skettenis 	/* Return ECAM address. */
503727cb1a9Skettenis 	return ((bus << 20) | (device << 15) | (function << 12));
504727cb1a9Skettenis }
505727cb1a9Skettenis 
506727cb1a9Skettenis void
rkpcie_decompose_tag(void * v,pcitag_t tag,int * bp,int * dp,int * fp)507727cb1a9Skettenis rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
508727cb1a9Skettenis {
509727cb1a9Skettenis 	if (bp != NULL)
510727cb1a9Skettenis 		*bp = (tag >> 20) & 0xff;
511727cb1a9Skettenis 	if (dp != NULL)
512727cb1a9Skettenis 		*dp = (tag >> 15) & 0x1f;
513727cb1a9Skettenis 	if (fp != NULL)
514727cb1a9Skettenis 		*fp = (tag >> 12) & 0x7;
515727cb1a9Skettenis }
516727cb1a9Skettenis 
517727cb1a9Skettenis int
rkpcie_conf_size(void * v,pcitag_t tag)518727cb1a9Skettenis rkpcie_conf_size(void *v, pcitag_t tag)
519727cb1a9Skettenis {
520727cb1a9Skettenis 	return PCIE_CONFIG_SPACE_SIZE;
521727cb1a9Skettenis }
522727cb1a9Skettenis 
523727cb1a9Skettenis pcireg_t
rkpcie_conf_read(void * v,pcitag_t tag,int reg)524727cb1a9Skettenis rkpcie_conf_read(void *v, pcitag_t tag, int reg)
525727cb1a9Skettenis {
526727cb1a9Skettenis 	struct rkpcie_softc *sc = v;
527727cb1a9Skettenis 	int bus, dev, fn;
528727cb1a9Skettenis 
529727cb1a9Skettenis 	rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn);
5305f9b80c0Skettenis 	if (bus == sc->sc_bus) {
5315f9b80c0Skettenis 		KASSERT(dev == 0);
532727cb1a9Skettenis 		return HREAD4(sc, PCIE_RC_NORMAL_BASE + tag | reg);
5335f9b80c0Skettenis 	}
5345f9b80c0Skettenis 	if (bus == sc->sc_bus + 1) {
5355f9b80c0Skettenis 		KASSERT(dev == 0);
536727cb1a9Skettenis 		return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg);
537727cb1a9Skettenis 	}
538727cb1a9Skettenis 
5395f9b80c0Skettenis 	return 0xffffffff;
5405f9b80c0Skettenis }
5415f9b80c0Skettenis 
542727cb1a9Skettenis void
rkpcie_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)543727cb1a9Skettenis rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
544727cb1a9Skettenis {
545727cb1a9Skettenis 	struct rkpcie_softc *sc = v;
546727cb1a9Skettenis 	int bus, dev, fn;
547727cb1a9Skettenis 
548727cb1a9Skettenis 	rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn);
5495f9b80c0Skettenis 	if (bus == sc->sc_bus) {
5505f9b80c0Skettenis 		KASSERT(dev == 0);
551727cb1a9Skettenis 		HWRITE4(sc, PCIE_RC_NORMAL_BASE + tag | reg, data);
552727cb1a9Skettenis 		return;
5535f9b80c0Skettenis 	}
5545f9b80c0Skettenis 	if (bus == sc->sc_bus + 1) {
5555f9b80c0Skettenis 		KASSERT(dev == 0);
556727cb1a9Skettenis 		bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, tag | reg, data);
5575f9b80c0Skettenis 		return;
5585f9b80c0Skettenis 	}
559727cb1a9Skettenis }
560727cb1a9Skettenis 
561727cb1a9Skettenis int
rkpcie_probe_device_hook(void * v,struct pci_attach_args * pa)562619b146dSpatrick rkpcie_probe_device_hook(void *v, struct pci_attach_args *pa)
563619b146dSpatrick {
564619b146dSpatrick 	return 0;
565619b146dSpatrick }
566619b146dSpatrick 
567619b146dSpatrick int
rkpcie_intr_map(struct pci_attach_args * pa,pci_intr_handle_t * ihp)568727cb1a9Skettenis rkpcie_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
569727cb1a9Skettenis {
570727cb1a9Skettenis 	int pin = pa->pa_rawintrpin;
571727cb1a9Skettenis 
572727cb1a9Skettenis 	if (pin == 0 || pin > PCI_INTERRUPT_PIN_MAX)
573727cb1a9Skettenis 		return -1;
574727cb1a9Skettenis 
575727cb1a9Skettenis 	if (pa->pa_tag == 0)
576727cb1a9Skettenis 		return -1;
577727cb1a9Skettenis 
578e410b95bSkettenis 	ihp->ih_pc = pa->pa_pc;
579e410b95bSkettenis 	ihp->ih_tag = pa->pa_intrtag;
580e410b95bSkettenis 	ihp->ih_intrpin = pa->pa_intrpin;
581e410b95bSkettenis 	ihp->ih_type = PCI_INTX;
582f8b19a43Skettenis 
583f8b19a43Skettenis 	return 0;
584727cb1a9Skettenis }
585727cb1a9Skettenis 
586727cb1a9Skettenis const char *
rkpcie_intr_string(void * v,pci_intr_handle_t ih)587e410b95bSkettenis rkpcie_intr_string(void *v, pci_intr_handle_t ih)
588727cb1a9Skettenis {
589e410b95bSkettenis 	switch (ih.ih_type) {
590f8b19a43Skettenis 	case PCI_MSI:
591f0a2ac19Skettenis 		return "msi";
592f8b19a43Skettenis 	case PCI_MSIX:
593f8b19a43Skettenis 		return "msix";
594f8b19a43Skettenis 	}
595f0a2ac19Skettenis 
596727cb1a9Skettenis 	return "intx";
597727cb1a9Skettenis }
598727cb1a9Skettenis 
599727cb1a9Skettenis void *
rkpcie_intr_establish(void * v,pci_intr_handle_t ih,int level,struct cpu_info * ci,int (* func)(void *),void * arg,char * name)600e410b95bSkettenis rkpcie_intr_establish(void *v, pci_intr_handle_t ih, int level,
601d67371fdSpatrick     struct cpu_info *ci, int (*func)(void *), void *arg, char *name)
602727cb1a9Skettenis {
603727cb1a9Skettenis 	struct rkpcie_softc *sc = v;
604f0a2ac19Skettenis 	void *cookie;
605727cb1a9Skettenis 
606e410b95bSkettenis 	KASSERT(ih.ih_type != PCI_NONE);
607e410b95bSkettenis 
608e410b95bSkettenis 	if (ih.ih_type != PCI_INTX) {
609*56d02c00Skettenis 		uint64_t addr = 0, data;
610f0a2ac19Skettenis 
611f0a2ac19Skettenis 		/* Assume hardware passes Requester ID as sideband data. */
612e410b95bSkettenis 		data = pci_requester_id(ih.ih_pc, ih.ih_tag);
613d67371fdSpatrick 		cookie = fdt_intr_establish_msi_cpu(sc->sc_node, &addr,
614d67371fdSpatrick 		    &data, level, ci, func, arg, name);
615f0a2ac19Skettenis 		if (cookie == NULL)
616f0a2ac19Skettenis 			return NULL;
617f0a2ac19Skettenis 
618f0a2ac19Skettenis 		/* TODO: translate address to the PCI device's view */
619f0a2ac19Skettenis 
620e410b95bSkettenis 		if (ih.ih_type == PCI_MSIX) {
621e410b95bSkettenis 			pci_msix_enable(ih.ih_pc, ih.ih_tag,
622e410b95bSkettenis 			    sc->sc_iot, ih.ih_intrpin, addr, data);
623f8b19a43Skettenis 		} else
624e410b95bSkettenis 			pci_msi_enable(ih.ih_pc, ih.ih_tag, addr, data);
625f0a2ac19Skettenis 	} else {
626727cb1a9Skettenis 		/* Unmask legacy interrupts. */
627727cb1a9Skettenis 		HWRITE4(sc, PCIE_CLIENT_INT_MASK,
628727cb1a9Skettenis 		    PCIE_CLIENT_INTA_UNMASK | PCIE_CLIENT_INTB_UNMASK |
629727cb1a9Skettenis 		    PCIE_CLIENT_INTC_UNMASK | PCIE_CLIENT_INTD_UNMASK);
630727cb1a9Skettenis 
631d67371fdSpatrick 		cookie = fdt_intr_establish_idx_cpu(sc->sc_node, 1, level,
632d67371fdSpatrick 		    ci, func, arg, name);
633727cb1a9Skettenis 	}
634727cb1a9Skettenis 
635f0a2ac19Skettenis 	return cookie;
636f0a2ac19Skettenis }
637f0a2ac19Skettenis 
638727cb1a9Skettenis void
rkpcie_intr_disestablish(void * v,void * cookie)639727cb1a9Skettenis rkpcie_intr_disestablish(void *v, void *cookie)
640727cb1a9Skettenis {
641727cb1a9Skettenis }
642727cb1a9Skettenis 
643727cb1a9Skettenis /*
644727cb1a9Skettenis  * PHY Support.
645727cb1a9Skettenis  */
646727cb1a9Skettenis 
647727cb1a9Skettenis #define RK3399_GRF_SOC_CON5_PCIE	0xe214
648727cb1a9Skettenis #define  RK3399_TX_ELEC_IDLE_OFF_MASK	((1 << 3) << 16)
649727cb1a9Skettenis #define  RK3399_TX_ELEC_IDLE_OFF	(1 << 3)
650727cb1a9Skettenis #define RK3399_GRF_SOC_CON8		0xe220
651727cb1a9Skettenis #define  RK3399_PCIE_TEST_DATA_MASK	((0xf << 7) << 16)
652727cb1a9Skettenis #define  RK3399_PCIE_TEST_DATA_SHIFT	7
653727cb1a9Skettenis #define  RK3399_PCIE_TEST_ADDR_MASK	((0x3f << 1) << 16)
654727cb1a9Skettenis #define  RK3399_PCIE_TEST_ADDR_SHIFT	1
655727cb1a9Skettenis #define  RK3399_PCIE_TEST_WRITE_ENABLE	(((1 << 0) << 16) | (1 << 0))
656727cb1a9Skettenis #define  RK3399_PCIE_TEST_WRITE_DISABLE	(((1 << 0) << 16) | (0 << 0))
657727cb1a9Skettenis #define RK3399_GRF_SOC_STATUS1		0xe2a4
658727cb1a9Skettenis #define  RK3399_PCIE_PHY_PLL_LOCKED	(1 << 9)
659727cb1a9Skettenis #define  RK3399_PCIE_PHY_PLL_OUTPUT	(1 << 10)
660727cb1a9Skettenis 
661727cb1a9Skettenis #define RK3399_PCIE_PHY_CFG_PLL_LOCK	0x10
662727cb1a9Skettenis #define RK3399_PCIE_PHY_CFG_CLK_TEST	0x10
663727cb1a9Skettenis #define  RK3399_PCIE_PHY_CFG_SEPE_RATE	(1 << 3)
664727cb1a9Skettenis #define RK3399_PCIE_PHY_CFG_CLK_SCC	0x12
665727cb1a9Skettenis #define  RK3399_PCIE_PHY_CFG_PLL_100M	(1 << 3)
666727cb1a9Skettenis 
667727cb1a9Skettenis void
rkpcie_phy_init(struct rkpcie_softc * sc)668727cb1a9Skettenis rkpcie_phy_init(struct rkpcie_softc *sc)
669727cb1a9Skettenis {
670ede3fb81Skettenis 	uint32_t phys[8];
671ede3fb81Skettenis 	int len;
672727cb1a9Skettenis 
673ede3fb81Skettenis 	len = OF_getpropintarray(sc->sc_node, "phys", phys, sizeof(phys));
674ede3fb81Skettenis 	if (len < sizeof(phys[0]))
675727cb1a9Skettenis 		return;
676727cb1a9Skettenis 
677ede3fb81Skettenis 	sc->sc_phy_node = OF_getnodebyphandle(phys[0]);
678727cb1a9Skettenis 	if (sc->sc_phy_node == 0)
679727cb1a9Skettenis 		return;
680727cb1a9Skettenis 
681b7c46c5dSpatrick 	clock_set_assigned(sc->sc_phy_node);
682727cb1a9Skettenis 	clock_enable(sc->sc_phy_node, "refclk");
683727cb1a9Skettenis 	reset_assert(sc->sc_phy_node, "phy");
684727cb1a9Skettenis }
685727cb1a9Skettenis 
686727cb1a9Skettenis void
rkpcie_phy_write_conf(struct regmap * rm,uint8_t addr,uint8_t data)687727cb1a9Skettenis rkpcie_phy_write_conf(struct regmap *rm, uint8_t addr, uint8_t data)
688727cb1a9Skettenis {
689727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON8,
690727cb1a9Skettenis 	    RK3399_PCIE_TEST_ADDR_MASK |
691727cb1a9Skettenis 	    (addr << RK3399_PCIE_TEST_ADDR_SHIFT) |
692727cb1a9Skettenis 	    RK3399_PCIE_TEST_DATA_MASK |
693727cb1a9Skettenis 	    (data << RK3399_PCIE_TEST_DATA_SHIFT) |
694727cb1a9Skettenis 	    RK3399_PCIE_TEST_WRITE_DISABLE);
695727cb1a9Skettenis 	delay(1);
696727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON8,
697727cb1a9Skettenis 	    RK3399_PCIE_TEST_WRITE_ENABLE);
698727cb1a9Skettenis 	delay(1);
699727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON8,
700727cb1a9Skettenis 	    RK3399_PCIE_TEST_WRITE_DISABLE);
701727cb1a9Skettenis }
702727cb1a9Skettenis 
703727cb1a9Skettenis void
rkpcie_phy_poweron(struct rkpcie_softc * sc)704727cb1a9Skettenis rkpcie_phy_poweron(struct rkpcie_softc *sc)
705727cb1a9Skettenis {
706727cb1a9Skettenis 	struct regmap *rm;
707727cb1a9Skettenis 	uint32_t status;
708727cb1a9Skettenis 	int lane = 0;
709727cb1a9Skettenis 	int timo;
710727cb1a9Skettenis 
711727cb1a9Skettenis 	reset_deassert(sc->sc_phy_node, "phy");
712727cb1a9Skettenis 
713727cb1a9Skettenis 	rm = regmap_bynode(OF_parent(sc->sc_phy_node));
714727cb1a9Skettenis 	if (rm == NULL)
715727cb1a9Skettenis 		return;
716727cb1a9Skettenis 
717727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON8,
718727cb1a9Skettenis 	    RK3399_PCIE_TEST_ADDR_MASK |
719727cb1a9Skettenis 	    RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT);
720727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON5_PCIE,
721727cb1a9Skettenis 	    RK3399_TX_ELEC_IDLE_OFF_MASK << lane | 0);
722727cb1a9Skettenis 
723727cb1a9Skettenis 	for (timo = 50; timo > 0; timo--) {
724727cb1a9Skettenis 		status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);
725727cb1a9Skettenis 		if (status & RK3399_PCIE_PHY_PLL_LOCKED)
726727cb1a9Skettenis 			break;
727727cb1a9Skettenis 		delay(20000);
728727cb1a9Skettenis 	}
729727cb1a9Skettenis 	if (timo == 0) {
730727cb1a9Skettenis 		printf("%s: PHY PLL lock timeout\n", sc->sc_dev.dv_xname);
731727cb1a9Skettenis 		return;
732727cb1a9Skettenis 	}
733727cb1a9Skettenis 
734727cb1a9Skettenis 	rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_TEST,
735727cb1a9Skettenis 	    RK3399_PCIE_PHY_CFG_SEPE_RATE);
736727cb1a9Skettenis 	rkpcie_phy_write_conf(rm, RK3399_PCIE_PHY_CFG_CLK_SCC,
737727cb1a9Skettenis 	    RK3399_PCIE_PHY_CFG_PLL_100M);
738727cb1a9Skettenis 
739727cb1a9Skettenis 	for (timo = 50; timo > 0; timo--) {
740727cb1a9Skettenis 		status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);
741727cb1a9Skettenis 		if ((status & RK3399_PCIE_PHY_PLL_OUTPUT) == 0)
742727cb1a9Skettenis 			break;
743727cb1a9Skettenis 		delay(20000);
744727cb1a9Skettenis 	}
745727cb1a9Skettenis 	if (timo == 0) {
746727cb1a9Skettenis 		printf("%s: PHY PLL output enable timeout\n",
747727cb1a9Skettenis 		    sc->sc_dev.dv_xname);
748727cb1a9Skettenis 		return;
749727cb1a9Skettenis 	}
750727cb1a9Skettenis 
751727cb1a9Skettenis 	regmap_write_4(rm, RK3399_GRF_SOC_CON8,
752727cb1a9Skettenis 	    RK3399_PCIE_TEST_ADDR_MASK |
753727cb1a9Skettenis 	    RK3399_PCIE_PHY_CFG_PLL_LOCK << RK3399_PCIE_TEST_ADDR_SHIFT);
754727cb1a9Skettenis 
755727cb1a9Skettenis 	for (timo = 50; timo > 0; timo--) {
756727cb1a9Skettenis 		status = regmap_read_4(rm, RK3399_GRF_SOC_STATUS1);
757727cb1a9Skettenis 		if (status & RK3399_PCIE_PHY_PLL_LOCKED)
758727cb1a9Skettenis 			break;
759727cb1a9Skettenis 		delay(20000);
760727cb1a9Skettenis 	}
761727cb1a9Skettenis 	if (timo == 0) {
762727cb1a9Skettenis 		printf("%s: PHY PLL relock timeout\n", sc->sc_dev.dv_xname);
763727cb1a9Skettenis 		return;
764727cb1a9Skettenis 	}
765727cb1a9Skettenis }
766