xref: /openbsd-src/sys/arch/sparc64/include/instr.h (revision 2e44fda6ab2a47047383d07428958392f5935898)
1*2e44fda6Sjason /*	$OpenBSD: instr.h,v 1.7 2003/07/13 07:00:48 jason Exp $	*/
23ee24058Sjason /*	$NetBSD: instr.h,v 1.3 2000/01/10 03:53:20 eeh Exp $ */
33ee24058Sjason 
43ee24058Sjason /*
53ee24058Sjason  * Copyright (c) 1992, 1993
63ee24058Sjason  *	The Regents of the University of California.  All rights reserved.
73ee24058Sjason  *
83ee24058Sjason  * This software was developed by the Computer Systems Engineering group
93ee24058Sjason  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
103ee24058Sjason  * contributed to Berkeley.
113ee24058Sjason  *
123ee24058Sjason  * All advertising materials mentioning features or use of this software
133ee24058Sjason  * must display the following acknowledgement:
143ee24058Sjason  *	This product includes software developed by the University of
153ee24058Sjason  *	California, Lawrence Berkeley Laboratory.
163ee24058Sjason  *
173ee24058Sjason  * Redistribution and use in source and binary forms, with or without
183ee24058Sjason  * modification, are permitted provided that the following conditions
193ee24058Sjason  * are met:
203ee24058Sjason  * 1. Redistributions of source code must retain the above copyright
213ee24058Sjason  *    notice, this list of conditions and the following disclaimer.
223ee24058Sjason  * 2. Redistributions in binary form must reproduce the above copyright
233ee24058Sjason  *    notice, this list of conditions and the following disclaimer in the
243ee24058Sjason  *    documentation and/or other materials provided with the distribution.
2529295d1cSmillert  * 3. Neither the name of the University nor the names of its contributors
263ee24058Sjason  *    may be used to endorse or promote products derived from this software
273ee24058Sjason  *    without specific prior written permission.
283ee24058Sjason  *
293ee24058Sjason  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
303ee24058Sjason  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
313ee24058Sjason  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
323ee24058Sjason  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
333ee24058Sjason  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
343ee24058Sjason  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
353ee24058Sjason  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
363ee24058Sjason  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
373ee24058Sjason  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
383ee24058Sjason  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
393ee24058Sjason  * SUCH DAMAGE.
403ee24058Sjason  *
413ee24058Sjason  *	@(#)instr.h	8.1 (Berkeley) 6/11/93
423ee24058Sjason  */
433ee24058Sjason 
443ee24058Sjason /* see also Appendix F of the SPARC version 8 document */
453ee24058Sjason enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem };
463ee24058Sjason enum IOP2 { IOP2_UNIMP, IOP2_BPcc, IOP2_Bicc, IOP2_BPr,
473ee24058Sjason 	IOP2_SETHI, IOP2_FBPfcc, IOP2_FBfcc, IOP2_CBccc };
483ee24058Sjason enum IOP3_reg {
493ee24058Sjason 	IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR,
503ee24058Sjason 	IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR,
511ef7fde7Sjason 	IOP3_ADDX, IOP3_MULX, IOP3_UMUL, IOP3_SMUL,
521ef7fde7Sjason 	IOP3_SUBX, IOP3_UDIVX, IOP3_UDIV, IOP3_SDIV,
533ee24058Sjason 	IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc,
543ee24058Sjason 	IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc,
553ee24058Sjason 	IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc,
563ee24058Sjason 	IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc,
573ee24058Sjason 	IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV,
583ee24058Sjason 	IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA,
593ee24058Sjason 	IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR,
601ef7fde7Sjason 	IOP3_MOVcc, IOP3_SDIVX, IOP3_POPC, IOP3_MOVr,
613ee24058Sjason 	IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR,
623ee24058Sjason 	IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2,
633ee24058Sjason 	IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH,
641ef7fde7Sjason 	IOP3_SAVE, IOP3_RESTORE, IOP3_DONE_RETRY, IOP3_rerr3f
653ee24058Sjason };
663ee24058Sjason enum IOP3_mem {
673ee24058Sjason 	IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD,
683ee24058Sjason 	IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD,
69b83e38a1Sjason 	IOP3_LDSW, IOP3_LDSB, IOP3_LDSH, IOP3_LDX,
70b83e38a1Sjason 	IOP3_merr0c, IOP3_LDSTUB, IOP3_STX, IOP3_SWAP,
713ee24058Sjason 	IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA,
723ee24058Sjason 	IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA,
73b83e38a1Sjason 	IOP3_LDSWA, IOP3_LDSBA, IOP3_LDSHA, IOP3_LDXA,
74b83e38a1Sjason 	IOP3_merr1c, IOP3_LDSTUBA, IOP3_STXA, IOP3_SWAPA,
75b83e38a1Sjason 	IOP3_LDF, IOP3_LDFSR, IOP3_LDQF, IOP3_LDDF,
76b83e38a1Sjason 	IOP3_STF, IOP3_STFSR, IOP3_STQF, IOP3_STDF,
773ee24058Sjason 	IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b,
78b83e38a1Sjason 	IOP3_merr2c, IOP3_PREFETCH, IOP3_merr2e, IOP3_merr2f,
79b83e38a1Sjason 	IOP3_LFC, IOP3_LDCSR, IOP3_LDQFA, IOP3_LDDC,
80f6b156ccSjason 	IOP3_STC, IOP3_STCSR, IOP3_STQFA, IOP3_STDC,
813ee24058Sjason 	IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b,
82b83e38a1Sjason 	IOP3_CASA, IOP3_PREFETCHA, IOP3_CASXA, IOP3_merr3f
833ee24058Sjason };
843ee24058Sjason 
853ee24058Sjason /*
863ee24058Sjason  * Integer condition codes.
873ee24058Sjason  */
883ee24058Sjason #define	Icc_N	0x0		/* never */
893ee24058Sjason #define	Icc_E	0x1		/* equal (equiv. zero) */
903ee24058Sjason #define	Icc_LE	0x2		/* less or equal */
913ee24058Sjason #define	Icc_L	0x3		/* less */
923ee24058Sjason #define	Icc_LEU	0x4		/* less or equal unsigned */
933ee24058Sjason #define	Icc_CS	0x5		/* carry set (equiv. less unsigned) */
943ee24058Sjason #define	Icc_NEG	0x6		/* negative */
953ee24058Sjason #define	Icc_VS	0x7		/* overflow set */
963ee24058Sjason #define	Icc_A	0x8		/* always */
973ee24058Sjason #define	Icc_NE	0x9		/* not equal (equiv. not zero) */
983ee24058Sjason #define	Icc_G	0xa		/* greater */
993ee24058Sjason #define	Icc_GE	0xb		/* greater or equal */
1003ee24058Sjason #define	Icc_GU	0xc		/* greater unsigned */
1013ee24058Sjason #define	Icc_CC	0xd		/* carry clear (equiv. gtr or eq unsigned) */
1023ee24058Sjason #define	Icc_POS	0xe		/* positive */
1033ee24058Sjason #define	Icc_VC	0xf		/* overflow clear */
1043ee24058Sjason 
1053ee24058Sjason /*
1063ee24058Sjason  * Integer registers.
1073ee24058Sjason  */
1083ee24058Sjason #define	I_G0	0
1093ee24058Sjason #define	I_G1	1
1103ee24058Sjason #define	I_G2	2
1113ee24058Sjason #define	I_G3	3
1123ee24058Sjason #define	I_G4	4
1133ee24058Sjason #define	I_G5	5
1143ee24058Sjason #define	I_G6	6
1153ee24058Sjason #define	I_G7	7
1163ee24058Sjason #define	I_O0	8
1173ee24058Sjason #define	I_O1	9
1183ee24058Sjason #define	I_O2	10
1193ee24058Sjason #define	I_O3	11
1203ee24058Sjason #define	I_O4	12
1213ee24058Sjason #define	I_O5	13
1223ee24058Sjason #define	I_O6	14
1233ee24058Sjason #define	I_O7	15
1243ee24058Sjason #define	I_L0	16
1253ee24058Sjason #define	I_L1	17
1263ee24058Sjason #define	I_L2	18
1273ee24058Sjason #define	I_L3	19
1283ee24058Sjason #define	I_L4	20
1293ee24058Sjason #define	I_L5	21
1303ee24058Sjason #define	I_L6	22
1313ee24058Sjason #define	I_L7	23
1323ee24058Sjason #define	I_I0	24
1333ee24058Sjason #define	I_I1	25
1343ee24058Sjason #define	I_I2	26
1353ee24058Sjason #define	I_I3	27
1363ee24058Sjason #define	I_I4	28
1373ee24058Sjason #define	I_I5	29
1383ee24058Sjason #define	I_I6	30
1393ee24058Sjason #define	I_I7	31
1403ee24058Sjason 
1413ee24058Sjason /*
1423ee24058Sjason  * An instruction.
1433ee24058Sjason  */
1443ee24058Sjason union instr {
1453ee24058Sjason 	int	i_int;			/* as a whole */
1463ee24058Sjason 
1473ee24058Sjason 	/*
1483ee24058Sjason 	 * The first level of decoding is to use the top 2 bits.
1493ee24058Sjason 	 * This gives us one of three `formats', which usually give
1503ee24058Sjason 	 * a second level of decoding.
1513ee24058Sjason 	 */
1523ee24058Sjason 	struct {
1533ee24058Sjason 		u_int	i_op:2;		/* first-level decode */
1543ee24058Sjason 		u_int	:30;
1553ee24058Sjason 	} i_any;
1563ee24058Sjason 
1573ee24058Sjason 	/*
1583ee24058Sjason 	 * Format 1 instructions: CALL (undifferentiated).
1593ee24058Sjason 	 */
1603ee24058Sjason 	struct {
1613ee24058Sjason 		u_int	:2;		/* 01 */
1623ee24058Sjason 		int	i_disp:30;	/* displacement */
1633ee24058Sjason 	} i_call;
1643ee24058Sjason 
1653ee24058Sjason 	/*
1663ee24058Sjason 	 * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal
1673ee24058Sjason 	 * unused codes).
1683ee24058Sjason 	 */
1693ee24058Sjason 	struct {
1703ee24058Sjason 		u_int	:2;		/* 00 */
1713ee24058Sjason 		u_int	:5;
1723ee24058Sjason 		u_int	i_op2:3;	/* second-level decode */
1733ee24058Sjason 		u_int	:22;
1743ee24058Sjason 	} i_op2;
1753ee24058Sjason 
1763ee24058Sjason 	/* UNIMP, SETHI */
1773ee24058Sjason 	struct {
1783ee24058Sjason 		u_int	:2;		/* 00 */
1793ee24058Sjason 		u_int	i_rd:5;		/* destination register */
1803ee24058Sjason 		u_int	i_op2:3;	/* opcode: UNIMP or SETHI */
1813ee24058Sjason 		u_int	i_imm:22;	/* immediate value */
1823ee24058Sjason 	} i_imm22;
1833ee24058Sjason 
1843ee24058Sjason 	/* branches: Bicc, FBfcc, CBccc */
1853ee24058Sjason 	struct {
1863ee24058Sjason 		u_int	:2;		/* 00 */
1873ee24058Sjason 		u_int	i_annul:1;	/* annul bit */
1883ee24058Sjason 		u_int	i_cond:4;	/* condition codes */
1893ee24058Sjason 		u_int	i_op2:3;	/* opcode: {Bi,FBf,CBc}cc */
1903ee24058Sjason 		int	i_disp:22;	/* branch displacement */
1913ee24058Sjason 	} i_branch;
1923ee24058Sjason 
1933ee24058Sjason 	/* more branches: BPcc, FBPfcc */
1943ee24058Sjason 	struct {
1953ee24058Sjason 		u_int	:2;		/* 00 */
1963ee24058Sjason 		u_int	i_annul:1;	/* annul bit */
1973ee24058Sjason 		u_int	i_cond:4;	/* condition codes */
1983ee24058Sjason 		u_int	i_op2:3;	/* opcode: {BP,FBPf}cc */
1993ee24058Sjason 		u_int	i_cc:2;		/* condition code selector */
2003ee24058Sjason 		u_int	i_pred:1;	/* branch prediction bit */
2013ee24058Sjason 		int	i_disp:19;	/* branch displacement */
2023ee24058Sjason 	} i_branch_p;
2033ee24058Sjason 
2043ee24058Sjason 	/* one last branch: BPr */
2053ee24058Sjason 	struct {
2063ee24058Sjason 		u_int	:2;		/* 00 */
2073ee24058Sjason 		u_int	i_annul:1;	/* annul bit */
2083ee24058Sjason 		u_int	:1;		/* 0 */
2093ee24058Sjason 		u_int	i_rcond:4;	/* register condition */
2103ee24058Sjason 		u_int	:3;		/* 011 */
2113ee24058Sjason 		int	i_disphi:2;	/* branch displacement, hi bits */
2123ee24058Sjason 		u_int   i_pred:1;	/* branch prediction bit */
2133ee24058Sjason 		u_int   i_rs1:1;	/* source register 1 */
2143ee24058Sjason 		u_int	i_displo:16;	/* branch displacement, lo bits */
2153ee24058Sjason 	} i_branch_pr;
2163ee24058Sjason 
2173ee24058Sjason 
2183ee24058Sjason 	/*
2193ee24058Sjason 	 * Format 3 instructions (memory reference; arithmetic, logical,
2203ee24058Sjason 	 * shift, and other miscellaneous operations).  The second-level
2213ee24058Sjason 	 * decode almost always makes use of an `rd' and `rs1', however
2223ee24058Sjason 	 * (see also IOP3_reg and IOP3_mem).
2233ee24058Sjason 	 *
2243ee24058Sjason 	 * Beyond that, the low 14 bits may be broken up in one of three
2253ee24058Sjason 	 * different ways, if at all:
2263ee24058Sjason 	 *	1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
2273ee24058Sjason 	 *	1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
2283ee24058Sjason 	 *	9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only]
2293ee24058Sjason 	 */
2303ee24058Sjason 	struct {
2313ee24058Sjason 		u_int	:2;		/* 10 or 11 */
2323ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2333ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
2343ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
2353ee24058Sjason 		u_int	i_low14:14;	/* varies */
2363ee24058Sjason 	} i_op3;
2373ee24058Sjason 
2383ee24058Sjason 	/*
2393ee24058Sjason 	 * Memory forms.  These set i_op=3 and use simm13 or asi layout.
2403ee24058Sjason 	 * Memory references without an ASI should use 0, but the actual
2413ee24058Sjason 	 * ASI field is simply ignored.
2423ee24058Sjason 	 */
2433ee24058Sjason 	struct {
2443ee24058Sjason 		u_int	:2;		/* 11 only */
2453ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2463ee24058Sjason 		u_int	i_op3:6;	/* second-level decode (see IOP3_mem) */
247*2e44fda6Sjason 		u_int	i_rs1:5;	/* source register 1 */
2483ee24058Sjason 		u_int	i_i:1;		/* immediate vs asi */
2493ee24058Sjason 		u_int	i_low13:13;	/* depend on i bit */
2503ee24058Sjason 	} i_loadstore;
2513ee24058Sjason 
2523ee24058Sjason 	/*
2533ee24058Sjason 	 * Memory and register forms.
2543ee24058Sjason 	 * These come in quite a variety and we do not
2553ee24058Sjason 	 * attempt to break them down much.
2563ee24058Sjason 	 */
2573ee24058Sjason 	struct {
2583ee24058Sjason 		u_int	:2;		/* 10 or 11 */
2593ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2603ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
2613ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
2623ee24058Sjason 		u_int	i_i:1;		/* immediate bit (1) */
2633ee24058Sjason 		int	i_simm13:13;	/* signed immediate */
2643ee24058Sjason 	} i_simm13;
2653ee24058Sjason 	struct {
2663ee24058Sjason 		u_int	:2;		/* 10 or 11 */
2673ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2683ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
2693ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
2703ee24058Sjason 		u_int	i_i:1;		/* immediate vs asi */
2713ee24058Sjason 		u_int	i_asi:8;	/* asi */
2723ee24058Sjason 		u_int	i_rs2:5;	/* source register 2 */
2733ee24058Sjason 	} i_asi;
2743ee24058Sjason 	struct {
2753ee24058Sjason 		u_int	:2;		/* 10 only (register, no memory) */
2763ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2773ee24058Sjason 		u_int	i_op3:6;	/* second-level decode (see IOP3_reg) */
2783ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
2793ee24058Sjason 		u_int	i_opf:9;	/* coprocessor 3rd-level decode */
2803ee24058Sjason 		u_int	i_rs2:5;	/* source register 2 */
2813ee24058Sjason 	} i_opf;
2823ee24058Sjason 
2833ee24058Sjason 	/*
2843ee24058Sjason 	 * Format 4 instructions (movcc, fmovr, fmovcc, and tcc).  The
2853ee24058Sjason 	 * second-level decode almost always makes use of an `rd' and either
2863ee24058Sjason 	 * `rs1' or `cond'.
2873ee24058Sjason 	 *
2883ee24058Sjason 	 * Beyond that, the low 14 bits may be broken up in one of three
2893ee24058Sjason 	 * different ways, if at all:
2903ee24058Sjason 	 *	1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem]
2913ee24058Sjason 	 *	1 bit of imm=1 + 13 bits of signed immediate [reg & mem]
2923ee24058Sjason 	 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] */
2933ee24058Sjason 	struct {
2943ee24058Sjason 		u_int	:2;		/* 10 */
2953ee24058Sjason 		u_int	i_rd:5;		/* destination register */
2963ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
2973ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
2983ee24058Sjason 		u_int	i_low14:14;	/* varies */
2993ee24058Sjason 	} i_op4;
3003ee24058Sjason 
3013ee24058Sjason 	/*
3023ee24058Sjason 	 * Move fp register on condition codes.
3033ee24058Sjason 	 */
3043ee24058Sjason 	struct {
3053ee24058Sjason 		u_int	:2;		/* 10 */
3063ee24058Sjason 		u_int	i_rd:5;		/* destination register */
3073ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
3083ee24058Sjason 		u_int	:1;
3093ee24058Sjason 		u_int	i_cond:4;	/* condition */
3103ee24058Sjason 		u_int	i_opf_cc:3;	/* condition code register */
3113ee24058Sjason 		u_int	i_opf_low:6;	/* third level decode */
3123ee24058Sjason 		u_int	i_rs2:5;	/* source register */
3133ee24058Sjason 	} i_fmovcc;
3143ee24058Sjason 
3153ee24058Sjason 	/*
3163ee24058Sjason 	 * Move fp register on integer register.
3173ee24058Sjason 	 */
3183ee24058Sjason 	struct {
3193ee24058Sjason 		u_int	:2;		/* 10 */
3203ee24058Sjason 		u_int	i_rd:5;		/* destination register */
3213ee24058Sjason 		u_int	i_op3:6;	/* second-level decode */
3223ee24058Sjason 		u_int	i_rs1:5;	/* source register 1 */
3233ee24058Sjason 		u_int	:1;
3243ee24058Sjason 		u_int	i_rcond:3;	/* register condition */
3253ee24058Sjason 		u_int	i_opf_low:6;
3263ee24058Sjason 		u_int	i_rs2:5;	/* source register 2 */
3273ee24058Sjason 	} i_fmovr;
3283ee24058Sjason 
3293ee24058Sjason };
3303ee24058Sjason 
3313ee24058Sjason /*
3323ee24058Sjason  * Internal macros for building instructions.  These correspond 1-to-1 to
3333ee24058Sjason  * the names above.  Note that x << y | z == (x << y) | z.
3343ee24058Sjason  */
3353ee24058Sjason #define	_I_ANY(op, b)	((op) << 30 | (b))
3363ee24058Sjason 
3373ee24058Sjason #define	_I_OP2(high, op2, low) \
3383ee24058Sjason 		_I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low))
3393ee24058Sjason #define	_I_IMM22(rd, op2, imm) \
3403ee24058Sjason 		_I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm))
3413ee24058Sjason #define	_I_BRANCH(a, c, op2, disp) \
3423ee24058Sjason 		_I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp))
3433ee24058Sjason #define	_I_FBFCC(a, cond, disp) \
3443ee24058Sjason 		_I_BRANCH(a, cond, IOP2_FBfcc, disp)
3453ee24058Sjason #define	_I_CBCCC(a, cond, disp) \
3463ee24058Sjason 		_I_BRANCH(a, cond, IOP2_CBccc, disp)
3473ee24058Sjason 
3483ee24058Sjason #define	_I_SIMM(simm)		(1 << 13 | ((simm) & 0x1fff))
3493ee24058Sjason 
3503ee24058Sjason #define	_I_OP3_GEN(form, rd, op3, rs1, low14) \
3513ee24058Sjason 		_I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14))
3523ee24058Sjason #define	_I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \
3533ee24058Sjason 		_I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2))
3543ee24058Sjason #define	_I_OP3_LS_RI(rd, op3, rs1, simm13) \
3553ee24058Sjason 		_I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13))
3563ee24058Sjason #define	_I_OP3_LS_RR(rd, op3, rs1, rs2) \
3573ee24058Sjason 		_I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2)
3583ee24058Sjason #define	_I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \
3593ee24058Sjason 		_I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2))
3603ee24058Sjason #define	_I_OP3_R_RI(rd, op3, rs1, simm13) \
3613ee24058Sjason 		_I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13))
3623ee24058Sjason #define	_I_OP3_R_RR(rd, op3, rs1, rs2) \
3633ee24058Sjason 		_I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2)
3643ee24058Sjason 
3653ee24058Sjason #define	I_CALL(d)		_I_ANY(IOP_CALL, d)
3663ee24058Sjason #define	I_UNIMP(v)		_I_IMM22(0, IOP2_UNIMP, v)
3673ee24058Sjason #define	I_BN(a, d)		_I_BRANCH(a, Icc_N, IOP2_Bicc, d)
3683ee24058Sjason #define	I_BE(a, d)		_I_BRANCH(a, Icc_E, IOP2_Bicc, d)
3693ee24058Sjason #define	I_BZ(a, d)		_I_BRANCH(a, Icc_E, IOP2_Bicc, d)
3703ee24058Sjason #define	I_BLE(a, d)		_I_BRANCH(a, Icc_LE, IOP2_Bicc, d)
3713ee24058Sjason #define	I_BL(a, d)		_I_BRANCH(a, Icc_L, IOP2_Bicc, d)
3723ee24058Sjason #define	I_BLEU(a, d)		_I_BRANCH(a, Icc_LEU, IOP2_Bicc, d)
3733ee24058Sjason #define	I_BCS(a, d)		_I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
3743ee24058Sjason #define	I_BLU(a, d)		_I_BRANCH(a, Icc_CS, IOP2_Bicc, d)
3753ee24058Sjason #define	I_BNEG(a, d)		_I_BRANCH(a, Icc_NEG, IOP2_Bicc, d)
3763ee24058Sjason #define	I_BVS(a, d)		_I_BRANCH(a, Icc_VS, IOP2_Bicc, d)
3773ee24058Sjason #define	I_BA(a, d)		_I_BRANCH(a, Icc_A, IOP2_Bicc, d)
3783ee24058Sjason #define	I_B(a, d)		_I_BRANCH(a, Icc_A, IOP2_Bicc, d)
3793ee24058Sjason #define	I_BNE(a, d)		_I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
3803ee24058Sjason #define	I_BNZ(a, d)		_I_BRANCH(a, Icc_NE, IOP2_Bicc, d)
3813ee24058Sjason #define	I_BG(a, d)		_I_BRANCH(a, Icc_G, IOP2_Bicc, d)
3823ee24058Sjason #define	I_BGE(a, d)		_I_BRANCH(a, Icc_GE, IOP2_Bicc, d)
3833ee24058Sjason #define	I_BGU(a, d)		_I_BRANCH(a, Icc_GU, IOP2_Bicc, d)
3843ee24058Sjason #define	I_BCC(a, d)		_I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
3853ee24058Sjason #define	I_BGEU(a, d)		_I_BRANCH(a, Icc_CC, IOP2_Bicc, d)
3863ee24058Sjason #define	I_BPOS(a, d)		_I_BRANCH(a, Icc_POS, IOP2_Bicc, d)
3873ee24058Sjason #define	I_BVC(a, d)		_I_BRANCH(a, Icc_VC, IOP2_Bicc, d)
3883ee24058Sjason #define	I_SETHI(r, v)		_I_IMM22(r, 4, v)
3893ee24058Sjason 
3903ee24058Sjason #define	I_ORri(rd, rs1, imm)	_I_OP3_R_RI(rd, IOP3_OR, rs1, imm)
3913ee24058Sjason #define	I_ORrr(rd, rs1, rs2)	_I_OP3_R_RR(rd, IOP3_OR, rs1, rs2)
3923ee24058Sjason 
3933ee24058Sjason #define	I_MOVi(rd, imm)		_I_OP3_R_RI(rd, IOP3_OR, I_G0, imm)
3943ee24058Sjason #define	I_MOVr(rd, rs)		_I_OP3_R_RR(rd, IOP3_OR, I_G0, rs)
3953ee24058Sjason 
3963ee24058Sjason #define	I_RDPSR(rd)		_I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0)
3973ee24058Sjason 
3983ee24058Sjason #define	I_JMPLri(rd, rs1, imm)	_I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm)
3993ee24058Sjason #define	I_JMPLrr(rd, rs1, rs2)	_I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2)
4003ee24058Sjason 
4013ee24058Sjason /*
402a4e0ff02Sjason  * FPop values.
4033ee24058Sjason  */
404a4e0ff02Sjason 
405a4e0ff02Sjason /* These are in FPop1 space */
406a4e0ff02Sjason #define	FMOVS		0x001
407a4e0ff02Sjason #define	FMOVD		0x002
408a4e0ff02Sjason #define	FMOVQ		0x003
409a4e0ff02Sjason #define	FNEGS		0x005
410a4e0ff02Sjason #define	FNEGD		0x006
411a4e0ff02Sjason #define	FNEGQ		0x007
412a4e0ff02Sjason #define	FABSS		0x009
413a4e0ff02Sjason #define	FABSD		0x00a
414a4e0ff02Sjason #define	FABSQ		0x00b
415a4e0ff02Sjason #define	FSQRTS		0x029
416a4e0ff02Sjason #define	FSQRTD		0x02a
417a4e0ff02Sjason #define	FSQRTQ		0x02b
418a4e0ff02Sjason #define	FADDS		0x041
419a4e0ff02Sjason #define	FADDD		0x042
420a4e0ff02Sjason #define	FADDQ		0x043
421a4e0ff02Sjason #define	FSUBS		0x045
422a4e0ff02Sjason #define	FSUBD		0x046
423a4e0ff02Sjason #define	FSUBQ		0x047
424a4e0ff02Sjason #define	FMULS		0x049
425a4e0ff02Sjason #define	FMULD		0x04a
426a4e0ff02Sjason #define	FMULQ		0x04b
427a4e0ff02Sjason #define	FDIVS		0x04d
428a4e0ff02Sjason #define	FDIVD		0x04e
429a4e0ff02Sjason #define	FDIVQ		0x04f
430a4e0ff02Sjason #define	FSMULD		0x069
431a4e0ff02Sjason #define	FDMULQ		0x06e
432a4e0ff02Sjason #define	FSTOX		0x081
433a4e0ff02Sjason #define	FDTOX		0x082
434a4e0ff02Sjason #define	FQTOX		0x083
435a4e0ff02Sjason #define	FXTOS		0x084
436a4e0ff02Sjason #define	FXTOD		0x088
437a4e0ff02Sjason #define	FXTOQ		0x08c
438a4e0ff02Sjason #define	FITOS		0x0c4
439a4e0ff02Sjason #define	FDTOS		0x0c6
440a4e0ff02Sjason #define	FQTOS		0x0c7
441a4e0ff02Sjason #define	FITOD		0x0c8
442a4e0ff02Sjason #define	FSTOD		0x0c9
443a4e0ff02Sjason #define	FQTOD		0x0cb
444a4e0ff02Sjason #define	FITOQ		0x0cc
445a4e0ff02Sjason #define	FSTOQ		0x0cd
446a4e0ff02Sjason #define	FDTOQ		0x0ce
447a4e0ff02Sjason #define	FSTOI		0x0d1
448a4e0ff02Sjason #define	FDTOI		0x0d2
449a4e0ff02Sjason #define	FQTOI		0x0d3
4503ee24058Sjason 
4513ee24058Sjason /* These are in FPop2 space */
452a4e0ff02Sjason #define	FMVFC0S		0x001
453a4e0ff02Sjason #define	FMVFC0D		0x002
454a4e0ff02Sjason #define	FMVFC0Q		0x003
455a4e0ff02Sjason #define	FMOVZS		0x025
456a4e0ff02Sjason #define	FMOVZD		0x026
457a4e0ff02Sjason #define	FMOVZQ		0x027
458a4e0ff02Sjason #define	FMVFC1S		0x041
459a4e0ff02Sjason #define	FMVFC1D		0x042
460a4e0ff02Sjason #define	FMVFC1Q		0x043
461a4e0ff02Sjason #define	FMOVLEZS	0x045
462a4e0ff02Sjason #define	FMOVLEZD	0x046
463a4e0ff02Sjason #define	FMOVLEZQ	0x047
464a4e0ff02Sjason #define	FCMPS		0x051
465a4e0ff02Sjason #define	FCMPD		0x052
466a4e0ff02Sjason #define	FCMPQ		0x053
467a4e0ff02Sjason #define	FCMPES		0x055
468a4e0ff02Sjason #define	FCMPED		0x056
469a4e0ff02Sjason #define	FCMPEQ		0x057
470a4e0ff02Sjason #define	FMOVLZS		0x065
471a4e0ff02Sjason #define	FMOVLZD		0x066
472a4e0ff02Sjason #define	FMOVLZQ		0x067
473a4e0ff02Sjason #define	FMVFC2S		0x081
474a4e0ff02Sjason #define	FMVFC2D		0x082
475a4e0ff02Sjason #define	FMVFC2Q		0x083
476a4e0ff02Sjason #define	FMOVNZS		0x0a5
477a4e0ff02Sjason #define	FMOVNZD		0x0a6
478a4e0ff02Sjason #define	FMOVNZQ		0x0a7
479a4e0ff02Sjason #define	FMVFC3S		0x0c1
480a4e0ff02Sjason #define	FMVFC3D		0x0c2
481a4e0ff02Sjason #define	FMVFC3Q		0x0c3
482a4e0ff02Sjason #define	FMOVGZS		0x0c5
483a4e0ff02Sjason #define	FMOVGZD		0x0c6
484a4e0ff02Sjason #define	FMOVGZQ		0x0c7
485a4e0ff02Sjason #define	FMOVGEZS	0x0e5
486a4e0ff02Sjason #define	FMOVGEZD	0x0e6
487a4e0ff02Sjason #define	FMOVGEZQ	0x0e7
488a4e0ff02Sjason #define	FMVICS		0x101
489a4e0ff02Sjason #define	FMVICD		0x102
490a4e0ff02Sjason #define	FMVICQ		0x103
491a4e0ff02Sjason #define	FMVXCS		0x181
492a4e0ff02Sjason #define	FMVXCD		0x182
493a4e0ff02Sjason #define	FMVXCQ		0x183
4943ee24058Sjason 
4953ee24058Sjason /*
4963ee24058Sjason  * FPU data types.
4973ee24058Sjason  */
4983ee24058Sjason #define FTYPE_LNG	-1	/* data = 64-bit signed long integer */
4993ee24058Sjason #define	FTYPE_INT	0	/* data = 32-bit signed integer */
5003ee24058Sjason #define	FTYPE_SNG	1	/* data = 32-bit float */
5013ee24058Sjason #define	FTYPE_DBL	2	/* data = 64-bit double */
5023ee24058Sjason #define	FTYPE_EXT	3	/* data = 128-bit extended (quad-prec) */
503