1*bff2ef4dSjsg /* $OpenBSD: mmu.h,v 1.3 2022/02/21 12:16:55 jsg Exp $ */ 295c7671fSmiod /* $NetBSD: mmu.h,v 1.9 2006/03/04 01:55:03 uwe Exp $ */ 395c7671fSmiod 495c7671fSmiod /*- 595c7671fSmiod * Copyright (c) 2002 The NetBSD Foundation, Inc. 695c7671fSmiod * All rights reserved. 795c7671fSmiod * 895c7671fSmiod * This code is derived from software contributed to The NetBSD Foundation 995c7671fSmiod * by UCHIYAMA Yasushi. 1095c7671fSmiod * 1195c7671fSmiod * Redistribution and use in source and binary forms, with or without 1295c7671fSmiod * modification, are permitted provided that the following conditions 1395c7671fSmiod * are met: 1495c7671fSmiod * 1. Redistributions of source code must retain the above copyright 1595c7671fSmiod * notice, this list of conditions and the following disclaimer. 1695c7671fSmiod * 2. Redistributions in binary form must reproduce the above copyright 1795c7671fSmiod * notice, this list of conditions and the following disclaimer in the 1895c7671fSmiod * documentation and/or other materials provided with the distribution. 1995c7671fSmiod * 2095c7671fSmiod * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2195c7671fSmiod * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2295c7671fSmiod * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2395c7671fSmiod * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2495c7671fSmiod * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2595c7671fSmiod * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2695c7671fSmiod * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2795c7671fSmiod * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2895c7671fSmiod * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2995c7671fSmiod * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3095c7671fSmiod * POSSIBILITY OF SUCH DAMAGE. 3195c7671fSmiod */ 3295c7671fSmiod 3395c7671fSmiod #ifndef _SH_MMU_H_ 3495c7671fSmiod #define _SH_MMU_H_ 3595c7671fSmiod 3695c7671fSmiod /* 3795c7671fSmiod * Initialize routines. 3895c7671fSmiod * sh_mmu_init Assign function vector. Don't access hardware. 3995c7671fSmiod * Call as early as possible. 4095c7671fSmiod * sh_mmu_start Reset TLB entry, set default ASID, and start to 4195c7671fSmiod * translate addresses. 4295c7671fSmiod * Call after exception vector was installed. 4395c7671fSmiod * 4495c7671fSmiod * TLB access ops. 45*bff2ef4dSjsg * sh_tlb_invalidate_addr invalidate TLB entries for given 4695c7671fSmiod * virtual addr with ASID. 4795c7671fSmiod * sh_tlb_invalidate_asid invalidate TLB entries for given ASID. 4895c7671fSmiod * sh_tlb_invalidate_all invalidate all non-wired TLB entries. 4995c7671fSmiod * sh_tlb_set_asid set ASID. 5095c7671fSmiod * sh_tlb_update load new PTE to TLB. 5195c7671fSmiod * 5295c7671fSmiod */ 5395c7671fSmiod 5495c7671fSmiod void sh_mmu_init(void); 5595c7671fSmiod void sh_mmu_information(void); 5695c7671fSmiod void sh_tlb_set_asid(int); 5795c7671fSmiod 5895c7671fSmiod #ifdef SH3 5995c7671fSmiod void sh3_mmu_start(void); 6095c7671fSmiod void sh3_tlb_invalidate_addr(int, vaddr_t); 6195c7671fSmiod void sh3_tlb_invalidate_asid(int); 6295c7671fSmiod void sh3_tlb_invalidate_all(void); 6395c7671fSmiod void sh3_tlb_update(int, vaddr_t, uint32_t); 6495c7671fSmiod #endif 6595c7671fSmiod 6695c7671fSmiod #ifdef SH4 6795c7671fSmiod void sh4_mmu_start(void); 6895c7671fSmiod void sh4_tlb_invalidate_addr(int, vaddr_t); 6995c7671fSmiod void sh4_tlb_invalidate_asid(int); 7095c7671fSmiod void sh4_tlb_invalidate_all(void); 7195c7671fSmiod void sh4_tlb_update(int, vaddr_t, uint32_t); 7295c7671fSmiod #endif 7395c7671fSmiod 7495c7671fSmiod 7595c7671fSmiod #if defined(SH3) && defined(SH4) 7695c7671fSmiod extern uint32_t __sh_PTEH; 7795c7671fSmiod 7895c7671fSmiod extern void (*__sh_mmu_start)(void); 7995c7671fSmiod extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t); 8095c7671fSmiod extern void (*__sh_tlb_invalidate_asid)(int); 8195c7671fSmiod extern void (*__sh_tlb_invalidate_all)(void); 8295c7671fSmiod extern void (*__sh_tlb_update)(int, vaddr_t, uint32_t); 8395c7671fSmiod 8495c7671fSmiod #define sh_mmu_start() (*__sh_mmu_start)() 8595c7671fSmiod #define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va) 8695c7671fSmiod #define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a) 8795c7671fSmiod #define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)() 8895c7671fSmiod #define sh_tlb_update(a, va, pte) (*__sh_tlb_update)(a, va, pte) 8995c7671fSmiod 9095c7671fSmiod #elif defined(SH3) 9195c7671fSmiod 9295c7671fSmiod #define sh_mmu_start() sh3_mmu_start() 9395c7671fSmiod #define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va) 9495c7671fSmiod #define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a) 9595c7671fSmiod #define sh_tlb_invalidate_all() sh3_tlb_invalidate_all() 9695c7671fSmiod #define sh_tlb_update(a, va, pte) sh3_tlb_update(a, va, pte) 9795c7671fSmiod 9895c7671fSmiod #elif defined(SH4) 9995c7671fSmiod 10095c7671fSmiod #define sh_mmu_start() sh4_mmu_start() 10195c7671fSmiod #define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va) 10295c7671fSmiod #define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a) 10395c7671fSmiod #define sh_tlb_invalidate_all() sh4_tlb_invalidate_all() 10495c7671fSmiod #define sh_tlb_update(a, va, pte) sh4_tlb_update(a, va, pte) 10595c7671fSmiod 10695c7671fSmiod #endif 10795c7671fSmiod 10895c7671fSmiod #endif /* !_SH_MMU_H_ */ 109