1*fe5dbe47Sjmatthew /* $OpenBSD: octuctlreg.h,v 1.2 2017/07/25 11:01:28 jmatthew Exp $ */ 2494889e9Sjmatthew 3494889e9Sjmatthew /* 4494889e9Sjmatthew * Copyright (c) 2015 Jonathan Matthew <jmatthew@openbsd.org> 5494889e9Sjmatthew * 6494889e9Sjmatthew * Permission to use, copy, modify, and/or distribute this software for any 7494889e9Sjmatthew * purpose with or without fee is hereby granted, provided that the above 8494889e9Sjmatthew * copyright notice and this permission notice appear in all copies. 9494889e9Sjmatthew * 10494889e9Sjmatthew * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11494889e9Sjmatthew * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12494889e9Sjmatthew * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13494889e9Sjmatthew * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14494889e9Sjmatthew * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15494889e9Sjmatthew * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16494889e9Sjmatthew * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17494889e9Sjmatthew */ 18494889e9Sjmatthew 19494889e9Sjmatthew #ifndef _OCTUCTLREG_H_ 20494889e9Sjmatthew #define _OCTUCTLREG_H_ 21494889e9Sjmatthew 22494889e9Sjmatthew /* 23494889e9Sjmatthew * UCTL - octeon II usb controller interface 24494889e9Sjmatthew */ 25494889e9Sjmatthew 26494889e9Sjmatthew #define UCTL_CLK_TARGET_FREQ 130000000ull 27494889e9Sjmatthew 28494889e9Sjmatthew #define UCTL_CLK_RST_CTL 0x00 29494889e9Sjmatthew #define UCTL_CLK_RST_CTL_HRST (1 << 0) 30494889e9Sjmatthew #define UCTL_CLK_RST_CTL_P_PRST (1 << 1) 31494889e9Sjmatthew #define UCTL_CLK_RST_CTL_P_POR (1 << 2) 32494889e9Sjmatthew #define UCTL_CLK_RST_CTL_P_COM_ON (1 << 3) 33494889e9Sjmatthew #define UCTL_CLK_RST_CTL_P_REFCLK_DIV_SHIFT 5 34494889e9Sjmatthew #define UCTL_CLK_RST_CTL_P_REFCLK_SEL_SHIFT 7 35494889e9Sjmatthew #define UCTL_CLK_RST_CTL_H_DIV_SHIFT 9 36494889e9Sjmatthew #define UCTL_CLK_RST_CTL_O_CLKDIV_EN (1 << 13) 37494889e9Sjmatthew #define UCTL_CLK_RST_CTL_H_CLKDIV_EN (1 << 14) 38494889e9Sjmatthew #define UCTL_CLK_RST_CTL_H_CLKDIV_RST (1 << 15) 39494889e9Sjmatthew #define UCTL_CLK_RST_CTL_H_CLKDIV_BYP (1 << 16) 40494889e9Sjmatthew #define UCTL_CLK_RST_CTL_O_CLKDIV_RST (1 << 17) 41494889e9Sjmatthew #define UCTL_CLK_RST_CTL_APP_START_CLK (1 << 18) 42494889e9Sjmatthew #define UCTL_CLK_RST_CTL_OHCI_SUSP_LGCY (1 << 19) 43494889e9Sjmatthew #define UCTL_CLK_RST_CTL_OHCI_SM (1 << 20) 44494889e9Sjmatthew #define UCTL_CLK_RST_CTL_OHCI_CLKCKTRST (1 << 21) 45494889e9Sjmatthew #define UCTL_CLK_RST_CTL_EHCI_SM (1 << 22) 46494889e9Sjmatthew 47494889e9Sjmatthew #define UCTL_UPHY_STATUS 0x08 48494889e9Sjmatthew 49494889e9Sjmatthew #define UCTL_UPHY_PORTX_STATUS 0x10 50494889e9Sjmatthew #define UCTL_UPHY_PORTX_STATUS_TXVREF_SHIFT 28 51494889e9Sjmatthew #define UCTL_UPHY_PORTX_STATUS_TXRISETUNE (1 << 27) 52494889e9Sjmatthew #define UCTL_UPHY_PORTX_STATUS_TXPREEMPHTUNE (1 << 26) 53494889e9Sjmatthew 54494889e9Sjmatthew #define UCTL_IF_ENA 0x30 55494889e9Sjmatthew #define UCTL_IF_ENA_EN (1 << 0) 56494889e9Sjmatthew 57494889e9Sjmatthew #define UCTL_EHCI_CTL 0x80 58494889e9Sjmatthew #define UCTL_EHCI_CTL_L2C_ADDR_MSB_MASK 0xff 59494889e9Sjmatthew #define UCTL_EHCI_CTL_L2C_ADDR_MSB_SHIFT 0 60494889e9Sjmatthew #define UCTL_EHCI_CTL_EHCI_64B_ADDR_EN (1 << 8) 61494889e9Sjmatthew #define UCTL_EHCI_CTL_L2C_DESC_EMOD_SHIFT 10 62494889e9Sjmatthew #define UCTL_EHCI_CTL_L2C_BUFF_EMOD_SHIFT 12 63494889e9Sjmatthew 64494889e9Sjmatthew #define UCTL_OHCI_CTL 0x88 65494889e9Sjmatthew #define UCTL_OHCI_CTL_L2C_ADDR_MSB_MASK 0xff 66494889e9Sjmatthew #define UCTL_OHCI_CTL_L2C_ADDR_MSB_SHIFT 0 67494889e9Sjmatthew #define UCTL_OHCI_CTL_L2C_DESC_EMOD_SHIFT 10 68494889e9Sjmatthew #define UCTL_OHCI_CTL_L2C_BUFF_EMOD_SHIFT 12 69494889e9Sjmatthew 70494889e9Sjmatthew #endif /* _OCTUCTLREG_H_ */ 71