xref: /openbsd-src/sys/arch/m88k/include/psl.h (revision 4001e0267b425b010c4f08af94b603f7a275b867)
1*4001e026Smiod /*	$OpenBSD: psl.h,v 1.8 2013/05/17 22:28:21 miod Exp $ */
23180e169Smiod /*
33180e169Smiod  * Copyright (c) 1996 Nivas Madhur
43180e169Smiod  * All rights reserved.
53180e169Smiod  *
63180e169Smiod  * Redistribution and use in source and binary forms, with or without
73180e169Smiod  * modification, are permitted provided that the following conditions
83180e169Smiod  * are met:
93180e169Smiod  * 1. Redistributions of source code must retain the above copyright
103180e169Smiod  *    notice, this list of conditions and the following disclaimer.
113180e169Smiod  * 2. Redistributions in binary form must reproduce the above copyright
123180e169Smiod  *    notice, this list of conditions and the following disclaimer in the
133180e169Smiod  *    documentation and/or other materials provided with the distribution.
143180e169Smiod  * 3. All advertising materials mentioning features or use of this software
153180e169Smiod  *    must display the following acknowledgement:
163180e169Smiod  *      This product includes software developed by Nivas Madhur.
173180e169Smiod  * 4. The name of the author may not be used to endorse or promote products
183180e169Smiod  *    derived from this software without specific prior written permission
193180e169Smiod  *
203180e169Smiod  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
213180e169Smiod  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
223180e169Smiod  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
233180e169Smiod  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
243180e169Smiod  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
253180e169Smiod  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
263180e169Smiod  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
273180e169Smiod  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
283180e169Smiod  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
293180e169Smiod  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
303180e169Smiod  *
313180e169Smiod  */
323180e169Smiod /*
333180e169Smiod  * Mach Operating System
343180e169Smiod  * Copyright (c) 1991 Carnegie Mellon University
353180e169Smiod  * Copyright (c) 1991 OMRON Corporation
363180e169Smiod  * All Rights Reserved.
373180e169Smiod  *
383180e169Smiod  * Permission to use, copy, modify and distribute this software and its
393180e169Smiod  * documentation is hereby granted, provided that both the copyright
403180e169Smiod  * notice and this permission notice appear in all copies of the
413180e169Smiod  * software, derivative works or modified versions, and any portions
423180e169Smiod  * thereof, and that both notices appear in supporting documentation.
433180e169Smiod  *
443180e169Smiod  */
453180e169Smiod 
462fa72412Spirofti #ifndef _M88K_PSL_H_
472fa72412Spirofti #define _M88K_PSL_H_
483180e169Smiod 
493180e169Smiod /*
50fbfa4346Smiod  * 881x0 control registers
513180e169Smiod  */
523180e169Smiod 
533180e169Smiod /*
543180e169Smiod  * processor identification register (PID)
553180e169Smiod  */
567e3026a6Smiod #define PID_ARN		0x0000ff00	/* architectural revision number */
5720236a35Smiod #define	ARN_SHIFT		8
5820236a35Smiod #define	ARN_88100		0x00
5920236a35Smiod #define	ARN_88110		0x01
607e3026a6Smiod #define PID_VN		0x000000fe	/* version number */
6120236a35Smiod #define	VN_SHIFT		1
627e3026a6Smiod #define PID_MC		0x00000001	/* 88100 master/checker mode */
633180e169Smiod 
643180e169Smiod /*
653180e169Smiod  * processor status register
663180e169Smiod  */
673180e169Smiod 
687e3026a6Smiod #define PSR_MODE	0x80000000	/* supervisor/user mode */
697e3026a6Smiod #define PSR_BO		0x40000000	/* byte-ordering 0:big 1:little */
70*4001e026Smiod #define PSR_SER		0x20000000	/* serial mode */
717e3026a6Smiod #define PSR_C		0x10000000	/* carry */
727e3026a6Smiod #define PSR_SGN		0x04000000	/* 88110 Signed Immediate mode */
737e3026a6Smiod #define PSR_SRM		0x02000000	/* 88110 Serialize Memory */
747e3026a6Smiod #define PSR_TRACE	0x00800000	/* 88110 hardware trace */
757e3026a6Smiod #define PSR_SFD		0x000003e0	/* SFU disable */
767e3026a6Smiod #define PSR_SFD2	0x00000010	/* 88110 SFU2 (Graphics) disable */
777e3026a6Smiod #define PSR_SFD1	0x00000008	/* SFU1 (FPU) disable */
787e3026a6Smiod #define PSR_MXM		0x00000004	/* misaligned access enable */
797e3026a6Smiod #define PSR_IND		0x00000002	/* interrupt disable */
807e3026a6Smiod #define PSR_SFRZ	0x00000001	/* shadow freeze */
813180e169Smiod 
82910f2c06Smiod /* bits userland is not allowed to change */
83*4001e026Smiod #define	PSR_USERSTATIC	(PSR_MODE | PSR_BO | PSR_SER | PSR_SGN | PSR_SRM | \
84*4001e026Smiod 			 PSR_SFD | PSR_MXM | PSR_IND | PSR_SFRZ)
85910f2c06Smiod 
867e3026a6Smiod #define FIP_V		0x00000002	/* valid */
877e3026a6Smiod #define FIP_E		0x00000001	/* exception */
887e3026a6Smiod #define FIP_ADDR	0xfffffffc	/* address mask */
897e3026a6Smiod #define NIP_V		0x00000002	/* valid */
907e3026a6Smiod #define NIP_E		0x00000001	/* exception */
917e3026a6Smiod #define NIP_ADDR	0xfffffffc	/* address mask */
927e3026a6Smiod #define XIP_V		0x00000002	/* valid */
937e3026a6Smiod #define XIP_E		0x00000001	/* exception */
947e3026a6Smiod #define XIP_ADDR	0xfffffffc	/* address mask */
953180e169Smiod 
962fa72412Spirofti #endif /* _M88K_PSL_H_ */
97