1*b58fb0baSjsg /* $OpenBSD: sysreg.h,v 1.1 2016/04/25 04:25:36 jsg Exp $ */ 2*b58fb0baSjsg /*- 3*b58fb0baSjsg * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 4*b58fb0baSjsg * Copyright 2014 Michal Meloun <meloun@miracle.cz> 5*b58fb0baSjsg * All rights reserved. 6*b58fb0baSjsg * 7*b58fb0baSjsg * Redistribution and use in source and binary forms, with or without 8*b58fb0baSjsg * modification, are permitted provided that the following conditions 9*b58fb0baSjsg * are met: 10*b58fb0baSjsg * 1. Redistributions of source code must retain the above copyright 11*b58fb0baSjsg * notice, this list of conditions and the following disclaimer. 12*b58fb0baSjsg * 2. Redistributions in binary form must reproduce the above copyright 13*b58fb0baSjsg * notice, this list of conditions and the following disclaimer in the 14*b58fb0baSjsg * documentation and/or other materials provided with the distribution. 15*b58fb0baSjsg * 16*b58fb0baSjsg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17*b58fb0baSjsg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18*b58fb0baSjsg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19*b58fb0baSjsg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20*b58fb0baSjsg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21*b58fb0baSjsg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22*b58fb0baSjsg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23*b58fb0baSjsg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24*b58fb0baSjsg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25*b58fb0baSjsg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26*b58fb0baSjsg * SUCH DAMAGE. 27*b58fb0baSjsg * 28*b58fb0baSjsg * $FreeBSD: head/sys/arm/include/sysreg.h 294740 2016-01-25 18:02:28Z zbb $ 29*b58fb0baSjsg */ 30*b58fb0baSjsg 31*b58fb0baSjsg /* 32*b58fb0baSjsg * Macros to make working with the System Control Registers simpler. 33*b58fb0baSjsg * 34*b58fb0baSjsg * Note that when register r0 is hard-coded in these definitions it means the 35*b58fb0baSjsg * cp15 operation neither reads nor writes the register, and r0 is used only 36*b58fb0baSjsg * because some syntatically-valid register name has to appear at that point to 37*b58fb0baSjsg * keep the asm parser happy. 38*b58fb0baSjsg */ 39*b58fb0baSjsg 40*b58fb0baSjsg #ifndef MACHINE_SYSREG_H 41*b58fb0baSjsg #define MACHINE_SYSREG_H 42*b58fb0baSjsg 43*b58fb0baSjsg /* 44*b58fb0baSjsg * CP14 registers 45*b58fb0baSjsg */ 46*b58fb0baSjsg 47*b58fb0baSjsg #define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ 48*b58fb0baSjsg #define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ 49*b58fb0baSjsg #define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ 50*b58fb0baSjsg #define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ 51*b58fb0baSjsg #define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ 52*b58fb0baSjsg #define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ 53*b58fb0baSjsg #define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ 54*b58fb0baSjsg #define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ 55*b58fb0baSjsg 56*b58fb0baSjsg #define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ 57*b58fb0baSjsg 58*b58fb0baSjsg 59*b58fb0baSjsg /* 60*b58fb0baSjsg * CP15 C0 registers 61*b58fb0baSjsg */ 62*b58fb0baSjsg #define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 63*b58fb0baSjsg #define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 64*b58fb0baSjsg #define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 65*b58fb0baSjsg #define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 66*b58fb0baSjsg #define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 67*b58fb0baSjsg #define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ 68*b58fb0baSjsg 69*b58fb0baSjsg #define CP15_ID_PFR0(rr) p15, 0, rr, c0, c1, 0 /* Processor Feature Register 0 */ 70*b58fb0baSjsg #define CP15_ID_PFR1(rr) p15, 0, rr, c0, c1, 1 /* Processor Feature Register 1 */ 71*b58fb0baSjsg #define CP15_ID_DFR0(rr) p15, 0, rr, c0, c1, 2 /* Debug Feature Register 0 */ 72*b58fb0baSjsg #define CP15_ID_AFR0(rr) p15, 0, rr, c0, c1, 3 /* Auxiliary Feature Register 0 */ 73*b58fb0baSjsg #define CP15_ID_MMFR0(rr) p15, 0, rr, c0, c1, 4 /* Memory Model Feature Register 0 */ 74*b58fb0baSjsg #define CP15_ID_MMFR1(rr) p15, 0, rr, c0, c1, 5 /* Memory Model Feature Register 1 */ 75*b58fb0baSjsg #define CP15_ID_MMFR2(rr) p15, 0, rr, c0, c1, 6 /* Memory Model Feature Register 2 */ 76*b58fb0baSjsg #define CP15_ID_MMFR3(rr) p15, 0, rr, c0, c1, 7 /* Memory Model Feature Register 3 */ 77*b58fb0baSjsg 78*b58fb0baSjsg #define CP15_ID_ISAR0(rr) p15, 0, rr, c0, c2, 0 /* Instruction Set Attribute Register 0 */ 79*b58fb0baSjsg #define CP15_ID_ISAR1(rr) p15, 0, rr, c0, c2, 1 /* Instruction Set Attribute Register 1 */ 80*b58fb0baSjsg #define CP15_ID_ISAR2(rr) p15, 0, rr, c0, c2, 2 /* Instruction Set Attribute Register 2 */ 81*b58fb0baSjsg #define CP15_ID_ISAR3(rr) p15, 0, rr, c0, c2, 3 /* Instruction Set Attribute Register 3 */ 82*b58fb0baSjsg #define CP15_ID_ISAR4(rr) p15, 0, rr, c0, c2, 4 /* Instruction Set Attribute Register 4 */ 83*b58fb0baSjsg #define CP15_ID_ISAR5(rr) p15, 0, rr, c0, c2, 5 /* Instruction Set Attribute Register 5 */ 84*b58fb0baSjsg 85*b58fb0baSjsg #define CP15_CCSIDR(rr) p15, 1, rr, c0, c0, 0 /* Cache Size ID Registers */ 86*b58fb0baSjsg #define CP15_CLIDR(rr) p15, 1, rr, c0, c0, 1 /* Cache Level ID Register */ 87*b58fb0baSjsg #define CP15_AIDR(rr) p15, 1, rr, c0, c0, 7 /* Auxiliary ID Register */ 88*b58fb0baSjsg 89*b58fb0baSjsg #define CP15_CSSELR(rr) p15, 2, rr, c0, c0, 0 /* Cache Size Selection Register */ 90*b58fb0baSjsg 91*b58fb0baSjsg /* 92*b58fb0baSjsg * CP15 C1 registers 93*b58fb0baSjsg */ 94*b58fb0baSjsg #define CP15_SCTLR(rr) p15, 0, rr, c1, c0, 0 /* System Control Register */ 95*b58fb0baSjsg #define CP15_ACTLR(rr) p15, 0, rr, c1, c0, 1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */ 96*b58fb0baSjsg #define CP15_CPACR(rr) p15, 0, rr, c1, c0, 2 /* Coprocessor Access Control Register */ 97*b58fb0baSjsg 98*b58fb0baSjsg #define CP15_SCR(rr) p15, 0, rr, c1, c1, 0 /* Secure Configuration Register */ 99*b58fb0baSjsg #define CP15_SDER(rr) p15, 0, rr, c1, c1, 1 /* Secure Debug Enable Register */ 100*b58fb0baSjsg #define CP15_NSACR(rr) p15, 0, rr, c1, c1, 2 /* Non-Secure Access Control Register */ 101*b58fb0baSjsg 102*b58fb0baSjsg /* 103*b58fb0baSjsg * CP15 C2 registers 104*b58fb0baSjsg */ 105*b58fb0baSjsg #define CP15_TTBR0(rr) p15, 0, rr, c2, c0, 0 /* Translation Table Base Register 0 */ 106*b58fb0baSjsg #define CP15_TTBR1(rr) p15, 0, rr, c2, c0, 1 /* Translation Table Base Register 1 */ 107*b58fb0baSjsg #define CP15_TTBCR(rr) p15, 0, rr, c2, c0, 2 /* Translation Table Base Control Register */ 108*b58fb0baSjsg 109*b58fb0baSjsg /* 110*b58fb0baSjsg * CP15 C3 registers 111*b58fb0baSjsg */ 112*b58fb0baSjsg #define CP15_DACR(rr) p15, 0, rr, c3, c0, 0 /* Domain Access Control Register */ 113*b58fb0baSjsg 114*b58fb0baSjsg /* 115*b58fb0baSjsg * CP15 C5 registers 116*b58fb0baSjsg */ 117*b58fb0baSjsg #define CP15_DFSR(rr) p15, 0, rr, c5, c0, 0 /* Data Fault Status Register */ 118*b58fb0baSjsg 119*b58fb0baSjsg /* From ARMv6: */ 120*b58fb0baSjsg #define CP15_IFSR(rr) p15, 0, rr, c5, c0, 1 /* Instruction Fault Status Register */ 121*b58fb0baSjsg /* From ARMv7: */ 122*b58fb0baSjsg #define CP15_ADFSR(rr) p15, 0, rr, c5, c1, 0 /* Auxiliary Data Fault Status Register */ 123*b58fb0baSjsg #define CP15_AIFSR(rr) p15, 0, rr, c5, c1, 1 /* Auxiliary Instruction Fault Status Register */ 124*b58fb0baSjsg 125*b58fb0baSjsg /* 126*b58fb0baSjsg * CP15 C6 registers 127*b58fb0baSjsg */ 128*b58fb0baSjsg #define CP15_DFAR(rr) p15, 0, rr, c6, c0, 0 /* Data Fault Address Register */ 129*b58fb0baSjsg 130*b58fb0baSjsg /* From ARMv6k: */ 131*b58fb0baSjsg #define CP15_IFAR(rr) p15, 0, rr, c6, c0, 2 /* Instruction Fault Address Register */ 132*b58fb0baSjsg 133*b58fb0baSjsg /* 134*b58fb0baSjsg * CP15 C7 registers 135*b58fb0baSjsg */ 136*b58fb0baSjsg #ifdef MULTIPROCESSOR 137*b58fb0baSjsg /* From ARMv7: */ 138*b58fb0baSjsg #define CP15_ICIALLUIS p15, 0, r0, c7, c1, 0 /* Instruction cache invalidate all PoU, IS */ 139*b58fb0baSjsg #define CP15_BPIALLIS p15, 0, r0, c7, c1, 6 /* Branch predictor invalidate all IS */ 140*b58fb0baSjsg #endif 141*b58fb0baSjsg 142*b58fb0baSjsg #define CP15_PAR(rr) p15, 0, rr, c7, c4, 0 /* Physical Address Register */ 143*b58fb0baSjsg 144*b58fb0baSjsg #define CP15_ICIALLU p15, 0, r0, c7, c5, 0 /* Instruction cache invalidate all PoU */ 145*b58fb0baSjsg #define CP15_ICIMVAU(rr) p15, 0, rr, c7, c5, 1 /* Instruction cache invalidate */ 146*b58fb0baSjsg #define CP15_BPIALL p15, 0, r0, c7, c5, 6 /* Branch predictor invalidate all */ 147*b58fb0baSjsg #define CP15_BPIMVA p15, 0, r0, c7, c5, 7 /* Branch predictor invalidate by MVA */ 148*b58fb0baSjsg 149*b58fb0baSjsg #define CP15_DCIMVAC(rr) p15, 0, rr, c7, c6, 1 /* Data cache invalidate by MVA PoC */ 150*b58fb0baSjsg #define CP15_DCISW(rr) p15, 0, rr, c7, c6, 2 /* Data cache invalidate by set/way */ 151*b58fb0baSjsg 152*b58fb0baSjsg #define CP15_ATS1CPR(rr) p15, 0, rr, c7, c8, 0 /* Stage 1 Current state PL1 read */ 153*b58fb0baSjsg #define CP15_ATS1CPW(rr) p15, 0, rr, c7, c8, 1 /* Stage 1 Current state PL1 write */ 154*b58fb0baSjsg #define CP15_ATS1CUR(rr) p15, 0, rr, c7, c8, 2 /* Stage 1 Current state unprivileged read */ 155*b58fb0baSjsg #define CP15_ATS1CUW(rr) p15, 0, rr, c7, c8, 3 /* Stage 1 Current state unprivileged write */ 156*b58fb0baSjsg 157*b58fb0baSjsg /* From ARMv7: */ 158*b58fb0baSjsg #define CP15_ATS12NSOPR(rr) p15, 0, rr, c7, c8, 4 /* Stages 1 and 2 Non-secure only PL1 read */ 159*b58fb0baSjsg #define CP15_ATS12NSOPW(rr) p15, 0, rr, c7, c8, 5 /* Stages 1 and 2 Non-secure only PL1 write */ 160*b58fb0baSjsg #define CP15_ATS12NSOUR(rr) p15, 0, rr, c7, c8, 6 /* Stages 1 and 2 Non-secure only unprivileged read */ 161*b58fb0baSjsg #define CP15_ATS12NSOUW(rr) p15, 0, rr, c7, c8, 7 /* Stages 1 and 2 Non-secure only unprivileged write */ 162*b58fb0baSjsg 163*b58fb0baSjsg #define CP15_DCCMVAC(rr) p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */ 164*b58fb0baSjsg #define CP15_DCCSW(rr) p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */ 165*b58fb0baSjsg 166*b58fb0baSjsg #define CP15_CP15DSB(rr) p15, 0, rr, c7, c10, 4 167*b58fb0baSjsg #define CP15_CP15DMB(rr) p15, 0, rr, c7, c10, 5 168*b58fb0baSjsg 169*b58fb0baSjsg /* From ARMv7: */ 170*b58fb0baSjsg #define CP15_DCCMVAU(rr) p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */ 171*b58fb0baSjsg 172*b58fb0baSjsg #define CP15_DCCIMVAC(rr) p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */ 173*b58fb0baSjsg #define CP15_DCCISW(rr) p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */ 174*b58fb0baSjsg 175*b58fb0baSjsg /* 176*b58fb0baSjsg * CP15 C8 registers 177*b58fb0baSjsg */ 178*b58fb0baSjsg #ifdef MULTIPROCESSOR 179*b58fb0baSjsg /* From ARMv7: */ 180*b58fb0baSjsg #define CP15_TLBIALLIS p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */ 181*b58fb0baSjsg #define CP15_TLBIMVAIS(rr) p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */ 182*b58fb0baSjsg #define CP15_TLBIASIDIS(rr) p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */ 183*b58fb0baSjsg #define CP15_TLBIMVAAIS(rr) p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */ 184*b58fb0baSjsg #endif 185*b58fb0baSjsg 186*b58fb0baSjsg #define CP15_DTLBIALL p15, 0, r0, c8, c6, 0 /* flush D tlb */ 187*b58fb0baSjsg #define CP15_DTLBIMVA p15, 0, r0, c8, c6, 1 /* Invalidate D TLB by MVA */ 188*b58fb0baSjsg #define CP15_ITLBIALL p15, 0, r0, c8, c5, 0 /* flush I tlb */ 189*b58fb0baSjsg #define CP15_ITLBIMVA p15, 0, r0, c8, c5, 1 /* Invalidate I TLB by MVA */ 190*b58fb0baSjsg 191*b58fb0baSjsg #define CP15_TLBIALL(rr) p15, 0, rr, c8, c7, 0 /* Invalidate entire unified TLB */ 192*b58fb0baSjsg #define CP15_TLBIMVA(rr) p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */ 193*b58fb0baSjsg #define CP15_TLBIASID(rr) p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */ 194*b58fb0baSjsg 195*b58fb0baSjsg /* From ARMv6: */ 196*b58fb0baSjsg #define CP15_TLBIMVAA(rr) p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */ 197*b58fb0baSjsg 198*b58fb0baSjsg /* 199*b58fb0baSjsg * CP15 C9 registers 200*b58fb0baSjsg */ 201*b58fb0baSjsg #define CP15_L2CTLR(rr) p15, 1, rr, c9, c0, 2 /* L2 Control Register */ 202*b58fb0baSjsg #define CP15_PMCR(rr) p15, 0, rr, c9, c12, 0 /* Performance Monitor Control Register */ 203*b58fb0baSjsg #define CP15_PMCNTENSET(rr) p15, 0, rr, c9, c12, 1 /* PM Count Enable Set Register */ 204*b58fb0baSjsg #define CP15_PMCNTENCLR(rr) p15, 0, rr, c9, c12, 2 /* PM Count Enable Clear Register */ 205*b58fb0baSjsg #define CP15_PMOVSR(rr) p15, 0, rr, c9, c12, 3 /* PM Overflow Flag Status Register */ 206*b58fb0baSjsg #define CP15_PMSWINC(rr) p15, 0, rr, c9, c12, 4 /* PM Software Increment Register */ 207*b58fb0baSjsg #define CP15_PMSELR(rr) p15, 0, rr, c9, c12, 5 /* PM Event Counter Selection Register */ 208*b58fb0baSjsg #define CP15_PMCCNTR(rr) p15, 0, rr, c9, c13, 0 /* PM Cycle Count Register */ 209*b58fb0baSjsg #define CP15_PMXEVTYPER(rr) p15, 0, rr, c9, c13, 1 /* PM Event Type Select Register */ 210*b58fb0baSjsg #define CP15_PMXEVCNTRR(rr) p15, 0, rr, c9, c13, 2 /* PM Event Count Register */ 211*b58fb0baSjsg #define CP15_PMUSERENR(rr) p15, 0, rr, c9, c14, 0 /* PM User Enable Register */ 212*b58fb0baSjsg #define CP15_PMINTENSET(rr) p15, 0, rr, c9, c14, 1 /* PM Interrupt Enable Set Register */ 213*b58fb0baSjsg #define CP15_PMINTENCLR(rr) p15, 0, rr, c9, c14, 2 /* PM Interrupt Enable Clear Register */ 214*b58fb0baSjsg 215*b58fb0baSjsg /* 216*b58fb0baSjsg * CP15 C10 registers 217*b58fb0baSjsg */ 218*b58fb0baSjsg /* Without LPAE this is PRRR, with LPAE it's MAIR0 */ 219*b58fb0baSjsg #define CP15_PRRR(rr) p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */ 220*b58fb0baSjsg #define CP15_MAIR0(rr) p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */ 221*b58fb0baSjsg /* Without LPAE this is NMRR, with LPAE it's MAIR1 */ 222*b58fb0baSjsg #define CP15_NMRR(rr) p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */ 223*b58fb0baSjsg #define CP15_MAIR1(rr) p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */ 224*b58fb0baSjsg 225*b58fb0baSjsg #define CP15_AMAIR0(rr) p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */ 226*b58fb0baSjsg #define CP15_AMAIR1(rr) p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */ 227*b58fb0baSjsg 228*b58fb0baSjsg /* 229*b58fb0baSjsg * CP15 C12 registers 230*b58fb0baSjsg */ 231*b58fb0baSjsg #define CP15_VBAR(rr) p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */ 232*b58fb0baSjsg #define CP15_MVBAR(rr) p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */ 233*b58fb0baSjsg 234*b58fb0baSjsg #define CP15_ISR(rr) p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */ 235*b58fb0baSjsg 236*b58fb0baSjsg /* 237*b58fb0baSjsg * CP15 C13 registers 238*b58fb0baSjsg */ 239*b58fb0baSjsg #define CP15_FCSEIDR(rr) p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */ 240*b58fb0baSjsg #define CP15_CONTEXTIDR(rr) p15, 0, rr, c13, c0, 1 /* Context ID Register */ 241*b58fb0baSjsg #define CP15_TPIDRURW(rr) p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */ 242*b58fb0baSjsg #define CP15_TPIDRURO(rr) p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */ 243*b58fb0baSjsg #define CP15_TPIDRPRW(rr) p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */ 244*b58fb0baSjsg 245*b58fb0baSjsg /* 246*b58fb0baSjsg * CP15 C14 registers 247*b58fb0baSjsg * These are the Generic Timer registers and may be unallocated on some SoCs. 248*b58fb0baSjsg * Only use these when you know the Generic Timer is available. 249*b58fb0baSjsg */ 250*b58fb0baSjsg #define CP15_CNTFRQ(rr) p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */ 251*b58fb0baSjsg #define CP15_CNTKCTL(rr) p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */ 252*b58fb0baSjsg #define CP15_CNTP_TVAL(rr) p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */ 253*b58fb0baSjsg #define CP15_CNTP_CTL(rr) p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */ 254*b58fb0baSjsg #define CP15_CNTV_TVAL(rr) p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */ 255*b58fb0baSjsg #define CP15_CNTV_CTL(rr) p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */ 256*b58fb0baSjsg #define CP15_CNTHCTL(rr) p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */ 257*b58fb0baSjsg #define CP15_CNTHP_TVAL(rr) p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */ 258*b58fb0baSjsg #define CP15_CNTHP_CTL(rr) p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */ 259*b58fb0baSjsg /* 64-bit registers for use with mcrr/mrrc */ 260*b58fb0baSjsg #define CP15_CNTPCT(rq, rr) p15, 0, rq, rr, c14 /* Physical Count Register */ 261*b58fb0baSjsg #define CP15_CNTVCT(rq, rr) p15, 1, rq, rr, c14 /* Virtual Count Register */ 262*b58fb0baSjsg #define CP15_CNTP_CVAL(rq, rr) p15, 2, rq, rr, c14 /* PL1 Physical Timer Compare Value Register */ 263*b58fb0baSjsg #define CP15_CNTV_CVAL(rq, rr) p15, 3, rq, rr, c14 /* Virtual Timer Compare Value Register */ 264*b58fb0baSjsg #define CP15_CNTVOFF(rq, rr) p15, 4, rq, rr, c14 /* Virtual Offset Register */ 265*b58fb0baSjsg #define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14 /* PL2 Physical Timer Compare Value Register */ 266*b58fb0baSjsg 267*b58fb0baSjsg /* 268*b58fb0baSjsg * CP15 C15 registers 269*b58fb0baSjsg */ 270*b58fb0baSjsg #define CP15_CBAR(rr) p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */ 271*b58fb0baSjsg 272*b58fb0baSjsg #endif /* !MACHINE_SYSREG_H */ 273