xref: /openbsd-src/sys/arch/arm/include/cpuconf.h (revision aaa8efb37c85cfa0bfcccf33c96a297c02665e60)
1*aaa8efb3Smiod /*	$OpenBSD: cpuconf.h,v 1.20 2024/11/07 08:12:12 miod Exp $	*/
2e1e4f5b1Sdrahn /*	$NetBSD: cpuconf.h,v 1.7 2003/05/23 00:57:24 ichiro Exp $	*/
3e1e4f5b1Sdrahn 
4e1e4f5b1Sdrahn /*
5e1e4f5b1Sdrahn  * Copyright (c) 2002 Wasabi Systems, Inc.
6e1e4f5b1Sdrahn  * All rights reserved.
7e1e4f5b1Sdrahn  *
8e1e4f5b1Sdrahn  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
9e1e4f5b1Sdrahn  *
10e1e4f5b1Sdrahn  * Redistribution and use in source and binary forms, with or without
11e1e4f5b1Sdrahn  * modification, are permitted provided that the following conditions
12e1e4f5b1Sdrahn  * are met:
13e1e4f5b1Sdrahn  * 1. Redistributions of source code must retain the above copyright
14e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer.
15e1e4f5b1Sdrahn  * 2. Redistributions in binary form must reproduce the above copyright
16e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer in the
17e1e4f5b1Sdrahn  *    documentation and/or other materials provided with the distribution.
18e1e4f5b1Sdrahn  * 3. All advertising materials mentioning features or use of this software
19e1e4f5b1Sdrahn  *    must display the following acknowledgement:
20e1e4f5b1Sdrahn  *	This product includes software developed for the NetBSD Project by
21e1e4f5b1Sdrahn  *	Wasabi Systems, Inc.
22e1e4f5b1Sdrahn  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
23e1e4f5b1Sdrahn  *    or promote products derived from this software without specific prior
24e1e4f5b1Sdrahn  *    written permission.
25e1e4f5b1Sdrahn  *
26e1e4f5b1Sdrahn  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
27e1e4f5b1Sdrahn  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28e1e4f5b1Sdrahn  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29e1e4f5b1Sdrahn  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
30e1e4f5b1Sdrahn  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31e1e4f5b1Sdrahn  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32e1e4f5b1Sdrahn  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33e1e4f5b1Sdrahn  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34e1e4f5b1Sdrahn  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35e1e4f5b1Sdrahn  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36e1e4f5b1Sdrahn  * POSSIBILITY OF SUCH DAMAGE.
37e1e4f5b1Sdrahn  */
38e1e4f5b1Sdrahn 
39e1e4f5b1Sdrahn #ifndef _ARM_CPUCONF_H_
40e1e4f5b1Sdrahn #define	_ARM_CPUCONF_H_
41e1e4f5b1Sdrahn 
42e1e4f5b1Sdrahn /*
43ab5e4bb7Smiod  * Define which MMU classes are configured:
44e1e4f5b1Sdrahn  *
450b0e92f9Sdrahn  *      ARM_MMU_V7		v6/v7 MMU with XP bit enabled subpage
460b0e92f9Sdrahn  *				protection is not used, TEX/AP is used instead.
47e1e4f5b1Sdrahn  */
48e1e4f5b1Sdrahn 
490b0e92f9Sdrahn #define ARM_MMU_V7		1
50e86c322dSdrahn 
5154b25531Sjsg #define	ARM_NMMUS		(ARM_MMU_V7)
52e1e4f5b1Sdrahn 
53e1e4f5b1Sdrahn #endif /* _ARM_CPUCONF_H_ */
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