xref: /openbsd-src/sys/arch/arm/include/cpu.h (revision b43d7c278ce9b35401a121323bd85088ec5b9443)
1*b43d7c27Sjca /*	$OpenBSD: cpu.h,v 1.67 2024/06/09 21:15:29 jca Exp $	*/
2e1e4f5b1Sdrahn /*	$NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $	*/
3e1e4f5b1Sdrahn 
4e1e4f5b1Sdrahn /*
5e1e4f5b1Sdrahn  * Copyright (c) 1994-1996 Mark Brinicombe.
6e1e4f5b1Sdrahn  * Copyright (c) 1994 Brini.
7e1e4f5b1Sdrahn  * All rights reserved.
8e1e4f5b1Sdrahn  *
9e1e4f5b1Sdrahn  * This code is derived from software written for Brini by Mark Brinicombe
10e1e4f5b1Sdrahn  *
11e1e4f5b1Sdrahn  * Redistribution and use in source and binary forms, with or without
12e1e4f5b1Sdrahn  * modification, are permitted provided that the following conditions
13e1e4f5b1Sdrahn  * are met:
14e1e4f5b1Sdrahn  * 1. Redistributions of source code must retain the above copyright
15e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer.
16e1e4f5b1Sdrahn  * 2. Redistributions in binary form must reproduce the above copyright
17e1e4f5b1Sdrahn  *    notice, this list of conditions and the following disclaimer in the
18e1e4f5b1Sdrahn  *    documentation and/or other materials provided with the distribution.
19e1e4f5b1Sdrahn  * 3. All advertising materials mentioning features or use of this software
20e1e4f5b1Sdrahn  *    must display the following acknowledgement:
21e1e4f5b1Sdrahn  *	This product includes software developed by Brini.
22e1e4f5b1Sdrahn  * 4. The name of the company nor the name of the author may be used to
23e1e4f5b1Sdrahn  *    endorse or promote products derived from this software without specific
24e1e4f5b1Sdrahn  *    prior written permission.
25e1e4f5b1Sdrahn  *
26e1e4f5b1Sdrahn  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27e1e4f5b1Sdrahn  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28e1e4f5b1Sdrahn  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29e1e4f5b1Sdrahn  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30e1e4f5b1Sdrahn  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31e1e4f5b1Sdrahn  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32e1e4f5b1Sdrahn  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33e1e4f5b1Sdrahn  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34e1e4f5b1Sdrahn  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35e1e4f5b1Sdrahn  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36e1e4f5b1Sdrahn  * SUCH DAMAGE.
37e1e4f5b1Sdrahn  *
38e1e4f5b1Sdrahn  * RiscBSD kernel project
39e1e4f5b1Sdrahn  *
40e1e4f5b1Sdrahn  * cpu.h
41e1e4f5b1Sdrahn  *
42e1e4f5b1Sdrahn  * CPU specific symbols
43e1e4f5b1Sdrahn  *
44e1e4f5b1Sdrahn  * Created      : 18/09/94
45e1e4f5b1Sdrahn  *
46e1e4f5b1Sdrahn  * Based on kate/katelib/arm6.h
47e1e4f5b1Sdrahn  */
48e1e4f5b1Sdrahn 
49e1e4f5b1Sdrahn #ifndef _ARM_CPU_H_
50e1e4f5b1Sdrahn #define _ARM_CPU_H_
51e1e4f5b1Sdrahn 
52e1e4f5b1Sdrahn /*
53e1e4f5b1Sdrahn  * User-visible definitions
54e1e4f5b1Sdrahn  */
55e1e4f5b1Sdrahn 
56e1e4f5b1Sdrahn /*  CTL_MACHDEP definitions. */
57ec6a7f63Smiod 		/*		1	   formerly int: CPU_DEBUG */
58ec6a7f63Smiod 		/*		2	   formerly string: CPU_BOOTED_DEVICE */
59ec6a7f63Smiod 		/*		3	   formerly string: CPU_BOOTED_KERNEL */
60e1e4f5b1Sdrahn #define	CPU_CONSDEV		4	/* struct: dev_t of our console */
61e1e4f5b1Sdrahn #define	CPU_POWERSAVE		5	/* int: use CPU powersave mode */
6242a67522Sdrahn #define	CPU_ALLOWAPERTURE	6	/* int: allow mmap of /dev/xf86 */
638e4e4f54Stedu 		/*		7	   formerly int: apmwarn */
64b2e0f490Snaddy 		/*		8	   formerly int: keyboard reset */
65f70fb4eeSderaadt 		/*		9	   formerly int: CPU_ZTSRAWMODE */
66f70fb4eeSderaadt 		/*		10	   formerly struct: CPU_ZTSSCALE */
67d01e828bSderaadt #define	CPU_MAXSPEED		11	/* int: number of valid machdep ids */
6839325887Snatano 		/*		12	   formerly int: CPU_LIDSUSPEND */
692d357aedSnatano #define CPU_LIDACTION		13	/* action caused by lid close */
70c5c0009cSkettenis #define	CPU_COMPATIBLE		14	/* compatible property */
71c5c0009cSkettenis #define	CPU_MAXID		15	/* number of valid machdep ids */
72e1e4f5b1Sdrahn 
73e1e4f5b1Sdrahn #define	CTL_MACHDEP_NAMES { \
74e1e4f5b1Sdrahn 	{ 0, 0 }, \
75ec6a7f63Smiod 	{ 0, 0 }, \
76ec6a7f63Smiod 	{ 0, 0 }, \
77ec6a7f63Smiod 	{ 0, 0 }, \
78e1e4f5b1Sdrahn 	{ "console_device", CTLTYPE_STRUCT }, \
79e1e4f5b1Sdrahn 	{ "powersave", CTLTYPE_INT }, \
8042a67522Sdrahn 	{ "allowaperture", CTLTYPE_INT }, \
818e4e4f54Stedu 	{ 0, 0 }, \
82b2e0f490Snaddy 	{ 0, 0 }, \
83f70fb4eeSderaadt 	{ 0, 0 }, \
84f70fb4eeSderaadt 	{ 0, 0 }, \
85d01e828bSderaadt 	{ "maxspeed", CTLTYPE_INT }, \
8639325887Snatano 	{ 0, 0 }, \
8742255e0dStom 	{ "lidaction", CTLTYPE_INT }, \
88c5c0009cSkettenis 	{ "compatible", CTLTYPE_STRING }, \
89e1e4f5b1Sdrahn }
90e1e4f5b1Sdrahn 
91e1e4f5b1Sdrahn #ifdef _KERNEL
92e1e4f5b1Sdrahn 
93e1e4f5b1Sdrahn /*
94e1e4f5b1Sdrahn  * Kernel-only definitions
95e1e4f5b1Sdrahn  */
96e1e4f5b1Sdrahn 
97e1e4f5b1Sdrahn #include <arm/cpuconf.h>
98e1e4f5b1Sdrahn 
99e1e4f5b1Sdrahn #include <machine/intr.h>
100e1e4f5b1Sdrahn #include <machine/frame.h>
101e1e4f5b1Sdrahn #include <machine/pcb.h>
102e1e4f5b1Sdrahn #include <arm/armreg.h>
103e1e4f5b1Sdrahn 
104e1e4f5b1Sdrahn /* 1 == use cpu_sleep(), 0 == don't */
105e1e4f5b1Sdrahn extern int cpu_do_powersave;
106e1e4f5b1Sdrahn 
107e1e4f5b1Sdrahn /* All the CLKF_* macros take a struct clockframe * as an argument. */
108e1e4f5b1Sdrahn 
109e1e4f5b1Sdrahn /*
110e1e4f5b1Sdrahn  * CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the
111e1e4f5b1Sdrahn  * frame came from USR mode or not.
112e1e4f5b1Sdrahn  */
113e1e4f5b1Sdrahn #define CLKF_USERMODE(frame)	((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE)
114e1e4f5b1Sdrahn 
115e1e4f5b1Sdrahn /*
116e1e4f5b1Sdrahn  * CLKF_INTR: True if we took the interrupt from inside another
117e1e4f5b1Sdrahn  * interrupt handler.
118e1e4f5b1Sdrahn  */
119f5bc2bf2Spatrick #define CLKF_INTR(frame)	(curcpu()->ci_idepth > 1)
120e1e4f5b1Sdrahn 
121e1e4f5b1Sdrahn /*
122e1e4f5b1Sdrahn  * CLKF_PC: Extract the program counter from a clockframe
123e1e4f5b1Sdrahn  */
124e1e4f5b1Sdrahn #define CLKF_PC(frame)		(frame->if_pc)
125e1e4f5b1Sdrahn 
126e1e4f5b1Sdrahn /*
127e1e4f5b1Sdrahn  * PROC_PC: Find out the program counter for the given process.
128e1e4f5b1Sdrahn  */
129e1e4f5b1Sdrahn #define PROC_PC(p)	((p)->p_addr->u_pcb.pcb_tf->tf_pc)
1301eaa59e7Sguenther #define PROC_STACK(p)	((p)->p_addr->u_pcb.pcb_tf->tf_usr_sp)
131e1e4f5b1Sdrahn 
132e1e4f5b1Sdrahn /* The address of the vector page. */
133e1e4f5b1Sdrahn extern vaddr_t vector_page;
134e1e4f5b1Sdrahn void	arm32_vector_init(vaddr_t, int);
135e1e4f5b1Sdrahn 
136e1e4f5b1Sdrahn #define	ARM_VEC_RESET			(1 << 0)
137e1e4f5b1Sdrahn #define	ARM_VEC_UNDEFINED		(1 << 1)
138e1e4f5b1Sdrahn #define	ARM_VEC_SWI			(1 << 2)
139e1e4f5b1Sdrahn #define	ARM_VEC_PREFETCH_ABORT		(1 << 3)
140e1e4f5b1Sdrahn #define	ARM_VEC_DATA_ABORT		(1 << 4)
141e1e4f5b1Sdrahn #define	ARM_VEC_ADDRESS_EXCEPTION	(1 << 5)
142e1e4f5b1Sdrahn #define	ARM_VEC_IRQ			(1 << 6)
143e1e4f5b1Sdrahn #define	ARM_VEC_FIQ			(1 << 7)
144e1e4f5b1Sdrahn 
145e1e4f5b1Sdrahn #define	ARM_NVEC			8
146e1e4f5b1Sdrahn #define	ARM_VEC_ALL			0xffffffff
147e1e4f5b1Sdrahn 
148e1e4f5b1Sdrahn /*
149e1e4f5b1Sdrahn  * Per-CPU information.  For now we assume one CPU.
150e1e4f5b1Sdrahn  */
151e1e4f5b1Sdrahn 
152dfaeb4bfScheloha #include <sys/clockintr.h>
153e1e4f5b1Sdrahn #include <sys/device.h>
154e1e4f5b1Sdrahn #include <sys/sched.h>
1551a1181a9Sjsg #include <sys/srp.h>
156abff443dSkettenis 
157e1e4f5b1Sdrahn struct cpu_info {
158f5bc2bf2Spatrick 	struct device		*ci_dev; /* Device corresponding to this CPU */
15909a5e7d8Spatrick 	struct cpu_info		*ci_next;
160f5bc2bf2Spatrick 	struct schedstate_percpu ci_schedstate; /* scheduler state */
161f5bc2bf2Spatrick 
1626a1ae6a6Skettenis 	u_int32_t		ci_cpuid;
1636a1ae6a6Skettenis 	uint64_t		ci_mpidr;
1643d29854dSkettenis 	int			ci_node;
1656a1ae6a6Skettenis 	struct cpu_info		*ci_self;
1663d29854dSkettenis 
167ace724d0Sart 	struct proc		*ci_curproc;
168c7b5578aSkettenis 	struct proc		*ci_fpuproc;
16909a5e7d8Spatrick 	u_int32_t		ci_randseed;
17009a5e7d8Spatrick 
17109a5e7d8Spatrick 	struct pcb		*ci_curpcb;
172aa482f12Spatrick 	struct pcb		*ci_idle_pcb;
173ace724d0Sart 
174e8a6d282Sdrahn 	uint32_t		ci_cpl;
175e8a6d282Sdrahn 	uint32_t		ci_ipending;
176f5bc2bf2Spatrick 	uint32_t		ci_idepth;
177f5bc2bf2Spatrick #ifdef DIAGNOSTIC
178f5bc2bf2Spatrick 	int			ci_mutex_level;
179f5bc2bf2Spatrick #endif
1806a1ae6a6Skettenis 	int			ci_want_resched;
1816a1ae6a6Skettenis 
1826a1ae6a6Skettenis 	void			(*ci_flush_bp)(void);
183f5bc2bf2Spatrick 
1843d29854dSkettenis 	struct opp_table	*ci_opp_table;
1853d29854dSkettenis 	volatile int		ci_opp_idx;
1863d29854dSkettenis 	volatile int		ci_opp_max;
1873d29854dSkettenis 	uint32_t		ci_cpu_supply;
1883d29854dSkettenis 
189abff443dSkettenis #ifdef MULTIPROCESSOR
190abff443dSkettenis 	struct srp_hazard	ci_srp_hazards[SRP_HAZARD_NUM];
1914e7e04caSkettenis 	volatile int		ci_flags;
1924e7e04caSkettenis 	uint32_t		ci_ttbr0;
1934e7e04caSkettenis 	vaddr_t			ci_pl1_stkend;
1944e7e04caSkettenis 	vaddr_t			ci_irq_stkend;
1954e7e04caSkettenis 	vaddr_t			ci_abt_stkend;
1964e7e04caSkettenis 	vaddr_t			ci_und_stkend;
197abff443dSkettenis #endif
198abff443dSkettenis 
1996377c2eaSmpi #ifdef GPROF
2006377c2eaSmpi 	struct gmonparam *ci_gmon;
2011d970828Scheloha 	struct clockintr ci_gmonclock;
2026377c2eaSmpi #endif
203c737cf90Scheloha 	struct clockqueue	ci_queue;
2041a4a9ab2Scheloha 	char			ci_panicbuf[512];
205e1e4f5b1Sdrahn };
206e1e4f5b1Sdrahn 
2076a1ae6a6Skettenis #define CPUF_PRIMARY 		(1<<0)
2086a1ae6a6Skettenis #define CPUF_AP	 		(1<<1)
2096a1ae6a6Skettenis #define CPUF_IDENTIFY		(1<<2)
2106a1ae6a6Skettenis #define CPUF_IDENTIFIED		(1<<3)
2116a1ae6a6Skettenis #define CPUF_PRESENT		(1<<4)
2126a1ae6a6Skettenis #define CPUF_GO			(1<<5)
2136a1ae6a6Skettenis #define CPUF_RUNNING		(1<<6)
2146a1ae6a6Skettenis 
215df0dc601Spatrick static inline struct cpu_info *
curcpu(void)216df0dc601Spatrick curcpu(void)
217df0dc601Spatrick {
218df0dc601Spatrick 	struct cpu_info *__ci;
219df0dc601Spatrick 	__asm volatile("mrc	p15, 0, %0, c13, c0, 4" : "=r" (__ci));
220df0dc601Spatrick 	return (__ci);
221df0dc601Spatrick }
222df0dc601Spatrick 
223abff443dSkettenis extern struct cpu_info cpu_info_primary;
224abff443dSkettenis extern struct cpu_info *cpu_info_list;
225abff443dSkettenis 
226df0dc601Spatrick #ifndef MULTIPROCESSOR
227e1e4f5b1Sdrahn #define cpu_number()	0
228ace724d0Sart #define CPU_IS_PRIMARY(ci)	1
229d73de46fSkettenis #define CPU_IS_RUNNING(ci)	1
230ace724d0Sart #define CPU_INFO_ITERATOR	int
231ace724d0Sart #define CPU_INFO_FOREACH(cii, ci) \
232ace724d0Sart 	for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
2334bbbf93eSart #define CPU_INFO_UNIT(ci)	0
234e3444f33Sart #define MAXCPUS	1
235056a2ca6Skettenis #define cpu_kick(ci)
236e17eb8b0Sart #define cpu_unidle(ci)
237869502c2Spatrick #else
238869502c2Spatrick #define cpu_number()		(curcpu()->ci_cpuid)
239869502c2Spatrick #define CPU_IS_PRIMARY(ci)	((ci) == &cpu_info_primary)
240d73de46fSkettenis #define CPU_IS_RUNNING(ci)	((ci)->ci_flags & CPUF_RUNNING)
241869502c2Spatrick #define CPU_INFO_ITERATOR		int
242869502c2Spatrick #define CPU_INFO_FOREACH(cii, ci)	for (cii = 0, ci = cpu_info_list; \
243869502c2Spatrick 					    ci != NULL; ci = ci->ci_next)
244869502c2Spatrick #define CPU_INFO_UNIT(ci)	((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
245869502c2Spatrick #define MAXCPUS	4
246056a2ca6Skettenis void cpu_kick(struct cpu_info *);
247056a2ca6Skettenis void cpu_unidle(struct cpu_info *ci);
248869502c2Spatrick 
249869502c2Spatrick extern struct cpu_info *cpu_info[MAXCPUS];
250869502c2Spatrick 
251869502c2Spatrick void cpu_boot_secondary_processors(void);
252869502c2Spatrick #endif /* !MULTIPROCESSOR */
253e1e4f5b1Sdrahn 
254*b43d7c27Sjca #define CPU_BUSY_CYCLE()	__asm volatile ("" ::: "memory")
25565f535b7Suebayasi 
25609a5e7d8Spatrick #define curpcb		curcpu()->ci_curpcb
25709a5e7d8Spatrick 
25801802d2cSdlg unsigned int cpu_rnd_messybits(void);
25901802d2cSdlg 
260e1e4f5b1Sdrahn /*
261e1e4f5b1Sdrahn  * Scheduling glue
262e1e4f5b1Sdrahn  */
263e1e4f5b1Sdrahn 
264e1e4f5b1Sdrahn extern int astpending;
265e1e4f5b1Sdrahn #define setsoftast() (astpending = 1)
266e1e4f5b1Sdrahn 
267e1e4f5b1Sdrahn /*
268e1e4f5b1Sdrahn  * Notify the current process (p) that it has a signal pending,
269e1e4f5b1Sdrahn  * process as soon as possible.
270e1e4f5b1Sdrahn  */
271e1e4f5b1Sdrahn 
272e1e4f5b1Sdrahn #define signotify(p)            setsoftast()
273e1e4f5b1Sdrahn 
274e1e4f5b1Sdrahn /*
275e1e4f5b1Sdrahn  * Preempt the current process if in interrupt from user mode,
276e1e4f5b1Sdrahn  * or after the current trap/syscall if in system mode.
277e1e4f5b1Sdrahn  */
278e1e4f5b1Sdrahn extern int want_resched;	/* resched() was called */
279e1e4f5b1Sdrahn #define	need_resched(ci)	(want_resched = 1, setsoftast())
2802c9d4ccbSart #define clear_resched(ci) 	want_resched = 0
281e1e4f5b1Sdrahn 
282e1e4f5b1Sdrahn /*
283e1e4f5b1Sdrahn  * Give a profiling tick to the current process when the user profiling
284e1e4f5b1Sdrahn  * buffer pages are invalid.  On the i386, request an ast to send us
285e1e4f5b1Sdrahn  * through trap(), marking the proc as needing a profiling tick.
286e1e4f5b1Sdrahn  */
28729514732Sart #define	need_proftick(p)	setsoftast()
288e1e4f5b1Sdrahn 
289e1e4f5b1Sdrahn /*
290e1e4f5b1Sdrahn  * cpu device glue (belongs in cpuvar.h)
291e1e4f5b1Sdrahn  */
292e1e4f5b1Sdrahn 
293aa482f12Spatrick int	cpu_alloc_idle_pcb(struct cpu_info *);
294e1e4f5b1Sdrahn 
295e1e4f5b1Sdrahn /*
296e1e4f5b1Sdrahn  * Random cruft
297e1e4f5b1Sdrahn  */
298e1e4f5b1Sdrahn 
299e1e4f5b1Sdrahn /* cpuswitch.S */
300e1e4f5b1Sdrahn struct pcb;
30138b77b7aSdrahn void	savectx		(struct pcb *pcb);
302e1e4f5b1Sdrahn 
303e1e4f5b1Sdrahn /* machdep.h */
3041eae9e2dSmiod void bootsync		(int);
305e1e4f5b1Sdrahn 
306e1e4f5b1Sdrahn /* fault.c */
30738b77b7aSdrahn int badaddr_read	(void *, size_t, void *);
308e1e4f5b1Sdrahn 
309e1e4f5b1Sdrahn /* syscall.c */
31038b77b7aSdrahn void swi_handler	(trapframe_t *);
311e1e4f5b1Sdrahn 
312142120ddSmiod /* machine_machdep.c */
313142120ddSmiod void board_startup(void);
314142120ddSmiod 
315abff443dSkettenis static inline u_long
intr_disable(void)316abff443dSkettenis intr_disable(void)
317abff443dSkettenis {
318abff443dSkettenis 	uint32_t cpsr;
319abff443dSkettenis 
320abff443dSkettenis 	__asm volatile ("mrs %0, cpsr" : "=r"(cpsr));
321abff443dSkettenis 	__asm volatile ("msr cpsr_c, %0" :: "r"(cpsr | PSR_I));
322abff443dSkettenis 
323abff443dSkettenis 	return cpsr;
324abff443dSkettenis }
325abff443dSkettenis 
326abff443dSkettenis static inline void
intr_restore(u_long cpsr)327abff443dSkettenis intr_restore(u_long cpsr)
328abff443dSkettenis {
329abff443dSkettenis 	__asm volatile ("msr cpsr_c, %0" :: "r"(cpsr));
330abff443dSkettenis }
331e1e4f5b1Sdrahn 
332e1e4f5b1Sdrahn #endif /* _KERNEL */
333e1e4f5b1Sdrahn 
334abff443dSkettenis #ifdef MULTIPROCESSOR
335abff443dSkettenis #include <sys/mplock.h>
336abff443dSkettenis #endif /* MULTIPROCESSOR */
337abff443dSkettenis 
338e1e4f5b1Sdrahn #endif /* !_ARM_CPU_H_ */
339