1*23781415Spirofti /* $OpenBSD: pctr.h,v 1.7 2019/08/26 12:41:47 pirofti Exp $ */ 2a456bd90Sderaadt 3a456bd90Sderaadt /* 4a456bd90Sderaadt * Pentium performance counter driver for OpenBSD. 5a456bd90Sderaadt * Copyright 1996 David Mazieres <dm@lcs.mit.edu>. 6a456bd90Sderaadt * 7a456bd90Sderaadt * Modification and redistribution in source and binary forms is 8a456bd90Sderaadt * permitted provided that due credit is given to the author and the 9a456bd90Sderaadt * OpenBSD project by leaving this copyright notice intact. 10a456bd90Sderaadt */ 11a456bd90Sderaadt 122fa72412Spirofti #ifndef _MACHINE_PCTR_H_ 132fa72412Spirofti #define _MACHINE_PCTR_H_ 14a456bd90Sderaadt 15a456bd90Sderaadt #include <sys/ioccom.h> 16a456bd90Sderaadt 179eecd0bfSderaadt typedef u_int64_t pctrval; 189eecd0bfSderaadt 19a456bd90Sderaadt #define PCTR_NUM 4 20a456bd90Sderaadt 21a456bd90Sderaadt struct pctrst { 229eecd0bfSderaadt u_int pctr_fn[PCTR_NUM]; /* Current settings of counters */ 239eecd0bfSderaadt pctrval pctr_tsc; /* Free-running 64-bit cycle counter */ 249eecd0bfSderaadt pctrval pctr_hwc[PCTR_NUM]; /* Values of the hardware counters */ 25a456bd90Sderaadt }; 26a456bd90Sderaadt 27a456bd90Sderaadt /* Bit values in fn fields and PIOCS ioctl's */ 28a456bd90Sderaadt #define PCTR_U 0x010000 /* Monitor user-level events */ 29a456bd90Sderaadt #define PCTR_K 0x020000 /* Monitor kernel-level events */ 30a456bd90Sderaadt #define PCTR_E 0x040000 /* Edge detect */ 31a456bd90Sderaadt #define PCTR_EN 0x400000 /* Enable counters (counter 0 only) */ 32a456bd90Sderaadt #define PCTR_I 0x800000 /* Invert counter mask */ 33a456bd90Sderaadt 349eecd0bfSderaadt /* Unit Mask values to distinguish cache coherent states */ 359eecd0bfSderaadt #define PCTR_UM_M 0x0800 /* Modified cache lines */ 369eecd0bfSderaadt #define PCTR_UM_E 0x0400 /* Exclusive cache lines */ 379eecd0bfSderaadt #define PCTR_UM_S 0x0200 /* Shared cache lines */ 389eecd0bfSderaadt #define PCTR_UM_I 0x0100 /* Invalid cache lines */ 399eecd0bfSderaadt #define PCTR_UM_MESI (PCTR_UM_M|PCTR_UM_E|PCTR_UM_S|PCTR_UM_I) 409eecd0bfSderaadt #define PCTR_UM_A 0x2000 /* Any initiator */ 41a456bd90Sderaadt 429eecd0bfSderaadt #define PCTR_UM_SHIFT 8 /* Left shift for unit mask */ 439eecd0bfSderaadt #define PCTR_CM_SHIFT 24 /* Left shift for counter mask */ 449eecd0bfSderaadt 459eecd0bfSderaadt /* ioctl to set which counter a device tracks */ 46a456bd90Sderaadt #define PCIOCRD _IOR('c', 1, struct pctrst) /* Read counter value */ 47a456bd90Sderaadt #define PCIOCS0 _IOW('c', 8, unsigned int) /* Set counter 0 function */ 48a456bd90Sderaadt #define PCIOCS1 _IOW('c', 9, unsigned int) /* Set counter 1 function */ 49a456bd90Sderaadt #define PCIOCS2 _IOW('c', 10, unsigned int) /* Set counter 2 function */ 50a456bd90Sderaadt #define PCIOCS3 _IOW('c', 11, unsigned int) /* Set counter 3 function */ 51a456bd90Sderaadt 52a456bd90Sderaadt #define _PATH_PCTR "/dev/pctr" 53a456bd90Sderaadt 549eecd0bfSderaadt #define rdpmc(pmc) \ 559eecd0bfSderaadt ({ \ 569eecd0bfSderaadt u_int32_t hi, lo; \ 572df76cc2Sguenther __asm volatile("rdpmc" \ 589eecd0bfSderaadt : "=d" (hi), "=a" (lo) : "c" (pmc)); \ 599eecd0bfSderaadt hi &= 0xffffff; \ 609eecd0bfSderaadt (((u_int64_t)hi << 32) | (u_int64_t)lo); \ 619eecd0bfSderaadt }) 629eecd0bfSderaadt 63a456bd90Sderaadt #ifdef _KERNEL 64a456bd90Sderaadt 65a456bd90Sderaadt void pctrattach(int); 66a456bd90Sderaadt int pctropen(dev_t, int, int, struct proc *); 67a456bd90Sderaadt int pctrclose(dev_t, int, int, struct proc *); 689eecd0bfSderaadt int pctrioctl(dev_t, u_long, caddr_t, int, struct proc *); 6970cf982aSguenther void pctr_reload(struct cpu_info *); 7070cf982aSguenther void pctr_resume(struct cpu_info *); 71a456bd90Sderaadt 72a456bd90Sderaadt #endif /* _KERNEL */ 732fa72412Spirofti #endif /* ! _MACHINE_PCTR_H_ */ 74