xref: /openbsd-src/sys/arch/amd64/include/bus.h (revision d5a984e5ffbed41e56832b99c96a9ef19fad454b)
1*d5a984e5Sbluhm /*	$OpenBSD: bus.h,v 1.36 2024/08/14 18:31:33 bluhm Exp $	*/
2f5df1827Smickey /*	$NetBSD: bus.h,v 1.6 1996/11/10 03:19:25 thorpej Exp $	*/
3f5df1827Smickey 
4f5df1827Smickey /*-
5f5df1827Smickey  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
6f5df1827Smickey  * All rights reserved.
7f5df1827Smickey  *
8f5df1827Smickey  * This code is derived from software contributed to The NetBSD Foundation
9f5df1827Smickey  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10f5df1827Smickey  * NASA Ames Research Center.
11f5df1827Smickey  *
12f5df1827Smickey  * Redistribution and use in source and binary forms, with or without
13f5df1827Smickey  * modification, are permitted provided that the following conditions
14f5df1827Smickey  * are met:
15f5df1827Smickey  * 1. Redistributions of source code must retain the above copyright
16f5df1827Smickey  *    notice, this list of conditions and the following disclaimer.
17f5df1827Smickey  * 2. Redistributions in binary form must reproduce the above copyright
18f5df1827Smickey  *    notice, this list of conditions and the following disclaimer in the
19f5df1827Smickey  *    documentation and/or other materials provided with the distribution.
20f5df1827Smickey  *
21f5df1827Smickey  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22f5df1827Smickey  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23f5df1827Smickey  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24f5df1827Smickey  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25f5df1827Smickey  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26f5df1827Smickey  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27f5df1827Smickey  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28f5df1827Smickey  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29f5df1827Smickey  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30f5df1827Smickey  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31f5df1827Smickey  * POSSIBILITY OF SUCH DAMAGE.
32f5df1827Smickey  */
33f5df1827Smickey 
34f5df1827Smickey /*
35f5df1827Smickey  * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
36f5df1827Smickey  * Copyright (c) 1996 Jason R. Thorpe.  All rights reserved.
37f5df1827Smickey  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
38f5df1827Smickey  *
39f5df1827Smickey  * Redistribution and use in source and binary forms, with or without
40f5df1827Smickey  * modification, are permitted provided that the following conditions
41f5df1827Smickey  * are met:
42f5df1827Smickey  * 1. Redistributions of source code must retain the above copyright
43f5df1827Smickey  *    notice, this list of conditions and the following disclaimer.
44f5df1827Smickey  * 2. Redistributions in binary form must reproduce the above copyright
45f5df1827Smickey  *    notice, this list of conditions and the following disclaimer in the
46f5df1827Smickey  *    documentation and/or other materials provided with the distribution.
47f5df1827Smickey  * 3. All advertising materials mentioning features or use of this software
48f5df1827Smickey  *    must display the following acknowledgement:
49f5df1827Smickey  *	This product includes software developed by Christopher G. Demetriou
50f5df1827Smickey  *	for the NetBSD Project.
51f5df1827Smickey  * 4. The name of the author may not be used to endorse or promote products
52f5df1827Smickey  *    derived from this software without specific prior written permission
53f5df1827Smickey  *
54f5df1827Smickey  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
55f5df1827Smickey  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
56f5df1827Smickey  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
57f5df1827Smickey  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
58f5df1827Smickey  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
59f5df1827Smickey  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60f5df1827Smickey  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61f5df1827Smickey  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62f5df1827Smickey  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
63f5df1827Smickey  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64f5df1827Smickey  */
65f5df1827Smickey 
662fa72412Spirofti #ifndef _MACHINE_BUS_H_
672fa72412Spirofti #define _MACHINE_BUS_H_
68f5df1827Smickey 
698f2e613aSoga #include <sys/mutex.h>
703d6bf9c2Soga #include <sys/tree.h>
718f2e613aSoga 
72f5df1827Smickey #include <machine/pio.h>
73f5df1827Smickey 
74f5df1827Smickey /*
75f5df1827Smickey  * Bus address and size types
76f5df1827Smickey  */
77f5df1827Smickey typedef u_long bus_addr_t;
78f5df1827Smickey typedef u_long bus_size_t;
79f5df1827Smickey 
80f5df1827Smickey /*
81f5df1827Smickey  * Access methods for bus resources and address space.
82f5df1827Smickey  */
8393c7b57cSdlg struct x86_bus_space_ops;
8493c7b57cSdlg typedef	const struct x86_bus_space_ops *bus_space_tag_t;
85f5df1827Smickey typedef	u_long bus_space_handle_t;
86f5df1827Smickey 
8799afcea1Sderaadt int	bus_space_map(bus_space_tag_t t, bus_addr_t addr,
88f5df1827Smickey     bus_size_t size, int flags, bus_space_handle_t *bshp);
89f5df1827Smickey /* like map, but without extent map checking/allocation */
9099afcea1Sderaadt int	_bus_space_map(bus_space_tag_t t, bus_addr_t addr,
91f5df1827Smickey     bus_size_t size, int flags, bus_space_handle_t *bshp);
92f5df1827Smickey 
9399afcea1Sderaadt int	bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart,
9407083fbcSmarco 	    bus_addr_t rend, bus_size_t size, bus_size_t align,
9507083fbcSmarco 	    bus_size_t boundary, int flags, bus_addr_t *addrp,
9607083fbcSmarco 	    bus_space_handle_t *bshp);
9799afcea1Sderaadt void	bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh,
9807083fbcSmarco 	    bus_size_t size);
9907083fbcSmarco 
100f5df1827Smickey /*
101f5df1827Smickey  *      int bus_space_unmap(bus_space_tag_t t,
102f5df1827Smickey  *          bus_space_handle_t bsh, bus_size_t size);
103f5df1827Smickey  *
104f5df1827Smickey  * Unmap a region of bus space.
105f5df1827Smickey  */
106f5df1827Smickey 
10799afcea1Sderaadt void	bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
108f5df1827Smickey 	    bus_size_t size);
10999afcea1Sderaadt void	_bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh,
110f5df1827Smickey 	    bus_size_t size, bus_addr_t *);
111f5df1827Smickey 
112f5df1827Smickey /* like bus_space_map(), but without extent map checking/allocation */
113f5df1827Smickey int	_bus_space_map(bus_space_tag_t t, bus_addr_t addr,
1142ab138fdSmiod 	    bus_size_t size, int flags, bus_space_handle_t *bshp);
115f5df1827Smickey 
116f5df1827Smickey /*
117f5df1827Smickey  *      int bus_space_subregion(bus_space_tag_t t,
118f5df1827Smickey  *          bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
119f5df1827Smickey  *          bus_space_handle_t *nbshp);
120f5df1827Smickey  *
121f5df1827Smickey  * Get a new handle for a subregion of an already-mapped area of bus space.
122f5df1827Smickey  */
123f5df1827Smickey 
12499afcea1Sderaadt int	bus_space_subregion(bus_space_tag_t t, bus_space_handle_t bsh,
125f5df1827Smickey 	    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp);
126f5df1827Smickey 
12793c7b57cSdlg struct x86_bus_space_ops {
12893c7b57cSdlg 
129f5df1827Smickey /*
130f5df1827Smickey  *	u_intN_t bus_space_read_N(bus_space_tag_t tag,
131f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset);
132f5df1827Smickey  *
133f5df1827Smickey  * Read a 1, 2, 4, or 8 byte quantity from bus space
134f5df1827Smickey  * described by tag/handle/offset.
135f5df1827Smickey  */
13693c7b57cSdlg 	u_int8_t	(*read_1)(bus_space_handle_t, bus_size_t);
13793c7b57cSdlg 	u_int16_t	(*read_2)(bus_space_handle_t, bus_size_t);
13893c7b57cSdlg 	u_int32_t	(*read_4)(bus_space_handle_t, bus_size_t);
13993c7b57cSdlg 	u_int64_t	(*read_8)(bus_space_handle_t, bus_size_t);
140f5df1827Smickey 
14193c7b57cSdlg #define bus_space_read_1(_t, _h, _o) ((_t)->read_1((_h), (_o)))
14293c7b57cSdlg #define bus_space_read_2(_t, _h, _o) ((_t)->read_2((_h), (_o)))
14393c7b57cSdlg #define bus_space_read_4(_t, _h, _o) ((_t)->read_4((_h), (_o)))
14493c7b57cSdlg #define bus_space_read_8(_t, _h, _o) ((_t)->read_8((_h), (_o)))
145f5df1827Smickey 
146aacc3e86Sdlg #define bus_space_read_raw_2(_t, _h, _o) ((_t)->read_2((_h), (_o)))
147aacc3e86Sdlg #define bus_space_read_raw_4(_t, _h, _o) ((_t)->read_4((_h), (_o)))
148aacc3e86Sdlg #define bus_space_read_raw_8(_t, _h, _o) ((_t)->read_8((_h), (_o)))
149aacc3e86Sdlg 
150f5df1827Smickey /*
151f5df1827Smickey  *	void bus_space_read_multi_N(bus_space_tag_t tag,
152f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
153f5df1827Smickey  *	    u_intN_t *addr, size_t count);
154f5df1827Smickey  *
155f5df1827Smickey  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
156f5df1827Smickey  * described by tag/handle/offset and copy into buffer provided.
157f5df1827Smickey  */
158f5df1827Smickey 
15993c7b57cSdlg 	void		(*read_multi_1)(bus_space_handle_t, bus_size_t,
160ebbaad44Soga 			    u_int8_t *, bus_size_t);
16193c7b57cSdlg 	void		(*read_multi_2)(bus_space_handle_t, bus_size_t,
162ebbaad44Soga 			    u_int16_t *, bus_size_t);
16393c7b57cSdlg 	void		(*read_multi_4)(bus_space_handle_t, bus_size_t,
164ebbaad44Soga 			    u_int32_t *, bus_size_t);
16593c7b57cSdlg 	void		(*read_multi_8)(bus_space_handle_t, bus_size_t,
1669f2791f2Sdlg 			    u_int64_t *, bus_size_t);
167f5df1827Smickey 
16893c7b57cSdlg #define bus_space_read_multi_1(_t, _h, _o, _a, _c) \
16993c7b57cSdlg 	((_t)->read_multi_1((_h), (_o), (_a), (_c)))
17093c7b57cSdlg #define bus_space_read_multi_2(_t, _h, _o, _a, _c) \
17193c7b57cSdlg 	((_t)->read_multi_2((_h), (_o), (_a), (_c)))
17293c7b57cSdlg #define bus_space_read_multi_4(_t, _h, _o, _a, _c) \
17393c7b57cSdlg 	((_t)->read_multi_4((_h), (_o), (_a), (_c)))
17493c7b57cSdlg #define bus_space_read_multi_8(_t, _h, _o, _a, _c) \
17593c7b57cSdlg 	((_t)->read_multi_8((_h), (_o), (_a), (_c)))
17693c7b57cSdlg 
177f5df1827Smickey /*
178f5df1827Smickey  *	void bus_space_read_raw_multi_N(bus_space_tag_t tag,
179f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
180f5df1827Smickey  *	    u_int8_t *addr, size_t count);
181f5df1827Smickey  *
182f5df1827Smickey  * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
183f5df1827Smickey  * described by tag/handle/offset and copy into buffer provided.  The buffer
184f5df1827Smickey  * must have proper alignment for the N byte wide entities.  Furthermore
185f5df1827Smickey  * possible byte-swapping should be done by these functions.
186f5df1827Smickey  */
187f5df1827Smickey 
18893c7b57cSdlg #define bus_space_read_raw_multi_2(_t, _h, _o, _a, _c) \
18993c7b57cSdlg 	((_t)->read_multi_2((_h), (_o), (u_int16_t *)(_a), (_c) >> 1))
19093c7b57cSdlg #define bus_space_read_raw_multi_4(_t, _h, _o, _a, _c) \
19193c7b57cSdlg 	((_t)->read_multi_4((_h), (_o), (u_int32_t *)(_a), (_c) >> 2))
19293c7b57cSdlg #define bus_space_read_raw_multi_8(_t, _h, _o, _a, _c) \
19393c7b57cSdlg 	((_t)->read_multi_8((_h), (_o), (u_int64_t *)(_a), (_c) >> 3))
194f5df1827Smickey 
195f5df1827Smickey /*
196f5df1827Smickey  *	void bus_space_read_region_N(bus_space_tag_t tag,
197f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
198f5df1827Smickey  *	    u_intN_t *addr, size_t count);
199f5df1827Smickey  *
200f5df1827Smickey  * Read `count' 1, 2, 4, or 8 byte quantities from bus space
201f5df1827Smickey  * described by tag/handle and starting at `offset' and copy into
202f5df1827Smickey  * buffer provided.
203f5df1827Smickey  */
204f5df1827Smickey 
20593c7b57cSdlg 	void		(*read_region_1)(bus_space_handle_t,
206ebbaad44Soga 			    bus_size_t, u_int8_t *, bus_size_t);
20793c7b57cSdlg 	void		(*read_region_2)(bus_space_handle_t,
208ebbaad44Soga 			    bus_size_t, u_int16_t *, bus_size_t);
20993c7b57cSdlg 	void		(*read_region_4)(bus_space_handle_t,
210ebbaad44Soga 			    bus_size_t, u_int32_t *, bus_size_t);
21193c7b57cSdlg 	void		(*read_region_8)(bus_space_handle_t,
2129f2791f2Sdlg 			    bus_size_t, u_int64_t *, bus_size_t);
213f5df1827Smickey 
21493c7b57cSdlg #define bus_space_read_region_1(_t, _h, _o, _a, _c) \
21593c7b57cSdlg 	((_t)->read_region_1((_h), (_o), (_a), (_c)))
21693c7b57cSdlg #define bus_space_read_region_2(_t, _h, _o, _a, _c) \
21793c7b57cSdlg 	((_t)->read_region_2((_h), (_o), (_a), (_c)))
21893c7b57cSdlg #define bus_space_read_region_4(_t, _h, _o, _a, _c) \
21993c7b57cSdlg 	((_t)->read_region_4((_h), (_o), (_a), (_c)))
22093c7b57cSdlg #define bus_space_read_region_8(_t, _h, _o, _a, _c) \
22193c7b57cSdlg 	((_t)->read_region_8((_h), (_o), (_a), (_c)))
22293c7b57cSdlg 
223f5df1827Smickey /*
224f5df1827Smickey  *	void bus_space_read_raw_region_N(bus_space_tag_t tag,
225f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
226f5df1827Smickey  *	    u_int8_t *addr, size_t count);
227f5df1827Smickey  *
228f5df1827Smickey  * Read `count' bytes in 2, 4 or 8 byte wide quantities from bus space
229f5df1827Smickey  * described by tag/handle and starting at `offset' and copy into
230f5df1827Smickey  * buffer provided.  The buffer must have proper alignment for the N byte
231f5df1827Smickey  * wide entities.  Furthermore possible byte-swapping should be done by
232f5df1827Smickey  * these functions.
233f5df1827Smickey  */
234f5df1827Smickey 
23593c7b57cSdlg #define bus_space_read_raw_region_2(_t, _h, _o, _a, _c) \
23693c7b57cSdlg 	((_t)->read_region_2((_h), (_o), (u_int16_t *)(_a), (_c) >> 1))
23793c7b57cSdlg #define bus_space_read_raw_region_4(_t, _h, _o, _a, _c) \
23893c7b57cSdlg 	((_t)->read_region_4((_h), (_o), (u_int32_t *)(_a), (_c) >> 2))
23993c7b57cSdlg #define bus_space_read_raw_region_8(_t, _h, _o, _a, _c) \
24093c7b57cSdlg 	((_t)->read_region_8((_h), (_o), (u_int64_t *)(_a), (_c) >> 3))
241f5df1827Smickey 
242f5df1827Smickey /*
243f5df1827Smickey  *	void bus_space_write_N(bus_space_tag_t tag,
244f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
245f5df1827Smickey  *	    u_intN_t value);
246f5df1827Smickey  *
247f5df1827Smickey  * Write the 1, 2, 4, or 8 byte value `value' to bus space
248f5df1827Smickey  * described by tag/handle/offset.
249f5df1827Smickey  */
250f5df1827Smickey 
25193c7b57cSdlg 	void		(*write_1)(bus_space_handle_t, bus_size_t, u_int8_t);
25293c7b57cSdlg 	void		(*write_2)(bus_space_handle_t, bus_size_t, u_int16_t);
25393c7b57cSdlg 	void		(*write_4)(bus_space_handle_t, bus_size_t, u_int32_t);
25493c7b57cSdlg 	void		(*write_8)(bus_space_handle_t, bus_size_t, u_int64_t);
25593c7b57cSdlg 
25693c7b57cSdlg #define bus_space_write_1(_t, _h, _o, _v) \
25793c7b57cSdlg 	((_t)->write_1((_h), (_o), (_v)))
25893c7b57cSdlg #define bus_space_write_2(_t, _h, _o, _v) \
25993c7b57cSdlg 	((_t)->write_2((_h), (_o), (_v)))
26093c7b57cSdlg #define bus_space_write_4(_t, _h, _o, _v) \
26193c7b57cSdlg 	((_t)->write_4((_h), (_o), (_v)))
26293c7b57cSdlg #define bus_space_write_8(_t, _h, _o, _v) \
26393c7b57cSdlg 	((_t)->write_8((_h), (_o), (_v)))
264f5df1827Smickey 
265aacc3e86Sdlg #define bus_space_write_raw_2(_t, _h, _o, _v) \
266aacc3e86Sdlg 	((_t)->write_2((_h), (_o), (_v)))
267aacc3e86Sdlg #define bus_space_write_raw_4(_t, _h, _o, _v) \
268aacc3e86Sdlg 	((_t)->write_4((_h), (_o), (_v)))
269aacc3e86Sdlg #define bus_space_write_raw_8(_t, _h, _o, _v) \
270aacc3e86Sdlg 	((_t)->write_8((_h), (_o), (_v)))
271aacc3e86Sdlg 
272f5df1827Smickey /*
273f5df1827Smickey  *	void bus_space_write_multi_N(bus_space_tag_t tag,
274f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
275f5df1827Smickey  *	    const u_intN_t *addr, size_t count);
276f5df1827Smickey  *
277f5df1827Smickey  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
278f5df1827Smickey  * provided to bus space described by tag/handle/offset.
279f5df1827Smickey  */
280f5df1827Smickey 
28193c7b57cSdlg 	void		(*write_multi_1)(bus_space_handle_t,
282ebbaad44Soga 			    bus_size_t, const u_int8_t *, bus_size_t);
28393c7b57cSdlg 	void		(*write_multi_2)(bus_space_handle_t,
284ebbaad44Soga 			    bus_size_t, const u_int16_t *, bus_size_t);
28593c7b57cSdlg 	void		(*write_multi_4)(bus_space_handle_t,
286ebbaad44Soga 			    bus_size_t, const u_int32_t *, bus_size_t);
28793c7b57cSdlg 	void		(*write_multi_8)(bus_space_handle_t,
2889f2791f2Sdlg 			    bus_size_t, const u_int64_t *, bus_size_t);
289f5df1827Smickey 
29093c7b57cSdlg #define bus_space_write_multi_1(_t, _h, _o, _a, _c) \
29193c7b57cSdlg 	((_t)->write_multi_1((_h), (_o), (_a), (_c)))
29293c7b57cSdlg #define bus_space_write_multi_2(_t, _h, _o, _a, _c) \
29393c7b57cSdlg 	((_t)->write_multi_2((_h), (_o), (_a), (_c)))
29493c7b57cSdlg #define bus_space_write_multi_4(_t, _h, _o, _a, _c) \
29593c7b57cSdlg 	((_t)->write_multi_4((_h), (_o), (_a), (_c)))
29693c7b57cSdlg #define bus_space_write_multi_8(_t, _h, _o, _a, _c) \
29793c7b57cSdlg 	((_t)->write_multi_8((_h), (_o), (_a), (_c)))
29893c7b57cSdlg 
299f5df1827Smickey /*
300f5df1827Smickey  *	void bus_space_write_raw_multi_N(bus_space_tag_t tag,
301f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
302f5df1827Smickey  *	    const u_int8_t *addr, size_t count);
303f5df1827Smickey  *
304f5df1827Smickey  * Write `count' bytes in 2, 4 or 8 byte wide quantities from the buffer
305f5df1827Smickey  * provided to bus space described by tag/handle/offset.  The buffer
306f5df1827Smickey  * must have proper alignment for the N byte wide entities.  Furthermore
307f5df1827Smickey  * possible byte-swapping should be done by these functions.
308f5df1827Smickey  */
309f5df1827Smickey 
31093c7b57cSdlg #define bus_space_write_raw_multi_2(_t, _h, _o, _a, _c) \
31193c7b57cSdlg 	((_t)->write_multi_2((_h), (_o), (const u_int16_t *)(_a), (_c) >> 1))
31293c7b57cSdlg #define bus_space_write_raw_multi_4(_t, _h, _o, _a, _c) \
31393c7b57cSdlg 	((_t)->write_multi_4((_h), (_o), (const u_int32_t *)(_a), (_c) >> 2))
31493c7b57cSdlg #define bus_space_write_raw_multi_8(_t, _h, _o, _a, _c) \
31593c7b57cSdlg 	((_t)->write_multi_8((_h), (_o), (const u_int64_t *)(_a), (_c) >> 3))
316f5df1827Smickey 
317f5df1827Smickey /*
318f5df1827Smickey  *	void bus_space_write_region_N(bus_space_tag_t tag,
319f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
320f5df1827Smickey  *	    const u_intN_t *addr, size_t count);
321f5df1827Smickey  *
322f5df1827Smickey  * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
323f5df1827Smickey  * to bus space described by tag/handle starting at `offset'.
324f5df1827Smickey  */
325f5df1827Smickey 
32693c7b57cSdlg 	void		(*write_region_1)(bus_space_handle_t,
327ebbaad44Soga 			    bus_size_t, const u_int8_t *, bus_size_t);
32893c7b57cSdlg 	void		(*write_region_2)(bus_space_handle_t,
329ebbaad44Soga 			    bus_size_t, const u_int16_t *, bus_size_t);
33093c7b57cSdlg 	void		(*write_region_4)(bus_space_handle_t,
331ebbaad44Soga 			    bus_size_t, const u_int32_t *, bus_size_t);
33293c7b57cSdlg 	void		(*write_region_8)(bus_space_handle_t,
3339f2791f2Sdlg 			    bus_size_t, const u_int64_t *, bus_size_t);
334f5df1827Smickey 
33593c7b57cSdlg #define bus_space_write_region_1(_t, _h, _o, _a, _c) \
33693c7b57cSdlg 	((_t)->write_region_1((_h), (_o), (_a), (_c)))
33793c7b57cSdlg #define bus_space_write_region_2(_t, _h, _o, _a, _c) \
33893c7b57cSdlg 	((_t)->write_region_2((_h), (_o), (_a), (_c)))
33993c7b57cSdlg #define bus_space_write_region_4(_t, _h, _o, _a, _c) \
34093c7b57cSdlg 	((_t)->write_region_4((_h), (_o), (_a), (_c)))
34193c7b57cSdlg #define bus_space_write_region_8(_t, _h, _o, _a, _c) \
34293c7b57cSdlg 	((_t)->write_region_8((_h), (_o), (_a), (_c)))
34393c7b57cSdlg 
344f5df1827Smickey /*
345f5df1827Smickey  *	void bus_space_write_raw_region_N(bus_space_tag_t tag,
346f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
347f5df1827Smickey  *	    const u_int8_t *addr, size_t count);
348f5df1827Smickey  *
349f5df1827Smickey  * Write `count' bytes in 2, 4 or 8 byte wide quantities to bus space
350f5df1827Smickey  * described by tag/handle and starting at `offset' from the
351f5df1827Smickey  * buffer provided.  The buffer must have proper alignment for the N byte
352f5df1827Smickey  * wide entities.  Furthermore possible byte-swapping should be done by
353f5df1827Smickey  * these functions.
354f5df1827Smickey  */
355f5df1827Smickey 
35693c7b57cSdlg #define bus_space_write_raw_region_2(_t, _h, _o, _a, _c) \
35793c7b57cSdlg 	((_t)->write_region_2((_h), (_o), (const u_int16_t *)(_a), (_c) >> 1))
35893c7b57cSdlg #define bus_space_write_raw_region_4(_t, _h, _o, _a, _c) \
35993c7b57cSdlg 	((_t)->write_region_4((_h), (_o), (const u_int32_t *)(_a), (_c) >> 2))
36093c7b57cSdlg #define bus_space_write_raw_region_8(_t, _h, _o, _a, _c) \
36193c7b57cSdlg 	((_t)->write_region_8((_h), (_o), (const u_int64_t *)(_a), (_c) >> 3))
362f5df1827Smickey 
363f5df1827Smickey /*
364f5df1827Smickey  *	void bus_space_set_multi_N(bus_space_tag_t tag,
365f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
366f5df1827Smickey  *	    u_intN_t val, size_t count);
367f5df1827Smickey  *
368f5df1827Smickey  * Write the 1, 2, 4, or 8 byte value `val' to bus space described
369f5df1827Smickey  * by tag/handle/offset `count' times.
370f5df1827Smickey  */
371f5df1827Smickey 
37293c7b57cSdlg 	void		(*set_multi_1)(bus_space_handle_t,
373ebbaad44Soga 			    bus_size_t, u_int8_t, size_t);
37493c7b57cSdlg 	void		(*set_multi_2)(bus_space_handle_t,
375ebbaad44Soga 			    bus_size_t, u_int16_t, size_t);
37693c7b57cSdlg 	void		(*set_multi_4)(bus_space_handle_t,
377ebbaad44Soga 			    bus_size_t, u_int32_t, size_t);
37893c7b57cSdlg 	void		(*set_multi_8)(bus_space_handle_t,
3799f2791f2Sdlg 			    bus_size_t, u_int64_t, size_t);
380f5df1827Smickey 
38193c7b57cSdlg #define bus_space_set_multi_1(_t, _h, _o, _a, _c) \
38293c7b57cSdlg 	((_t)->set_multi_1((_h), (_o), (_a), (_c)))
38393c7b57cSdlg #define bus_space_set_multi_2(_t, _h, _o, _a, _c) \
38493c7b57cSdlg 	((_t)->set_multi_2((_h), (_o), (_a), (_c)))
38593c7b57cSdlg #define bus_space_set_multi_4(_t, _h, _o, _a, _c) \
38693c7b57cSdlg 	((_t)->set_multi_4((_h), (_o), (_a), (_c)))
38793c7b57cSdlg #define bus_space_set_multi_8(_t, _h, _o, _a, _c) \
38893c7b57cSdlg 	((_t)->set_multi_8((_h), (_o), (_a), (_c)))
38993c7b57cSdlg 
390f5df1827Smickey /*
391f5df1827Smickey  *	void bus_space_set_region_N(bus_space_tag_t tag,
392f5df1827Smickey  *	    bus_space_handle_t bsh, bus_size_t offset,
393f5df1827Smickey  *	    u_intN_t val, size_t count);
394f5df1827Smickey  *
395f5df1827Smickey  * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
396f5df1827Smickey  * by tag/handle starting at `offset'.
397f5df1827Smickey  */
398f5df1827Smickey 
39993c7b57cSdlg 	void		(*set_region_1)(bus_space_handle_t,
400ebbaad44Soga 			    bus_size_t, u_int8_t, size_t);
40193c7b57cSdlg 	void		(*set_region_2)(bus_space_handle_t,
402ebbaad44Soga 			    bus_size_t, u_int16_t, size_t);
40393c7b57cSdlg 	void		(*set_region_4)(bus_space_handle_t,
404ebbaad44Soga 			    bus_size_t, u_int32_t, size_t);
40593c7b57cSdlg 	void		(*set_region_8)(bus_space_handle_t,
4069f2791f2Sdlg 			    bus_size_t, u_int64_t, size_t);
407f5df1827Smickey 
40893c7b57cSdlg #define bus_space_set_region_1(_t, _h, _o, _a, _c) \
40993c7b57cSdlg 	((_t)->set_region_1((_h), (_o), (_a), (_c)))
41093c7b57cSdlg #define bus_space_set_region_2(_t, _h, _o, _a, _c) \
41193c7b57cSdlg 	((_t)->set_region_2((_h), (_o), (_a), (_c)))
41293c7b57cSdlg #define bus_space_set_region_4(_t, _h, _o, _a, _c) \
41393c7b57cSdlg 	((_t)->set_region_4((_h), (_o), (_a), (_c)))
41493c7b57cSdlg #define bus_space_set_region_8(_t, _h, _o, _a, _c) \
41593c7b57cSdlg 	((_t)->set_region_8((_h), (_o), (_a), (_c)))
41693c7b57cSdlg 
417f5df1827Smickey /*
418f5df1827Smickey  *	void bus_space_copy_N(bus_space_tag_t tag,
419f5df1827Smickey  *	    bus_space_handle_t bsh1, bus_size_t off1,
420f5df1827Smickey  *	    bus_space_handle_t bsh2, bus_size_t off2,
421f5df1827Smickey  *	    size_t count);
422f5df1827Smickey  *
423f5df1827Smickey  * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
424f5df1827Smickey  * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
425f5df1827Smickey  */
426f5df1827Smickey 
42793c7b57cSdlg 	void		(*copy_1)(bus_space_handle_t,
428ebbaad44Soga 			    bus_size_t, bus_space_handle_t, bus_size_t, size_t);
42993c7b57cSdlg 	void		(*copy_2)(bus_space_handle_t,
430ebbaad44Soga 			    bus_size_t, bus_space_handle_t, bus_size_t, size_t);
43193c7b57cSdlg 	void		(*copy_4)(bus_space_handle_t,
432ebbaad44Soga 			    bus_size_t, bus_space_handle_t, bus_size_t, size_t);
43393c7b57cSdlg 	void		(*copy_8)(bus_space_handle_t,
4349f2791f2Sdlg 			    bus_size_t, bus_space_handle_t, bus_size_t, size_t);
435f5df1827Smickey 
43693c7b57cSdlg #define bus_space_copy_1(_t, _h1, _o1, _h2, _o2, _c) \
43793c7b57cSdlg 	((_t)->copy_1((_h1), (_o1), (_h2), (_o2), (_c)))
43893c7b57cSdlg #define bus_space_copy_2(_t, _h1, _o1, _h2, _o2, _c) \
43993c7b57cSdlg 	((_t)->copy_2((_h1), (_o1), (_h2), (_o2), (_c)))
44093c7b57cSdlg #define bus_space_copy_4(_t, _h1, _o1, _h2, _o2, _c) \
44193c7b57cSdlg 	((_t)->copy_4((_h1), (_o1), (_h2), (_o2), (_c)))
44293c7b57cSdlg #define bus_space_copy_8(_t, _h1, _o1, _h2, _o2, _c) \
44393c7b57cSdlg 	((_t)->copy_8((_h1), (_o1), (_h2), (_o2), (_c)))
444515b194eSmarco 
445515b194eSmarco /*
446515b194eSmarco  *	void *bus_space_vaddr(bus_space_tag_t, bus_space_handle_t);
447515b194eSmarco  *
448515b194eSmarco  * Get the kernel virtual address for the mapped bus space.
449515b194eSmarco  * Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR.
450515b194eSmarco  */
45193c7b57cSdlg 	void *		(*vaddr)(bus_space_handle_t);
45293c7b57cSdlg 
45393c7b57cSdlg #define bus_space_vaddr(_t, _h) \
45493c7b57cSdlg 	((_t)->vaddr((_h)))
45593c7b57cSdlg 
45693c7b57cSdlg /*
45793c7b57cSdlg  *      paddr_t bus_space_mmap(bus_space_tag_t t, bus_addr_t base,
45893c7b57cSdlg  *          off_t offset, int prot, int flags);
45993c7b57cSdlg  *
46093c7b57cSdlg  * Mmap an area of bus space.
46193c7b57cSdlg  */
46293c7b57cSdlg 
46393c7b57cSdlg 	paddr_t		(*mmap)(bus_addr_t, off_t, int, int);
46493c7b57cSdlg 
46593c7b57cSdlg #define bus_space_mmap(_t, _a, _o, _p, _f) \
46693c7b57cSdlg 	((_t)->mmap((_a), (_o), (_p), (_f)))
46793c7b57cSdlg };
46893c7b57cSdlg 
46993c7b57cSdlg /*
47093c7b57cSdlg  * Bus read/write barrier methods.
47193c7b57cSdlg  */
47293c7b57cSdlg #define	BUS_SPACE_BARRIER_READ	0x01		/* force read barrier */
47393c7b57cSdlg #define	BUS_SPACE_BARRIER_WRITE	0x02		/* force write barrier */
47493c7b57cSdlg 
47593c7b57cSdlg static inline void
47693c7b57cSdlg bus_space_barrier(bus_space_tag_t space, bus_space_handle_t
47793c7b57cSdlg     handle, bus_size_t offset, bus_size_t length, int flags)
47893c7b57cSdlg {
47993c7b57cSdlg 	switch (flags) {
48093c7b57cSdlg 	case (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE):
481157282f2Sjsg 		__asm volatile("mfence" ::: "memory");
48293c7b57cSdlg 		break;
48393c7b57cSdlg 	case BUS_SPACE_BARRIER_WRITE:
484157282f2Sjsg 		__asm volatile("sfence" ::: "memory");
48593c7b57cSdlg 		break;
48693c7b57cSdlg 	default:
487157282f2Sjsg 		__asm volatile("lfence" ::: "memory");
48893c7b57cSdlg 		break;
48993c7b57cSdlg 	}
49093c7b57cSdlg }
49193c7b57cSdlg 
49293c7b57cSdlg #define	BUS_SPACE_MAP_CACHEABLE		0x0001
49393c7b57cSdlg #define	BUS_SPACE_MAP_LINEAR		0x0002
49493c7b57cSdlg #define	BUS_SPACE_MAP_PREFETCHABLE	0x0008
49593c7b57cSdlg 
49693c7b57cSdlg /*
49793c7b57cSdlg  * Values for the x86 bus space tag, not to be used directly by MI code.
49893c7b57cSdlg  */
49993c7b57cSdlg 
50093c7b57cSdlg /* space is i/o space */
50193c7b57cSdlg extern const struct x86_bus_space_ops x86_bus_space_io_ops;
50293c7b57cSdlg #define	X86_BUS_SPACE_IO	(&x86_bus_space_io_ops)
50393c7b57cSdlg 
50493c7b57cSdlg /* space is mem space */
50593c7b57cSdlg extern const struct x86_bus_space_ops x86_bus_space_mem_ops;
50693c7b57cSdlg #define X86_BUS_SPACE_MEM	(&x86_bus_space_mem_ops)
50793c7b57cSdlg 
50893c7b57cSdlg /*
50993c7b57cSdlg  * bus_dma
51093c7b57cSdlg  */
51193c7b57cSdlg 
512f5df1827Smickey /*
513f5df1827Smickey  * Flags used in various bus DMA methods.
514f5df1827Smickey  */
515471ccd18Soga #define	BUS_DMA_WAITOK		0x0000	/* safe to sleep (pseudo-flag) */
516471ccd18Soga #define	BUS_DMA_NOWAIT		0x0001	/* not safe to sleep */
517471ccd18Soga #define	BUS_DMA_ALLOCNOW	0x0002	/* perform resource allocation now */
518471ccd18Soga #define	BUS_DMA_COHERENT	0x0004	/* hint: map memory DMA coherent */
519471ccd18Soga #define	BUS_DMA_BUS1		0x0010	/* placeholders for bus functions... */
520471ccd18Soga #define	BUS_DMA_BUS2		0x0020
521471ccd18Soga #define	BUS_DMA_32BIT		0x0040
522471ccd18Soga #define	BUS_DMA_24BIT		0x0080	/* isadma map */
523471ccd18Soga #define	BUS_DMA_STREAMING	0x0100	/* hint: sequential, unidirectional */
524471ccd18Soga #define	BUS_DMA_READ		0x0200	/* mapping is device -> memory only */
525471ccd18Soga #define	BUS_DMA_WRITE		0x0400	/* mapping is memory -> device only */
526471ccd18Soga #define	BUS_DMA_NOCACHE		0x0800	/* map memory uncached */
527471ccd18Soga #define	BUS_DMA_ZERO		0x1000	/* zero memory in dmamem_alloc */
528b0002153Sdlg #define	BUS_DMA_64BIT		0x2000	/* device handles 64bit dva */
529d4ee1f8dSoga 
530f5df1827Smickey /* Forwards needed by prototypes below. */
531f5df1827Smickey struct mbuf;
532f5df1827Smickey struct proc;
533f5df1827Smickey struct uio;
534f5df1827Smickey 
535f5df1827Smickey /*
536f5df1827Smickey  * Operations performed by bus_dmamap_sync().
537f5df1827Smickey  */
538f5df1827Smickey #define BUS_DMASYNC_PREREAD	0x01
539f5df1827Smickey #define BUS_DMASYNC_POSTREAD	0x02
540f5df1827Smickey #define BUS_DMASYNC_PREWRITE	0x04
541f5df1827Smickey #define BUS_DMASYNC_POSTWRITE	0x08
542f5df1827Smickey 
54313fad3d0Soga typedef struct bus_dma_tag		*bus_dma_tag_t;
54413fad3d0Soga typedef struct bus_dmamap		*bus_dmamap_t;
545f5df1827Smickey 
546f5df1827Smickey /*
547f5df1827Smickey  *	bus_dma_segment_t
548f5df1827Smickey  *
549f5df1827Smickey  *	Describes a single contiguous DMA transaction.  Values
550f5df1827Smickey  *	are suitable for programming into DMA registers.
551f5df1827Smickey  */
55213fad3d0Soga struct bus_dma_segment {
553f5df1827Smickey 	bus_addr_t	ds_addr;	/* DMA address */
554f5df1827Smickey 	bus_size_t	ds_len;		/* length of transfer */
555*d5a984e5Sbluhm 	vaddr_t		_ds_va;		/* mapped loaded data */
556*d5a984e5Sbluhm 	vaddr_t		_ds_bounce_va;	/* mapped bounced data */
557*d5a984e5Sbluhm 
5588f2e613aSoga 	/*
5598f2e613aSoga 	 * Ugh. need this so can pass alignment down from bus_dmamem_alloc
5608f2e613aSoga 	 * to scatter gather maps. only the first one is used so the rest is
5618f2e613aSoga 	 * wasted space. bus_dma could do with fixing the api for this.
5628f2e613aSoga 	 */
5638f2e613aSoga 	 bus_size_t	_ds_boundary;	/* don't cross */
5648f2e613aSoga 	 bus_size_t	_ds_align;	/* align to me */
565f5df1827Smickey };
56613fad3d0Soga typedef struct bus_dma_segment	bus_dma_segment_t;
567f5df1827Smickey 
568f5df1827Smickey /*
569f5df1827Smickey  *	bus_dma_tag_t
570f5df1827Smickey  *
571f5df1827Smickey  *	A machine-dependent opaque type describing the implementation of
572f5df1827Smickey  *	DMA for a given bus.
573f5df1827Smickey  */
574f5df1827Smickey 
57513fad3d0Soga struct bus_dma_tag {
576f5df1827Smickey 	void	*_cookie;		/* cookie used in the guts */
577f5df1827Smickey 
578f5df1827Smickey 	/*
579f5df1827Smickey 	 * DMA mapping methods.
580f5df1827Smickey 	 */
581f5df1827Smickey 	int	(*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
582f5df1827Smickey 		    bus_size_t, bus_size_t, int, bus_dmamap_t *);
583f5df1827Smickey 	void	(*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
584f5df1827Smickey 	int	(*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
585f5df1827Smickey 		    bus_size_t, struct proc *, int);
586f5df1827Smickey 	int	(*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
587f5df1827Smickey 		    struct mbuf *, int);
588f5df1827Smickey 	int	(*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
589f5df1827Smickey 		    struct uio *, int);
590f5df1827Smickey 	int	(*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
591f5df1827Smickey 		    bus_dma_segment_t *, int, bus_size_t, int);
592f5df1827Smickey 	void	(*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
593f5df1827Smickey 	void	(*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
594f5df1827Smickey 		    bus_addr_t, bus_size_t, int);
595f5df1827Smickey 
596f5df1827Smickey 	/*
597f5df1827Smickey 	 * DMA memory utility functions.
598f5df1827Smickey 	 */
599f5df1827Smickey 	int	(*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
600f5df1827Smickey 		    bus_size_t, bus_dma_segment_t *, int, int *, int);
6013df3eb3bSkettenis 	int	(*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t,
6023df3eb3bSkettenis 		    bus_size_t, bus_dma_segment_t *, int, int *, int,
6033df3eb3bSkettenis 		    bus_addr_t, bus_addr_t);
604f5df1827Smickey 	void	(*_dmamem_free)(bus_dma_tag_t,
605f5df1827Smickey 		    bus_dma_segment_t *, int);
606f5df1827Smickey 	int	(*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
607f5df1827Smickey 		    int, size_t, caddr_t *, int);
608f5df1827Smickey 	void	(*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
609f5df1827Smickey 	paddr_t	(*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
610f5df1827Smickey 		    int, off_t, int, int);
611f5df1827Smickey };
612f5df1827Smickey 
613f5df1827Smickey #define	bus_dmamap_create(t, s, n, m, b, f, p)			\
614f5df1827Smickey 	(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
615f5df1827Smickey #define	bus_dmamap_destroy(t, p)				\
616f5df1827Smickey 	(*(t)->_dmamap_destroy)((t), (p))
617f5df1827Smickey #define	bus_dmamap_load(t, m, b, s, p, f)			\
618f5df1827Smickey 	(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
619f5df1827Smickey #define	bus_dmamap_load_mbuf(t, m, b, f)			\
620f5df1827Smickey 	(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
621f5df1827Smickey #define	bus_dmamap_load_uio(t, m, u, f)				\
622f5df1827Smickey 	(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
623f5df1827Smickey #define	bus_dmamap_load_raw(t, m, sg, n, s, f)			\
624f5df1827Smickey 	(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
625f5df1827Smickey #define	bus_dmamap_unload(t, p)					\
626f5df1827Smickey 	(*(t)->_dmamap_unload)((t), (p))
627f5df1827Smickey #define	bus_dmamap_sync(t, p, o, l, ops)			\
628bcc3a45bSkettenis 	(*(t)->_dmamap_sync)((t), (p), (o), (l), (ops))
629f5df1827Smickey 
630f5df1827Smickey #define	bus_dmamem_alloc(t, s, a, b, sg, n, r, f)		\
631f5df1827Smickey 	(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
6323df3eb3bSkettenis #define	bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h)	\
6333df3eb3bSkettenis 	(*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg),	\
6343df3eb3bSkettenis 		(n), (r), (f), (l), (h))
635f5df1827Smickey #define	bus_dmamem_free(t, sg, n)				\
636f5df1827Smickey 	(*(t)->_dmamem_free)((t), (sg), (n))
637f5df1827Smickey #define	bus_dmamem_map(t, sg, n, s, k, f)			\
638f5df1827Smickey 	(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
639f5df1827Smickey #define	bus_dmamem_unmap(t, k, s)				\
640f5df1827Smickey 	(*(t)->_dmamem_unmap)((t), (k), (s))
641f5df1827Smickey #define	bus_dmamem_mmap(t, sg, n, o, p, f)			\
642f5df1827Smickey 	(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
643f5df1827Smickey 
644f5df1827Smickey /*
645f5df1827Smickey  *	bus_dmamap_t
646f5df1827Smickey  *
647f5df1827Smickey  *	Describes a DMA mapping.
648f5df1827Smickey  */
64913fad3d0Soga struct bus_dmamap {
650f5df1827Smickey 	/*
651da6a775aSjason 	 * PRIVATE MEMBERS: not for use by machine-independent code.
652f5df1827Smickey 	 */
653f5df1827Smickey 	bus_size_t	_dm_size;	/* largest DMA transfer mappable */
654eeb83a6bSsf 	int		_dm_flags;	/* misc. flags */
655f5df1827Smickey 	int		_dm_segcnt;	/* number of segs this map can map */
656f5df1827Smickey 	bus_size_t	_dm_maxsegsz;	/* largest possible segment */
657f5df1827Smickey 	bus_size_t	_dm_boundary;	/* don't cross this */
658f5df1827Smickey 
659f5df1827Smickey 	void		*_dm_cookie;	/* cookie for bus-specific functions */
660f5df1827Smickey 
661*d5a984e5Sbluhm 	struct vm_page **_dm_pages;	/* replacement pages */
662*d5a984e5Sbluhm 	vaddr_t		_dm_pgva;	/* those above -- mapped */
663*d5a984e5Sbluhm 	int		_dm_npages;	/* number of pages allocated */
664*d5a984e5Sbluhm 	int		_dm_nused;	/* number of pages replaced */
665*d5a984e5Sbluhm 
666f5df1827Smickey 	/*
667f5df1827Smickey 	 * PUBLIC MEMBERS: these are used by machine-independent code.
668f5df1827Smickey 	 */
669f5df1827Smickey 	bus_size_t	dm_mapsize;	/* size of the mapping */
670f5df1827Smickey 	int		dm_nsegs;	/* # valid segments in mapping */
671f5df1827Smickey 	bus_dma_segment_t dm_segs[1];	/* segments; variable length */
672f5df1827Smickey };
673f5df1827Smickey 
674f5df1827Smickey int	_bus_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
675f5df1827Smickey 	    bus_size_t, int, bus_dmamap_t *);
676f5df1827Smickey void	_bus_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
677f5df1827Smickey int	_bus_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
678f5df1827Smickey 	    bus_size_t, struct proc *, int);
679f5df1827Smickey int	_bus_dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t,
680f5df1827Smickey 	    struct mbuf *, int);
681f5df1827Smickey int	_bus_dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t,
682f5df1827Smickey 	    struct uio *, int);
683f5df1827Smickey int	_bus_dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
684f5df1827Smickey 	    bus_dma_segment_t *, int, bus_size_t, int);
685f5df1827Smickey void	_bus_dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
686f5df1827Smickey void	_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
687f5df1827Smickey 	    bus_size_t, int);
688f5df1827Smickey 
689f5df1827Smickey int	_bus_dmamem_alloc(bus_dma_tag_t tag, bus_size_t size,
690f5df1827Smickey 	    bus_size_t alignment, bus_size_t boundary,
691f5df1827Smickey 	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
692f5df1827Smickey void	_bus_dmamem_free(bus_dma_tag_t tag, bus_dma_segment_t *segs,
693f5df1827Smickey 	    int nsegs);
694f5df1827Smickey int	_bus_dmamem_map(bus_dma_tag_t tag, bus_dma_segment_t *segs,
695f5df1827Smickey 	    int nsegs, size_t size, caddr_t *kvap, int flags);
696f5df1827Smickey void	_bus_dmamem_unmap(bus_dma_tag_t tag, caddr_t kva,
697f5df1827Smickey 	    size_t size);
698f5df1827Smickey paddr_t	_bus_dmamem_mmap(bus_dma_tag_t tag, bus_dma_segment_t *segs,
699f5df1827Smickey 	    int nsegs, off_t off, int prot, int flags);
700f5df1827Smickey 
701f5df1827Smickey int	_bus_dmamem_alloc_range(bus_dma_tag_t tag, bus_size_t size,
702f5df1827Smickey 	    bus_size_t alignment, bus_size_t boundary,
703f5df1827Smickey 	    bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
7043df3eb3bSkettenis 	    bus_addr_t low, bus_addr_t high);
705f5df1827Smickey 
7062fa72412Spirofti #endif /* _MACHINE_BUS_H_ */
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