1*7b44a193Smiod.\" $OpenBSD: pci_mapreg_map.9,v 1.2 2023/04/13 15:07:42 miod Exp $ 240ad55d7Sdlg.\" 340ad55d7Sdlg.\" Copyright (c) 2019 David Gwynne <dlg@openbsd.org> 440ad55d7Sdlg.\" All rights reserved. 540ad55d7Sdlg.\" 640ad55d7Sdlg.\" Permission to use, copy, modify, and distribute this software for any 740ad55d7Sdlg.\" purpose with or without fee is hereby granted, provided that the above 840ad55d7Sdlg.\" copyright notice and this permission notice appear in all copies. 940ad55d7Sdlg.\" 1040ad55d7Sdlg.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1140ad55d7Sdlg.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1240ad55d7Sdlg.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1340ad55d7Sdlg.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1440ad55d7Sdlg.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1540ad55d7Sdlg.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1640ad55d7Sdlg.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1740ad55d7Sdlg.\" 18*7b44a193Smiod.Dd $Mdocdate: April 13 2023 $ 1940ad55d7Sdlg.Dt PCI_MAPREG_MAP 9 2040ad55d7Sdlg.Os 2140ad55d7Sdlg.Sh NAME 2240ad55d7Sdlg.Nm pci_mapreg_map , 2340ad55d7Sdlg.Nm pci_mapreg_info , 2440ad55d7Sdlg.Nm pci_mapreg_probe , 2540ad55d7Sdlg.Nm pci_mapreg_type 2640ad55d7Sdlg.Nd PCI register mappings 2740ad55d7Sdlg.Sh SYNOPSIS 2840ad55d7Sdlg.In dev/pci/pcivar.h 2940ad55d7Sdlg.Ft int 3040ad55d7Sdlg.Fo pci_mapreg_map 3140ad55d7Sdlg.Fa "struct pci_attach_args *paa" 3240ad55d7Sdlg.Fa "int reg" 3340ad55d7Sdlg.Fa "pcireg_t type" 3440ad55d7Sdlg.Fa "int flags" 3540ad55d7Sdlg.Fa "bus_space_tag_t *tagp" 3640ad55d7Sdlg.Fa "bus_space_handle_t *handlep" 3740ad55d7Sdlg.Fa "bus_addr_t *basep" 3840ad55d7Sdlg.Fa "bus_size_t *sizep" 3940ad55d7Sdlg.Fa "bus_size_t maxsize" 4040ad55d7Sdlg.Fc 4140ad55d7Sdlg.Ft int 4240ad55d7Sdlg.Fo pci_mapreg_info 4340ad55d7Sdlg.Fa "pci_chipset_tag_t pc" 4440ad55d7Sdlg.Fa "pcitag_t tag" 4540ad55d7Sdlg.Fa "int reg" 4640ad55d7Sdlg.Fa "pcireg_t type" 4740ad55d7Sdlg.Fa "bus_addr_t *basep" 4840ad55d7Sdlg.Fa "bus_size_t *sizep" 4940ad55d7Sdlg.Fa "int *flagsp" 5040ad55d7Sdlg.Fc 5140ad55d7Sdlg.Ft int 5240ad55d7Sdlg.Fo pci_mapreg_probe 5340ad55d7Sdlg.Fa "pci_chipset_tag_t pc" 5440ad55d7Sdlg.Fa "pcitag_t tag" 5540ad55d7Sdlg.Fa "int reg" 5640ad55d7Sdlg.Fa "pcireg_t *typep" 5740ad55d7Sdlg.Fc 5840ad55d7Sdlg.Ft pcireg_t 5940ad55d7Sdlg.Fo pci_mapreg_type 6040ad55d7Sdlg.Fa "pci_chipset_tag_t pc" 6140ad55d7Sdlg.Fa "pcitag_t tag" 6240ad55d7Sdlg.Fa "int reg" 6340ad55d7Sdlg.Fc 6440ad55d7Sdlg.Sh DESCRIPTION 6540ad55d7SdlgThese functions provide wrappers and helpers around 6640ad55d7Sdlg.Xr bus_space 9 6740ad55d7Sdlgmappings for device registers described by the Base Address Registers 6840ad55d7Sdlg(BARs) in a PCI devices configuration space. 6940ad55d7Sdlg.Pp 7040ad55d7Sdlg.Nm pci_mapreg_map 7140ad55d7Sdlgwraps a call to 7240ad55d7Sdlg.Xr bus_space_map 9 7340ad55d7Sdlgusing information from the BAR referenced by 7440ad55d7Sdlg.Fa reg 7540ad55d7Sdlgfor the device being attached with 7640ad55d7Sdlg.Fa paa . 7740ad55d7SdlgMemory or I/O mappings are derived from the 7840ad55d7Sdlg.Fa type 7940ad55d7Sdlgargument. 8040ad55d7SdlgThe size of the register mapping can be restricted by specifying a 8140ad55d7Sdlgnon-zero value in 8240ad55d7Sdlg.Fa maxsize . 8340ad55d7SdlgThe bus space tag and handle used for the mapping, as well 8440ad55d7Sdlgas the base address and size of the mapping, will be provided 8540ad55d7Sdlgto the caller via the optional 8640ad55d7Sdlg.Fa tagp , 8740ad55d7Sdlg.Fa handlep , 8840ad55d7Sdlg.Fa basep , 8940ad55d7Sdlgand 9040ad55d7Sdlg.Fa sizep 9140ad55d7Sdlgpointers. 9240ad55d7Sdlg.Pp 9340ad55d7Sdlg.Nm pci_mapreg_info 9440ad55d7Sdlgprovides bus space mapping information from the BAR referenced by 9540ad55d7Sdlg.Fa reg . 9640ad55d7SdlgThe 9740ad55d7Sdlg.Fa type 9840ad55d7Sdlgargument specifies whether the mapping provides Memory or I/O access. 9940ad55d7SdlgThe base address, size, and bus space flags are optionally provided 10040ad55d7Sdlgto the caller via the 10140ad55d7Sdlg.Fa basep , 10240ad55d7Sdlg.Fa sizep , 10340ad55d7Sdlgand 10440ad55d7Sdlg.Fa flagsp 10540ad55d7Sdlgpointers. 10640ad55d7Sdlg.Pp 10740ad55d7Sdlg.Nm pci_mapreg_probe 10840ad55d7Sdlgattempts to determine if the BAR referenced by 10940ad55d7Sdlg.Fa reg 11040ad55d7Sdlgdescribes a valid register mapping. 11140ad55d7Sdlg.Pp 11240ad55d7Sdlg.Nm pci_mapreg_type 11340ad55d7Sdlgreturns the type of register access for the registers at the BAR 11440ad55d7Sdlgreferenced by 11540ad55d7Sdlg.Fa reg . 11640ad55d7Sdlg.Sh RETURN VALUES 11740ad55d7Sdlg.Nm pci_mapreg_map , 11840ad55d7Sdlg.Nm pci_mapreg_info , 11940ad55d7Sdlgand 12040ad55d7Sdlg.Nm pci_mapreg_probe 12140ad55d7Sdlgreturn 0 on success, or an 12240ad55d7Sdlg.Xr errno 2 12340ad55d7Sdlgstyle value on failure. 12440ad55d7Sdlg.Pp 12540ad55d7Sdlg.Nm pci_mapreg_type 12640ad55d7Sdlgreturns either 12740ad55d7Sdlg.Dv PCI_MAPREG_TYPE_IO 12840ad55d7Sdlgor 12940ad55d7Sdlg.Dv PCI_MAPREG_TYPE_MEM . 13040ad55d7Sdlg.Sh SEE ALSO 13140ad55d7Sdlg.Xr pci 4 , 13240ad55d7Sdlg.Xr bus_space 9 , 13340ad55d7Sdlg.Xr pci_conf_read 9 134