1*dcfa02deSjsg.\" $OpenBSD: pci_intr_map.9,v 1.19 2024/11/13 10:56:18 jsg Exp $ 2783423bcSmickey.\" 3783423bcSmickey.\" Copyright (c) 2005 Michael Shalayeff 4783423bcSmickey.\" All rights reserved. 5783423bcSmickey.\" 6783423bcSmickey.\" Permission to use, copy, modify, and distribute this software for any 7783423bcSmickey.\" purpose with or without fee is hereby granted, provided that the above 8783423bcSmickey.\" copyright notice and this permission notice appear in all copies. 9783423bcSmickey.\" 10783423bcSmickey.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11783423bcSmickey.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12783423bcSmickey.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13783423bcSmickey.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14783423bcSmickey.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15783423bcSmickey.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16783423bcSmickey.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17783423bcSmickey.\" 18*dcfa02deSjsg.Dd $Mdocdate: November 13 2024 $ 1987bee306Sjmc.Dt PCI_INTR_MAP 9 20783423bcSmickey.Os 21783423bcSmickey.Sh NAME 22783423bcSmickey.Nm pci_intr_map , 23247f42c8Skettenis.Nm pci_intr_map_msi , 24c9dca022Sdlg.Nm pci_intr_map_msix , 2587bee306Sjmc.Nm pci_intr_line , 26783423bcSmickey.Nm pci_intr_string , 27783423bcSmickey.Nm pci_intr_establish , 28be1a0155Sdlg.\" .Nm pci_intr_establish_cpu , 29783423bcSmickey.Nm pci_intr_disestablish 30783423bcSmickey.Nd PCI interrupts 31783423bcSmickey.Sh SYNOPSIS 32dddd2645Sschwarze.In alpha/pci/pci_machdep.h 33dddd2645Sschwarze.In i386/pci/pci_machdep.h 34dddd2645Sschwarze.In machine/pci_machdep.h 35783423bcSmickey.Ft int 36783423bcSmickey.Fn pci_intr_map "struct pci_attach_args *paa" "pci_intr_handle_t *ih" 37783423bcSmickey.Ft int 38247f42c8Skettenis.Fn pci_intr_map_msi "struct pci_attach_args *paa" "pci_intr_handle_t *ih" 39247f42c8Skettenis.Ft int 40c9dca022Sdlg.Fo pci_intr_map_msix 41c9dca022Sdlg.Fa "struct pci_attach_args *paa" 42c9dca022Sdlg.Fa "int vector" 43c9dca022Sdlg.Fa "pci_intr_handle_t *ih" 44c9dca022Sdlg.Fc 45c9dca022Sdlg.Ft int 466f796c99Skettenis.Fn pci_intr_line "pci_intr_handle_t ih" 47783423bcSmickey.Ft const char * 48783423bcSmickey.Fn pci_intr_string "pci_chipset_tag_t pc" "pci_intr_handle_t ih" 49783423bcSmickey.Ft void * 5008a2eb03Sdlg.Fo pci_intr_establish 5108a2eb03Sdlg.Fa "pci_chipset_tag_t pc" 5208a2eb03Sdlg.Fa "pci_intr_handle_t ih" 5308a2eb03Sdlg.Fa "int level" 5408a2eb03Sdlg.Fa "int (*func)(void *)" 5508a2eb03Sdlg.Fa "void *arg" 5608a2eb03Sdlg.Fa "const char *name" 5708a2eb03Sdlg.Fc 58be1a0155Sdlg.\" .Ft void * 59be1a0155Sdlg.\" .Fo pci_intr_establish_cpu 60be1a0155Sdlg.\" .Fa "pci_chipset_tag_t pc" 61be1a0155Sdlg.\" .Fa "pci_intr_handle_t ih" 62be1a0155Sdlg.\" .Fa "int level" 63be1a0155Sdlg.\" .Fa "struct cpu_info *ci" 64be1a0155Sdlg.\" .Fa "int (*func)(void *)" 65be1a0155Sdlg.\" .Fa "void *arg" 66be1a0155Sdlg.\" .Fa "const char *name" 67be1a0155Sdlg.\" .Fc 68783423bcSmickey.Ft void 69783423bcSmickey.Fn pci_intr_disestablish "pci_chipset_tag_t pc" "void *v" 70783423bcSmickey.Sh DESCRIPTION 7187bee306SjmcThese functions are provided by the machine-dependent implementation 7287bee306Sjmcfor attaching handler functions to the interrupts of PCI devices. 73783423bcSmickey.Pp 7487bee306SjmcAn architect type is provided by the machine-dependent 75783423bcSmickeycode 7687bee306Sjmc.Va pci_intr_handle_t , 7787bee306Sjmcto be initialised by 78c9dca022Sdlg.Fn pci_intr_map , 79c9dca022Sdlg.Fn pci_intr_map_msi , 80247f42c8Skettenisor 81c9dca022Sdlg.Fn pci_intr_map_msix . 82783423bcSmickey.Pp 83783423bcSmickeyThe 8487bee306Sjmc.Fn pci_intr_map 8587bee306Sjmcfunction should be called first to establish a mapping between a PCI 86783423bcSmickeypin and the interrupt controller's interrupt vector. 8787bee306SjmcThis process may include resolving the mapping through 8887bee306Sjmcfirmware-provided information. 89c9dca022Sdlg.Pp 90247f42c8SkettenisFor devices that support Message Signaled Interrupts (MSI) the 91247f42c8Skettenis.Fn pci_intr_map_msi 92dfcecdcdSjmcfunction should be called instead. 93dfcecdcdSjmcThis function can fail if the 94247f42c8Skettenissystem does not support MSI. 95247f42c8SkettenisIn that case 96247f42c8Skettenis.Fn pci_intr_map 97247f42c8Skettenisshould be called to fall back on classic PCI interrupts. 98783423bcSmickey.Pp 99c9dca022SdlgFor devices that support Extended Message Signaled Interrupts (MSI-X) the 100c9dca022Sdlg.Fn pci_intr_map_msix 101c9dca022Sdlgfunction can be called instead. 102c9dca022SdlgThis function can fail if the system does not support MSI-X. 103c9dca022SdlgIn that case 104c9dca022Sdlg.Fn pci_intr_map_msi 105c9dca022Sdlgor 106c9dca022Sdlg.Fn pci_intr_map 107c9dca022Sdlgcan be called to fall back on Message Signalled Interrupts or classic 108c9dca022SdlgPCI interrupts respectively. 109c9dca022SdlgMSI-X can provide multiple interrupt vectors per device. 110c9dca022SdlgFor each vector, a separate call to 111c9dca022Sdlg.Fn pci_intr_map_msix 112c9dca022Sdlgis made with the 113c9dca022Sdlg.Fa vector 114c9dca022Sdlgargument specifying which interrupt vector to map. 115c9dca022Sdlg.Pp 11687bee306SjmcHaving initialised the 117e9ca8782Sdlg.Fa pci_intr_handle_t 11887bee306Sjmcin the previous step, an interrupt handler can be established using 119be1a0155Sdlg.Fn pci_intr_establish . 120be1a0155Sdlg.\" or 121be1a0155Sdlg.\" .Fn pci_intr_establish_cpu . 122be1a0155Sdlg.\" .Fn pci_intr_establish_cpu 123be1a0155Sdlg.\" establishes an interrupt on the CPU specified in the 124be1a0155Sdlg.\" .Fa ci 125be1a0155Sdlg.\" argument, while 126be1a0155Sdlg.\" .Fn pci_intr_establish 127be1a0155Sdlg.\" uses a system selected CPU. 128e9ca8782SdlgAn established interrupt handler is always called with the system 129e9ca8782Sdlginterrupt priority level set equal to, or higher than, 130e9ca8782Sdlg.Fa level . 131f1650feeSpedro.Pp 132be1a0155SdlgA printable string representation of an initialised interrupt mapping 133be1a0155Sdlgcan be generated with 134be1a0155Sdlg.Fn pci_intr_string . 135be1a0155Sdlg.Pp 13687bee306Sjmc.Fn pci_intr_line 13787bee306Sjmcprovides the interrupt line extracted from the MD interrupt handle. 13887bee306SjmcUpon device detachment, 13987bee306Sjmc.Fn pci_intr_disestablish 14087bee306Sjmcshould be used to disassociate the handler from the interrupt. 141b9d50d50Smickey.Pp 142b9d50d50SmickeySee 143b9d50d50Smickey.Xr spl 9 1447a1e9f22Sjmcfor an explanation of the 145b9d50d50Smickey.Va ipl 146b9d50d50Smickey.Dq interrupt priority levels . 14787bee306Sjmc.Sh EXAMPLES 148783423bcSmickeyA typical code sequence for establishing a handler 149783423bcSmickeyfor a device interrupt in the driver might be: 15087bee306Sjmc.Bd -literal -offset 3n 151783423bcSmickeyint 152783423bcSmickeyxxxattach(struct device *parent, struct device *self, void *aux) 153783423bcSmickey{ 154783423bcSmickey struct xxx_softc *sc = (struct xxx_softc *)self; 155783423bcSmickey struct pci_attach_args *pa = aux; 156783423bcSmickey pci_intr_handle_t ih; 157783423bcSmickey const char *intrstr; 158783423bcSmickey bus_size_t size; 159783423bcSmickey 160783423bcSmickey \&... 161783423bcSmickey 162247f42c8Skettenis if (pci_intr_map_msi(pa, &ih) && pci_intr_map(pa, &ih)) { 163e1665715Sjmc printf(": can't map interrupt\en"); 164783423bcSmickey bus_space_unmap(sc->iot, sc->ioh, size); 165783423bcSmickey return; 166783423bcSmickey } 167783423bcSmickey intrstr = pci_intr_string(pa->pa_pc, ih); 168783423bcSmickey sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, 169783423bcSmickey xxx_intr, sc, sc->sc_dev.dv_xname); 170783423bcSmickey if (!sc->sc_ih) { 171783423bcSmickey printf(": can't establish interrupt"); 172783423bcSmickey if (intrstr) 173783423bcSmickey printf(" at %s", intrstr); 174e1665715Sjmc printf("\en"); 175783423bcSmickey bus_space_unmap(sc->iot, sc->ioh, size); 176783423bcSmickey return; 177783423bcSmickey } 178783423bcSmickey 179e1665715Sjmc printf(": %s\en", intrstr); 180783423bcSmickey 181783423bcSmickey \&... 182783423bcSmickey} 183783423bcSmickey.Ed 184783423bcSmickey.Sh SEE ALSO 185783423bcSmickey.Xr cardbus 4 , 186783423bcSmickey.Xr pci 4 , 187783423bcSmickey.Xr pcibios 4 , 188b9d50d50Smickey.Xr pci_conf_read 9 , 189b9d50d50Smickey.Xr spl 9 190783423bcSmickey.Sh HISTORY 191783423bcSmickeyThese functions first appeared in 192783423bcSmickey.Ox 1.2 . 193783423bcSmickey.\" .Sh AUTHORS 194