1*5a419151Skettenis.\" $OpenBSD: rkclock.4,v 1.2 2018/03/31 09:44:35 kettenis Exp $ 22fcc7a32Sjsg.\" 32fcc7a32Sjsg.\" Copyright (c) 2018 Jonathan Gray <jsg@openbsd.org> 42fcc7a32Sjsg.\" 52fcc7a32Sjsg.\" Permission to use, copy, modify, and distribute this software for any 62fcc7a32Sjsg.\" purpose with or without fee is hereby granted, provided that the above 72fcc7a32Sjsg.\" copyright notice and this permission notice appear in all copies. 82fcc7a32Sjsg.\" 92fcc7a32Sjsg.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 102fcc7a32Sjsg.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 112fcc7a32Sjsg.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 122fcc7a32Sjsg.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 132fcc7a32Sjsg.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 142fcc7a32Sjsg.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 152fcc7a32Sjsg.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 162fcc7a32Sjsg.\" 172fcc7a32Sjsg.Dd $Mdocdate: March 31 2018 $ 182fcc7a32Sjsg.Dt RKCLOCK 4 192fcc7a32Sjsg.Os 202fcc7a32Sjsg.Sh NAME 212fcc7a32Sjsg.Nm rkclock 222fcc7a32Sjsg.Nd Rockchip Clock and Reset Unit 232fcc7a32Sjsg.Sh SYNOPSIS 242fcc7a32Sjsg.Cd "rkclock* at fdt?" 252fcc7a32Sjsg.Sh DESCRIPTION 262fcc7a32SjsgThe 272fcc7a32Sjsg.Nm 282fcc7a32Sjsgdriver controls clock gating for integrated components of Rockchip SoCs. 292fcc7a32Sjsg.Sh SEE ALSO 302fcc7a32Sjsg.Xr intro 4 312fcc7a32Sjsg.Sh HISTORY 322fcc7a32SjsgThe 332fcc7a32Sjsg.Nm 342fcc7a32Sjsgdevice driver first appeared in 352fcc7a32Sjsg.Ox 6.2 . 36*5a419151Skettenis.Sh AUTHORS 37*5a419151Skettenis.An -nosplit 38*5a419151SkettenisThe 39*5a419151Skettenis.Nm 40*5a419151Skettenisdriver was written by 41*5a419151Skettenis.An Mark Kettenis Aq Mt kettenis@openbsd.org . 42