1*72d4bfd9Sjsing /* $OpenBSD: crypto_cpu_caps.c,v 1.3 2024/11/12 13:14:57 jsing Exp $ */ 2ebcdcd38Sjsing /* 3ebcdcd38Sjsing * Copyright (c) 2024 Joel Sing <jsing@openbsd.org> 4ebcdcd38Sjsing * 5ebcdcd38Sjsing * Permission to use, copy, modify, and distribute this software for any 6ebcdcd38Sjsing * purpose with or without fee is hereby granted, provided that the above 7ebcdcd38Sjsing * copyright notice and this permission notice appear in all copies. 8ebcdcd38Sjsing * 9ebcdcd38Sjsing * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10ebcdcd38Sjsing * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11ebcdcd38Sjsing * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12ebcdcd38Sjsing * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13ebcdcd38Sjsing * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14ebcdcd38Sjsing * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15ebcdcd38Sjsing * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16ebcdcd38Sjsing */ 17ebcdcd38Sjsing 18ebcdcd38Sjsing #include <stdio.h> 19ebcdcd38Sjsing 20ebcdcd38Sjsing #include <openssl/crypto.h> 21ebcdcd38Sjsing 22ebcdcd38Sjsing #include "x86_arch.h" 23ebcdcd38Sjsing 24ebcdcd38Sjsing /* Legacy architecture specific capabilities, used by perlasm. */ 2529a830a1Sjsing uint64_t OPENSSL_ia32cap_P; 26ebcdcd38Sjsing 27ebcdcd38Sjsing /* Machine independent CPU capabilities. */ 28ebcdcd38Sjsing extern uint64_t crypto_cpu_caps; 29ebcdcd38Sjsing 30ebcdcd38Sjsing static inline void 31ebcdcd38Sjsing cpuid(uint32_t eax, uint32_t *out_eax, uint32_t *out_ebx, uint32_t *out_ecx, 32ebcdcd38Sjsing uint32_t *out_edx) 33ebcdcd38Sjsing { 34ebcdcd38Sjsing uint32_t ebx = 0, ecx = 0, edx = 0; 35ebcdcd38Sjsing 36ebcdcd38Sjsing #ifndef OPENSSL_NO_ASM 37ebcdcd38Sjsing __asm__ ("cpuid": "+a"(eax), "+b"(ebx), "+c"(ecx), "+d"(edx)); 38ebcdcd38Sjsing #else 39ebcdcd38Sjsing eax = 0; 40ebcdcd38Sjsing #endif 41ebcdcd38Sjsing 42ebcdcd38Sjsing if (out_eax != NULL) 43ebcdcd38Sjsing *out_eax = eax; 44ebcdcd38Sjsing if (out_ebx != NULL) 45ebcdcd38Sjsing *out_ebx = ebx; 46*72d4bfd9Sjsing if (out_ecx != NULL) 47ebcdcd38Sjsing *out_ecx = ecx; 48ebcdcd38Sjsing if (out_edx != NULL) 49ebcdcd38Sjsing *out_edx = edx; 50ebcdcd38Sjsing } 51ebcdcd38Sjsing 52ebcdcd38Sjsing static inline void 53ebcdcd38Sjsing xgetbv(uint32_t ecx, uint32_t *out_eax, uint32_t *out_edx) 54ebcdcd38Sjsing { 55ebcdcd38Sjsing uint32_t eax = 0, edx = 0; 56ebcdcd38Sjsing 57ebcdcd38Sjsing #ifndef OPENSSL_NO_ASM 58ebcdcd38Sjsing __asm__ ("xgetbv": "+a"(eax), "+c"(ecx), "+d"(edx)); 59ebcdcd38Sjsing #endif 60ebcdcd38Sjsing 61ebcdcd38Sjsing if (out_eax != NULL) 62ebcdcd38Sjsing *out_eax = eax; 63ebcdcd38Sjsing if (out_edx != NULL) 64ebcdcd38Sjsing *out_edx = edx; 65ebcdcd38Sjsing } 66ebcdcd38Sjsing 67ebcdcd38Sjsing void 68ebcdcd38Sjsing crypto_cpu_caps_init(void) 69ebcdcd38Sjsing { 70ebcdcd38Sjsing uint32_t eax, ebx, ecx, edx; 71ebcdcd38Sjsing uint64_t caps = 0; 72ebcdcd38Sjsing 73ebcdcd38Sjsing cpuid(0, &eax, &ebx, &ecx, &edx); 74ebcdcd38Sjsing 75ebcdcd38Sjsing /* "GenuineIntel" in little endian. */ 76ebcdcd38Sjsing if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) 77ebcdcd38Sjsing caps |= CPUCAP_MASK_INTEL; 78ebcdcd38Sjsing 79ebcdcd38Sjsing if (eax < 1) 80ebcdcd38Sjsing return; 81ebcdcd38Sjsing 82ebcdcd38Sjsing cpuid(1, &eax, &ebx, &ecx, &edx); 83ebcdcd38Sjsing 84ebcdcd38Sjsing if ((edx & IA32CAP_MASK0_FXSR) != 0) 85ebcdcd38Sjsing caps |= CPUCAP_MASK_FXSR; 86ebcdcd38Sjsing if ((edx & IA32CAP_MASK0_HT) != 0) 87ebcdcd38Sjsing caps |= CPUCAP_MASK_HT; 88ebcdcd38Sjsing if ((edx & IA32CAP_MASK0_MMX) != 0) 89ebcdcd38Sjsing caps |= CPUCAP_MASK_MMX; 90ebcdcd38Sjsing if ((edx & IA32CAP_MASK0_SSE) != 0) 91ebcdcd38Sjsing caps |= CPUCAP_MASK_SSE; 92ebcdcd38Sjsing if ((edx & IA32CAP_MASK0_SSE2) != 0) 93ebcdcd38Sjsing caps |= CPUCAP_MASK_SSE2; 94ebcdcd38Sjsing 95ebcdcd38Sjsing if ((ecx & IA32CAP_MASK1_AESNI) != 0) 96ebcdcd38Sjsing caps |= CPUCAP_MASK_AESNI; 97ebcdcd38Sjsing if ((ecx & IA32CAP_MASK1_PCLMUL) != 0) 98ebcdcd38Sjsing caps |= CPUCAP_MASK_PCLMUL; 99ebcdcd38Sjsing if ((ecx & IA32CAP_MASK1_SSSE3) != 0) 100ebcdcd38Sjsing caps |= CPUCAP_MASK_SSSE3; 101ebcdcd38Sjsing 102ebcdcd38Sjsing /* AVX requires OSXSAVE and XMM/YMM state to be enabled. */ 103ebcdcd38Sjsing if ((ecx & IA32CAP_MASK1_OSXSAVE) != 0) { 104ebcdcd38Sjsing xgetbv(0, &eax, NULL); 105ebcdcd38Sjsing if (((eax >> 1) & 3) == 3 && (ecx & IA32CAP_MASK1_AVX) != 0) 106ebcdcd38Sjsing caps |= CPUCAP_MASK_AVX; 107ebcdcd38Sjsing } 108ebcdcd38Sjsing 109ebcdcd38Sjsing /* Set machine independent CPU capabilities. */ 110ebcdcd38Sjsing if ((caps & CPUCAP_MASK_AESNI) != 0) 111ebcdcd38Sjsing crypto_cpu_caps |= CRYPTO_CPU_CAPS_ACCELERATED_AES; 112ebcdcd38Sjsing 113ebcdcd38Sjsing OPENSSL_ia32cap_P = caps; 114ebcdcd38Sjsing } 11529a830a1Sjsing 11629a830a1Sjsing uint64_t 11729a830a1Sjsing crypto_cpu_caps_ia32(void) 11829a830a1Sjsing { 11929a830a1Sjsing return OPENSSL_ia32cap_P; 12029a830a1Sjsing } 121