1*73d4fc9bSjmc.\" $OpenBSD: arm_sync_icache.2,v 1.4 2013/08/14 06:32:26 jmc Exp $ 20c2bf8fcSdrahn.\" $NetBSD: arm_sync_icache.2,v 1.5 2004/02/13 09:56:47 wiz Exp $ 30c2bf8fcSdrahn.\" 40c2bf8fcSdrahn.\" Copyright (c) 1996 Mark Brinicombe 50c2bf8fcSdrahn.\" All rights reserved. 60c2bf8fcSdrahn.\" 70c2bf8fcSdrahn.\" Redistribution and use in source and binary forms, with or without 80c2bf8fcSdrahn.\" modification, are permitted provided that the following conditions 90c2bf8fcSdrahn.\" are met: 100c2bf8fcSdrahn.\" 1. Redistributions of source code must retain the above copyright 110c2bf8fcSdrahn.\" notice, this list of conditions and the following disclaimer. 120c2bf8fcSdrahn.\" 2. Redistributions in binary form must reproduce the above copyright 130c2bf8fcSdrahn.\" notice, this list of conditions and the following disclaimer in the 140c2bf8fcSdrahn.\" documentation and/or other materials provided with the distribution. 150c2bf8fcSdrahn.\" 3. All advertising materials mentioning features or use of this software 160c2bf8fcSdrahn.\" must display the following acknowledgement: 170c2bf8fcSdrahn.\" This product includes software developed by Mark Brinicombe 180c2bf8fcSdrahn.\" 4. Neither the name of the University nor the names of its contributors 190c2bf8fcSdrahn.\" may be used to endorse or promote products derived from this software 200c2bf8fcSdrahn.\" without specific prior written permission. 210c2bf8fcSdrahn.\" 220c2bf8fcSdrahn.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 230c2bf8fcSdrahn.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 240c2bf8fcSdrahn.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 250c2bf8fcSdrahn.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 260c2bf8fcSdrahn.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 270c2bf8fcSdrahn.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 280c2bf8fcSdrahn.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 290c2bf8fcSdrahn.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 300c2bf8fcSdrahn.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 310c2bf8fcSdrahn.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 320c2bf8fcSdrahn.\" SUCH DAMAGE. 330c2bf8fcSdrahn.\" 34*73d4fc9bSjmc.Dd $Mdocdate: August 14 2013 $ 350c2bf8fcSdrahn.Dt ARM_SYNC_ICACHE 2 arm 360c2bf8fcSdrahn.Os 370c2bf8fcSdrahn.Sh NAME 380c2bf8fcSdrahn.Nm arm_sync_icache 39*73d4fc9bSjmc.Nd clean the CPU data cache and flush the CPU instruction cache 400c2bf8fcSdrahn.Sh SYNOPSIS 410c2bf8fcSdrahn.In machine/sysarch.h 420c2bf8fcSdrahn.Ft int 430c2bf8fcSdrahn.Fn arm_sync_icache "u_int addr" "int len" 440c2bf8fcSdrahn.Sh DESCRIPTION 450c2bf8fcSdrahn.Fn arm_sync_icache 460c2bf8fcSdrahnwill make sure that all the entries in the processor instruction cache 470c2bf8fcSdrahnare synchronized with main memory and that any data in a write back cache 480c2bf8fcSdrahnhas been cleaned. 490c2bf8fcSdrahnSome ARM processors (e.g. SA110) have separate instruction and data 500c2bf8fcSdrahncaches, thus any dynamically generated or modified code needs to be 510c2bf8fcSdrahnwritten back from any data caches to main memory and the instruction 520c2bf8fcSdrahncache needs to be synchronized with main memory. 530c2bf8fcSdrahn.Pp 540c2bf8fcSdrahnOn such processors, 550c2bf8fcSdrahn.Fn arm_sync_icache 560c2bf8fcSdrahnwill clean the data cache and invalidate the processor instruction cache 570c2bf8fcSdrahnto force reloading from main memory. 580c2bf8fcSdrahnOn processors that have a shared instruction and data cache and have a 590c2bf8fcSdrahnwrite through cache (e.g. ARM6), no action needs to be taken. 600c2bf8fcSdrahn.Pp 610c2bf8fcSdrahnThe routine takes a start address 620c2bf8fcSdrahn.Fa addr 630c2bf8fcSdrahnand a length 640c2bf8fcSdrahn.Fa len 650c2bf8fcSdrahnto describe the area of memory that needs to be cleaned and synchronized. 660c2bf8fcSdrahn.Sh ERRORS 670c2bf8fcSdrahn.Fn arm_sync_icache 680c2bf8fcSdrahnwill never fail so will always return 0. 690c2bf8fcSdrahn.Sh REFERENCES 700c2bf8fcSdrahnStrongARM Data Sheet 71