1*1ad61ae0Srobert# $OpenBSD: Makefile,v 1.7 2023/11/11 18:35:36 robert Exp $ 271c20c53Sjsg 371c20c53SjsgLIB= LLVMAMDGPUCodeGen 471c20c53SjsgNOPROFILE= 571c20c53Sjsg 671c20c53SjsgCPPFLAGS+= -I${.OBJDIR}/../include/llvm/AMDGPU \ 771c20c53Sjsg -I${LLVM_SRCS}/lib/Target/AMDGPU 871c20c53Sjsg 92584ca0bSjsgSRCS+= AMDGPUAliasAnalysis.cpp \ 1071c20c53Sjsg AMDGPUAlwaysInlinePass.cpp \ 1171c20c53Sjsg AMDGPUAnnotateKernelFeatures.cpp \ 1271c20c53Sjsg AMDGPUAnnotateUniformValues.cpp \ 1371c20c53Sjsg AMDGPUArgumentUsageInfo.cpp \ 1471c20c53Sjsg AMDGPUAsmPrinter.cpp \ 157350f337Spatrick AMDGPUAtomicOptimizer.cpp \ 16*1ad61ae0Srobert AMDGPUAttributor.cpp \ 1771c20c53Sjsg AMDGPUCallLowering.cpp \ 1871c20c53Sjsg AMDGPUCodeGenPrepare.cpp \ 19*1ad61ae0Srobert AMDGPUCombinerHelper.cpp \ 20*1ad61ae0Srobert AMDGPUCtorDtorLowering.cpp \ 21c04ab3e3Spatrick AMDGPUExportClustering.cpp \ 2271c20c53Sjsg AMDGPUFrameLowering.cpp \ 23*1ad61ae0Srobert AMDGPUGlobalISelUtils.cpp \ 2471c20c53Sjsg AMDGPUHSAMetadataStreamer.cpp \ 25*1ad61ae0Srobert AMDGPUInsertDelayAlu.cpp \ 265a38ef86Spatrick AMDGPUInstCombineIntrinsic.cpp \ 2771c20c53Sjsg AMDGPUInstrInfo.cpp \ 2871c20c53Sjsg AMDGPUInstructionSelector.cpp \ 2971c20c53Sjsg AMDGPUISelDAGToDAG.cpp \ 3071c20c53Sjsg AMDGPUISelLowering.cpp \ 315a38ef86Spatrick AMDGPULateCodeGenPrepare.cpp \ 3271c20c53Sjsg AMDGPULegalizerInfo.cpp \ 3371c20c53Sjsg AMDGPULibCalls.cpp \ 3471c20c53Sjsg AMDGPULibFunc.cpp \ 3571c20c53Sjsg AMDGPULowerIntrinsics.cpp \ 3671c20c53Sjsg AMDGPULowerKernelArguments.cpp \ 3771c20c53Sjsg AMDGPULowerKernelAttributes.cpp \ 385a38ef86Spatrick AMDGPULowerModuleLDSPass.cpp \ 3971c20c53Sjsg AMDGPUMachineCFGStructurizer.cpp \ 4071c20c53Sjsg AMDGPUMachineFunction.cpp \ 4171c20c53Sjsg AMDGPUMachineModuleInfo.cpp \ 4271c20c53Sjsg AMDGPUMacroFusion.cpp \ 4371c20c53Sjsg AMDGPUMCInstLower.cpp \ 44*1ad61ae0Srobert AMDGPUIGroupLP.cpp \ 455a38ef86Spatrick AMDGPUMIRFormatter.cpp \ 4671c20c53Sjsg AMDGPUOpenCLEnqueuedBlockLowering.cpp \ 47*1ad61ae0Srobert AMDGPUPerfHintAnalysis.cpp \ 48c04ab3e3Spatrick AMDGPUPostLegalizerCombiner.cpp \ 49c04ab3e3Spatrick AMDGPUPreLegalizerCombiner.cpp \ 50*1ad61ae0Srobert AMDGPUPrintfRuntimeBinding.cpp \ 5171c20c53Sjsg AMDGPUPromoteAlloca.cpp \ 52aa1fa3d4Spatrick AMDGPUPropagateAttributes.cpp \ 53*1ad61ae0Srobert AMDGPUPromoteKernelArguments.cpp \ 54c04ab3e3Spatrick AMDGPURegBankCombiner.cpp \ 5571c20c53Sjsg AMDGPURegisterBankInfo.cpp \ 56*1ad61ae0Srobert AMDGPUReleaseVGPRs.cpp \ 575a38ef86Spatrick AMDGPUReplaceLDSUseWithPointer.cpp \ 58*1ad61ae0Srobert AMDGPUResourceUsageAnalysis.cpp \ 5971c20c53Sjsg AMDGPURewriteOutArguments.cpp \ 60*1ad61ae0Srobert AMDGPURewriteUndefForPHI.cpp \ 61*1ad61ae0Srobert AMDGPUSetWavePriority.cpp \ 6271c20c53Sjsg AMDGPUSubtarget.cpp \ 6371c20c53Sjsg AMDGPUTargetMachine.cpp \ 6471c20c53Sjsg AMDGPUTargetObjectFile.cpp \ 6571c20c53Sjsg AMDGPUTargetTransformInfo.cpp \ 6671c20c53Sjsg AMDGPUUnifyDivergentExitNodes.cpp \ 6771c20c53Sjsg AMDGPUUnifyMetadata.cpp \ 68*1ad61ae0Srobert R600MachineCFGStructurizer.cpp \ 69*1ad61ae0Srobert GCNCreateVOPD.cpp \ 70*1ad61ae0Srobert GCNDPPCombine.cpp \ 7171c20c53Sjsg GCNHazardRecognizer.cpp \ 72*1ad61ae0Srobert GCNILPSched.cpp \ 7371c20c53Sjsg GCNIterativeScheduler.cpp \ 7471c20c53Sjsg GCNMinRegStrategy.cpp \ 75*1ad61ae0Srobert GCNNSAReassign.cpp \ 76*1ad61ae0Srobert GCNPreRAOptimizations.cpp \ 7771c20c53Sjsg GCNRegPressure.cpp \ 7871c20c53Sjsg GCNSchedStrategy.cpp \ 79*1ad61ae0Srobert GCNVOPDUtils.cpp \ 8071c20c53Sjsg R600AsmPrinter.cpp \ 8171c20c53Sjsg R600ClauseMergePass.cpp \ 8271c20c53Sjsg R600ControlFlowFinalizer.cpp \ 8371c20c53Sjsg R600EmitClauseMarkers.cpp \ 8471c20c53Sjsg R600ExpandSpecialInstrs.cpp \ 8571c20c53Sjsg R600FrameLowering.cpp \ 8671c20c53Sjsg R600InstrInfo.cpp \ 87*1ad61ae0Srobert R600ISelDAGToDAG.cpp \ 8871c20c53Sjsg R600ISelLowering.cpp \ 8971c20c53Sjsg R600MachineFunctionInfo.cpp \ 9071c20c53Sjsg R600MachineScheduler.cpp \ 91*1ad61ae0Srobert R600MCInstLower.cpp \ 9271c20c53Sjsg R600OpenCLImageTypeLoweringPass.cpp \ 9371c20c53Sjsg R600OptimizeVectorRegisters.cpp \ 9471c20c53Sjsg R600Packetizer.cpp \ 9571c20c53Sjsg R600RegisterInfo.cpp \ 96*1ad61ae0Srobert R600Subtarget.cpp \ 97*1ad61ae0Srobert R600TargetMachine.cpp \ 98*1ad61ae0Srobert R600TargetTransformInfo.cpp \ 9971c20c53Sjsg SIAnnotateControlFlow.cpp \ 10071c20c53Sjsg SIFixSGPRCopies.cpp \ 10171c20c53Sjsg SIFixVGPRCopies.cpp \ 10271c20c53Sjsg SIFoldOperands.cpp \ 10371c20c53Sjsg SIFormMemoryClauses.cpp \ 10471c20c53Sjsg SIFrameLowering.cpp \ 105c04ab3e3Spatrick SIInsertHardClauses.cpp \ 10671c20c53Sjsg SIInsertWaitcnts.cpp \ 10771c20c53Sjsg SIInstrInfo.cpp \ 10871c20c53Sjsg SIISelLowering.cpp \ 109*1ad61ae0Srobert SILateBranchLowering.cpp \ 11071c20c53Sjsg SILoadStoreOptimizer.cpp \ 11171c20c53Sjsg SILowerControlFlow.cpp \ 11271c20c53Sjsg SILowerI1Copies.cpp \ 113aa1fa3d4Spatrick SILowerSGPRSpills.cpp \ 11471c20c53Sjsg SIMachineFunctionInfo.cpp \ 11571c20c53Sjsg SIMachineScheduler.cpp \ 11671c20c53Sjsg SIMemoryLegalizer.cpp \ 117*1ad61ae0Srobert SIModeRegister.cpp \ 11871c20c53Sjsg SIOptimizeExecMasking.cpp \ 11971c20c53Sjsg SIOptimizeExecMaskingPreRA.cpp \ 1205a38ef86Spatrick SIOptimizeVGPRLiveRange.cpp \ 12171c20c53Sjsg SIPeepholeSDWA.cpp \ 122c04ab3e3Spatrick SIPostRABundler.cpp \ 123*1ad61ae0Srobert SIPreAllocateWWMRegs.cpp \ 124c04ab3e3Spatrick SIPreEmitPeephole.cpp \ 1255a38ef86Spatrick SIProgramInfo.cpp \ 12671c20c53Sjsg SIRegisterInfo.cpp \ 12771c20c53Sjsg SIShrinkInstructions.cpp \ 128*1ad61ae0Srobert SIWholeQuadMode.cpp 12971c20c53Sjsg 130aa1fa3d4Spatrick.PATH: ${.CURDIR}/../../../llvm/llvm/lib/Target/AMDGPU 131