1d2201f2fSdrahn /* Xtensa configuration settings. 2*cf2f2c56Smiod Copyright (C) 2001,2002,2003 Free Software Foundation, Inc. 3d2201f2fSdrahn Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4d2201f2fSdrahn 5d2201f2fSdrahn This program is free software; you can redistribute it and/or modify 6d2201f2fSdrahn it under the terms of the GNU General Public License as published by 7d2201f2fSdrahn the Free Software Foundation; either version 2, or (at your option) 8d2201f2fSdrahn any later version. 9d2201f2fSdrahn 10d2201f2fSdrahn This program is distributed in the hope that it will be useful, but 11d2201f2fSdrahn WITHOUT ANY WARRANTY; without even the implied warranty of 12d2201f2fSdrahn MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13d2201f2fSdrahn General Public License for more details. 14d2201f2fSdrahn 15d2201f2fSdrahn You should have received a copy of the GNU General Public License 16d2201f2fSdrahn along with this program; if not, write to the Free Software 17d2201f2fSdrahn Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 18d2201f2fSdrahn 19d2201f2fSdrahn #ifndef XTENSA_CONFIG_H 20d2201f2fSdrahn #define XTENSA_CONFIG_H 21d2201f2fSdrahn 22d2201f2fSdrahn /* The macros defined here match those with the same names in the Xtensa 23d2201f2fSdrahn compile-time HAL (Hardware Abstraction Layer). Please refer to the 24d2201f2fSdrahn Xtensa System Software Reference Manual for documentation of these 25d2201f2fSdrahn macros. */ 26d2201f2fSdrahn 27*cf2f2c56Smiod #undef XCHAL_HAVE_BE 28d2201f2fSdrahn #define XCHAL_HAVE_BE 1 29*cf2f2c56Smiod 30*cf2f2c56Smiod #undef XCHAL_HAVE_DENSITY 31d2201f2fSdrahn #define XCHAL_HAVE_DENSITY 1 32*cf2f2c56Smiod 33*cf2f2c56Smiod #undef XCHAL_HAVE_CONST16 34*cf2f2c56Smiod #define XCHAL_HAVE_CONST16 0 35*cf2f2c56Smiod 36*cf2f2c56Smiod #undef XCHAL_HAVE_ABS 37*cf2f2c56Smiod #define XCHAL_HAVE_ABS 1 38*cf2f2c56Smiod 39*cf2f2c56Smiod #undef XCHAL_HAVE_ADDX 40*cf2f2c56Smiod #define XCHAL_HAVE_ADDX 1 41*cf2f2c56Smiod 42*cf2f2c56Smiod #undef XCHAL_HAVE_L32R 43*cf2f2c56Smiod #define XCHAL_HAVE_L32R 1 44*cf2f2c56Smiod 45*cf2f2c56Smiod #undef XCHAL_HAVE_MAC16 46d2201f2fSdrahn #define XCHAL_HAVE_MAC16 0 47*cf2f2c56Smiod 48*cf2f2c56Smiod #undef XCHAL_HAVE_MUL16 49d2201f2fSdrahn #define XCHAL_HAVE_MUL16 0 50*cf2f2c56Smiod 51*cf2f2c56Smiod #undef XCHAL_HAVE_MUL32 52d2201f2fSdrahn #define XCHAL_HAVE_MUL32 0 53*cf2f2c56Smiod 54*cf2f2c56Smiod #undef XCHAL_HAVE_DIV32 55d2201f2fSdrahn #define XCHAL_HAVE_DIV32 0 56*cf2f2c56Smiod 57*cf2f2c56Smiod #undef XCHAL_HAVE_NSA 58d2201f2fSdrahn #define XCHAL_HAVE_NSA 1 59*cf2f2c56Smiod 60*cf2f2c56Smiod #undef XCHAL_HAVE_MINMAX 61d2201f2fSdrahn #define XCHAL_HAVE_MINMAX 0 62*cf2f2c56Smiod 63*cf2f2c56Smiod #undef XCHAL_HAVE_SEXT 64d2201f2fSdrahn #define XCHAL_HAVE_SEXT 0 65*cf2f2c56Smiod 66*cf2f2c56Smiod #undef XCHAL_HAVE_LOOPS 67d2201f2fSdrahn #define XCHAL_HAVE_LOOPS 1 68*cf2f2c56Smiod 69*cf2f2c56Smiod #undef XCHAL_HAVE_BOOLEANS 70d2201f2fSdrahn #define XCHAL_HAVE_BOOLEANS 0 71*cf2f2c56Smiod 72*cf2f2c56Smiod #undef XCHAL_HAVE_FP 73d2201f2fSdrahn #define XCHAL_HAVE_FP 0 74*cf2f2c56Smiod 75*cf2f2c56Smiod #undef XCHAL_HAVE_FP_DIV 76d2201f2fSdrahn #define XCHAL_HAVE_FP_DIV 0 77*cf2f2c56Smiod 78*cf2f2c56Smiod #undef XCHAL_HAVE_FP_RECIP 79d2201f2fSdrahn #define XCHAL_HAVE_FP_RECIP 0 80*cf2f2c56Smiod 81*cf2f2c56Smiod #undef XCHAL_HAVE_FP_SQRT 82d2201f2fSdrahn #define XCHAL_HAVE_FP_SQRT 0 83*cf2f2c56Smiod 84*cf2f2c56Smiod #undef XCHAL_HAVE_FP_RSQRT 85d2201f2fSdrahn #define XCHAL_HAVE_FP_RSQRT 0 86*cf2f2c56Smiod 87*cf2f2c56Smiod #undef XCHAL_HAVE_WINDOWED 88d2201f2fSdrahn #define XCHAL_HAVE_WINDOWED 1 89d2201f2fSdrahn 90*cf2f2c56Smiod 91*cf2f2c56Smiod #undef XCHAL_ICACHE_SIZE 92d2201f2fSdrahn #define XCHAL_ICACHE_SIZE 8192 93*cf2f2c56Smiod 94*cf2f2c56Smiod #undef XCHAL_DCACHE_SIZE 95d2201f2fSdrahn #define XCHAL_DCACHE_SIZE 8192 96*cf2f2c56Smiod 97*cf2f2c56Smiod #undef XCHAL_ICACHE_LINESIZE 98d2201f2fSdrahn #define XCHAL_ICACHE_LINESIZE 16 99*cf2f2c56Smiod 100*cf2f2c56Smiod #undef XCHAL_DCACHE_LINESIZE 101d2201f2fSdrahn #define XCHAL_DCACHE_LINESIZE 16 102*cf2f2c56Smiod 103*cf2f2c56Smiod #undef XCHAL_ICACHE_LINEWIDTH 104d2201f2fSdrahn #define XCHAL_ICACHE_LINEWIDTH 4 105*cf2f2c56Smiod 106*cf2f2c56Smiod #undef XCHAL_DCACHE_LINEWIDTH 107d2201f2fSdrahn #define XCHAL_DCACHE_LINEWIDTH 4 108*cf2f2c56Smiod 109*cf2f2c56Smiod #undef XCHAL_DCACHE_IS_WRITEBACK 110d2201f2fSdrahn #define XCHAL_DCACHE_IS_WRITEBACK 0 111d2201f2fSdrahn 112*cf2f2c56Smiod 113*cf2f2c56Smiod #undef XCHAL_HAVE_MMU 114d2201f2fSdrahn #define XCHAL_HAVE_MMU 1 115*cf2f2c56Smiod 116*cf2f2c56Smiod #undef XCHAL_MMU_MIN_PTE_PAGE_SIZE 117d2201f2fSdrahn #define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 118d2201f2fSdrahn 119*cf2f2c56Smiod 120*cf2f2c56Smiod #undef XCHAL_HAVE_DEBUG 121d2201f2fSdrahn #define XCHAL_HAVE_DEBUG 1 122*cf2f2c56Smiod 123*cf2f2c56Smiod #undef XCHAL_NUM_IBREAK 124d2201f2fSdrahn #define XCHAL_NUM_IBREAK 2 125*cf2f2c56Smiod 126*cf2f2c56Smiod #undef XCHAL_NUM_DBREAK 127d2201f2fSdrahn #define XCHAL_NUM_DBREAK 2 128*cf2f2c56Smiod 129*cf2f2c56Smiod #undef XCHAL_DEBUGLEVEL 130d2201f2fSdrahn #define XCHAL_DEBUGLEVEL 4 131d2201f2fSdrahn 132*cf2f2c56Smiod 133*cf2f2c56Smiod #undef XCHAL_EXTRA_SA_SIZE 134d2201f2fSdrahn #define XCHAL_EXTRA_SA_SIZE 0 135*cf2f2c56Smiod 136*cf2f2c56Smiod #undef XCHAL_EXTRA_SA_ALIGN 137d2201f2fSdrahn #define XCHAL_EXTRA_SA_ALIGN 1 138d2201f2fSdrahn 139d2201f2fSdrahn #endif /* !XTENSA_CONFIG_H */ 140