109467b48Spatrick //===--- SIProgramInfo.h ----------------------------------------*- C++ -*-===// 209467b48Spatrick // 309467b48Spatrick // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 409467b48Spatrick // See https://llvm.org/LICENSE.txt for license information. 509467b48Spatrick // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 609467b48Spatrick // 709467b48Spatrick //===----------------------------------------------------------------------===// 809467b48Spatrick // 909467b48Spatrick /// \file 1073471bf0Spatrick /// Defines struct to track resource usage and hardware flags for kernels and 1173471bf0Spatrick /// entry functions. 1209467b48Spatrick /// 1309467b48Spatrick // 1409467b48Spatrick //===----------------------------------------------------------------------===// 1509467b48Spatrick 1609467b48Spatrick #ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 1709467b48Spatrick #define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 1809467b48Spatrick 1973471bf0Spatrick #include "llvm/IR/CallingConv.h" 2073471bf0Spatrick #include <cstdint> 2173471bf0Spatrick 2209467b48Spatrick namespace llvm { 2309467b48Spatrick 2409467b48Spatrick /// Track resource usage for kernels / entry functions. 2509467b48Spatrick struct SIProgramInfo { 2609467b48Spatrick // Fields set in PGM_RSRC1 pm4 packet. 2709467b48Spatrick uint32_t VGPRBlocks = 0; 2809467b48Spatrick uint32_t SGPRBlocks = 0; 2909467b48Spatrick uint32_t Priority = 0; 3009467b48Spatrick uint32_t FloatMode = 0; 3109467b48Spatrick uint32_t Priv = 0; 3209467b48Spatrick uint32_t DX10Clamp = 0; 3309467b48Spatrick uint32_t DebugMode = 0; 3409467b48Spatrick uint32_t IEEEMode = 0; 3509467b48Spatrick uint32_t WgpMode = 0; // GFX10+ 3609467b48Spatrick uint32_t MemOrdered = 0; // GFX10+ 3709467b48Spatrick uint64_t ScratchSize = 0; 3809467b48Spatrick 3909467b48Spatrick // Fields set in PGM_RSRC2 pm4 packet. 4009467b48Spatrick uint32_t LDSBlocks = 0; 4109467b48Spatrick uint32_t ScratchBlocks = 0; 4209467b48Spatrick 4309467b48Spatrick uint64_t ComputePGMRSrc2 = 0; 4473471bf0Spatrick uint64_t ComputePGMRSrc3GFX90A = 0; 4509467b48Spatrick 4609467b48Spatrick uint32_t NumVGPR = 0; 4709467b48Spatrick uint32_t NumArchVGPR = 0; 4809467b48Spatrick uint32_t NumAccVGPR = 0; 4973471bf0Spatrick uint32_t AccumOffset = 0; 5073471bf0Spatrick uint32_t TgSplit = 0; 5109467b48Spatrick uint32_t NumSGPR = 0; 52*d415bd75Srobert unsigned SGPRSpill = 0; 53*d415bd75Srobert unsigned VGPRSpill = 0; 5409467b48Spatrick uint32_t LDSSize = 0; 5509467b48Spatrick bool FlatUsed = false; 5609467b48Spatrick 5709467b48Spatrick // Number of SGPRs that meets number of waves per execution unit request. 5809467b48Spatrick uint32_t NumSGPRsForWavesPerEU = 0; 5909467b48Spatrick 6009467b48Spatrick // Number of VGPRs that meets number of waves per execution unit request. 6109467b48Spatrick uint32_t NumVGPRsForWavesPerEU = 0; 6209467b48Spatrick 6309467b48Spatrick // Final occupancy. 6409467b48Spatrick uint32_t Occupancy = 0; 6509467b48Spatrick 6609467b48Spatrick // Whether there is recursion, dynamic allocas, indirect calls or some other 6709467b48Spatrick // reason there may be statically unknown stack usage. 6809467b48Spatrick bool DynamicCallStack = false; 6909467b48Spatrick 7009467b48Spatrick // Bonus information for debugging. 7109467b48Spatrick bool VCCUsed = false; 7209467b48Spatrick 7309467b48Spatrick SIProgramInfo() = default; 7473471bf0Spatrick 7573471bf0Spatrick /// Compute the value of the ComputePGMRsrc1 register. 7673471bf0Spatrick uint64_t getComputePGMRSrc1() const; 7773471bf0Spatrick uint64_t getPGMRSrc1(CallingConv::ID CC) const; 7809467b48Spatrick }; 7909467b48Spatrick 8009467b48Spatrick } // namespace llvm 8109467b48Spatrick 8209467b48Spatrick #endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H 83