1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_MC_H 28*0Sstevel@tonic-gate #define _SYS_MC_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * Interface of Memory Controller driver 38*0Sstevel@tonic-gate * 39*0Sstevel@tonic-gate * Logical view: memory -> segment -> bank -> device group -> device 40*0Sstevel@tonic-gate * physical view: mc -> device group -> device 41*0Sstevel@tonic-gate * 42*0Sstevel@tonic-gate * MCIOC_MEM, MCIOC_SEG, MCIOC_CTRLCONF, MCIOC_CONTROL are 43*0Sstevel@tonic-gate * associated with various length struct. If given number is less than the 44*0Sstevel@tonic-gate * number in kernel, kernel will update the number and return EINVAL so that 45*0Sstevel@tonic-gate * user could allocate enough space for the struct and fill the right number 46*0Sstevel@tonic-gate * of ids at the struct. 47*0Sstevel@tonic-gate * 48*0Sstevel@tonic-gate * All varaiable number ids will be paired, global and local. Global id is 49*0Sstevel@tonic-gate * unique in the same object list and local id is only unique to 50*0Sstevel@tonic-gate * its upper layer. For instance, one memory module group has N memory modules. 51*0Sstevel@tonic-gate * local ids of this memory module group is from 0 to N - 1, but global id 52*0Sstevel@tonic-gate * is unique in all memory modules. So global id will be the key in the list 53*0Sstevel@tonic-gate * and pass it to driver to search. Local id will be returned to user 54*0Sstevel@tonic-gate * application via ioctl. 55*0Sstevel@tonic-gate */ 56*0Sstevel@tonic-gate 57*0Sstevel@tonic-gate #define MCIOC ('M' << 8) 58*0Sstevel@tonic-gate #define MCIOC_MEMCONF (MCIOC|8) 59*0Sstevel@tonic-gate #define MCIOC_MEM (MCIOC|9) 60*0Sstevel@tonic-gate #define MCIOC_SEG (MCIOC|10) 61*0Sstevel@tonic-gate #define MCIOC_BANK (MCIOC|11) 62*0Sstevel@tonic-gate #define MCIOC_DEVGRP (MCIOC|12) 63*0Sstevel@tonic-gate #define MCIOC_CTRLCONF (MCIOC|13) 64*0Sstevel@tonic-gate #define MCIOC_CONTROL (MCIOC|14) 65*0Sstevel@tonic-gate #define MCIOC_ECFLUSH (MCIOC|15) 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate /* 68*0Sstevel@tonic-gate * libdevinfo property name for exporting the Memory Address 69*0Sstevel@tonic-gate * Decode Registers for each Logical bank. An array of [NBANK] 70*0Sstevel@tonic-gate * uint64_t's is created for each memory-controller node. 71*0Sstevel@tonic-gate */ 72*0Sstevel@tonic-gate #define MEM_CFG_PROP_NAME "logical-bank-ma-regs" 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate struct mc_ids { 75*0Sstevel@tonic-gate int globalid; 76*0Sstevel@tonic-gate int localid; 77*0Sstevel@tonic-gate }; 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate /* 80*0Sstevel@tonic-gate * Enabled memory controller is able to get memory-layout property, and 81*0Sstevel@tonic-gate * it could be with or without memory. 82*0Sstevel@tonic-gate */ 83*0Sstevel@tonic-gate struct mc_memconf { 84*0Sstevel@tonic-gate int nmcs; /* The number of enabled memory controllers */ 85*0Sstevel@tonic-gate int nsegments; /* The number of memory segments */ 86*0Sstevel@tonic-gate int nbanks; /* The max. number of banks per segment */ 87*0Sstevel@tonic-gate int ndevgrps; /* The max. number of device groups per mc */ 88*0Sstevel@tonic-gate int ndevs; /* The max. number of devices per device group */ 89*0Sstevel@tonic-gate int len_dev; /* The length of device label */ 90*0Sstevel@tonic-gate int xfer_size; /* Data transfer size in CPU cache line */ 91*0Sstevel@tonic-gate }; 92*0Sstevel@tonic-gate 93*0Sstevel@tonic-gate struct mc_memory { 94*0Sstevel@tonic-gate uint64_t size; /* size of physical memory */ 95*0Sstevel@tonic-gate int nsegments; /* The number of memory segments */ 96*0Sstevel@tonic-gate struct mc_ids segmentids[1]; /* segment ids for next iteration */ 97*0Sstevel@tonic-gate }; 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate struct mc_segment { 100*0Sstevel@tonic-gate int id; /* unique segment id */ 101*0Sstevel@tonic-gate int ifactor; /* interleave factor for this segment */ 102*0Sstevel@tonic-gate uint64_t base; /* starting physical address */ 103*0Sstevel@tonic-gate uint64_t size; /* in bytes */ 104*0Sstevel@tonic-gate int nbanks; /* The number of banks at this segment */ 105*0Sstevel@tonic-gate struct mc_ids bankids[1]; /* logical bank ids for next iteration */ 106*0Sstevel@tonic-gate }; 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate struct mc_bank { 109*0Sstevel@tonic-gate int id; /* unique id for logic bank */ 110*0Sstevel@tonic-gate struct mc_ids devgrpid; /* Only one device group id per logical bank */ 111*0Sstevel@tonic-gate uint64_t mask; /* If (Physic Address & MASK) == MATCH, */ 112*0Sstevel@tonic-gate uint64_t match; /* Physic Address is located at this bank. */ 113*0Sstevel@tonic-gate uint64_t size; /* memory size per logical bank */ 114*0Sstevel@tonic-gate }; 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate struct mc_ctrlconf { 117*0Sstevel@tonic-gate int nmcs; /* The number of enabled memory controllers */ 118*0Sstevel@tonic-gate struct mc_ids mcids[1]; /* mc ids for next iteration */ 119*0Sstevel@tonic-gate }; 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate struct mc_control { 122*0Sstevel@tonic-gate int id; /* unique id for memory controllers */ 123*0Sstevel@tonic-gate int ndevgrps; /* The number of device groups on this mc */ 124*0Sstevel@tonic-gate struct mc_ids devgrpids[1]; /* device group ids for next iteration */ 125*0Sstevel@tonic-gate }; 126*0Sstevel@tonic-gate 127*0Sstevel@tonic-gate struct mc_devgrp { 128*0Sstevel@tonic-gate int id; /* unique id for device groups */ 129*0Sstevel@tonic-gate int ndevices; /* The number of available devices on this dev group */ 130*0Sstevel@tonic-gate uint64_t size; /* memory size per physical dimm group */ 131*0Sstevel@tonic-gate }; 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate #ifdef __cplusplus 134*0Sstevel@tonic-gate } 135*0Sstevel@tonic-gate #endif 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate #endif /* _SYS_MC_H */ 138