1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_MACHINTREG_H 28*0Sstevel@tonic-gate #define _SYS_MACHINTREG_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * Interrupt Receive Data Registers 38*0Sstevel@tonic-gate * ASI_SDB_INTR_R or ASI_INTR_RECEIVE; ASI 0x7F; VA 0x40, 0x50, 0x60 39*0Sstevel@tonic-gate */ 40*0Sstevel@tonic-gate #define IRDR_0 0x40 41*0Sstevel@tonic-gate #define IRDR_1 0x50 42*0Sstevel@tonic-gate #define IRDR_2 0x60 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate #define UIII_IRDR_0 0x40 45*0Sstevel@tonic-gate #define UIII_IRDR_1 0x48 46*0Sstevel@tonic-gate #define UIII_IRDR_2 0x50 47*0Sstevel@tonic-gate #define UIII_IRDR_3 0x58 48*0Sstevel@tonic-gate #define UIII_IRDR_4 0x60 49*0Sstevel@tonic-gate #define UIII_IRDR_5 0x68 50*0Sstevel@tonic-gate #define UIII_IRDR_6 0x80 51*0Sstevel@tonic-gate #define UIII_IRDR_7 0x88 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate /* 54*0Sstevel@tonic-gate * Interrupt Receive Status Register 55*0Sstevel@tonic-gate * ASI_INTR_RECEIVE_STATUS; ASI 0x49; VA 0x0 56*0Sstevel@tonic-gate * 57*0Sstevel@tonic-gate * |---------------------------------------------------| 58*0Sstevel@tonic-gate * | RESERVED (Read as 0) | BUSY | PORTID | 59*0Sstevel@tonic-gate * |--------------------------------|------|-----------| 60*0Sstevel@tonic-gate * 63 6 5 4 0 61*0Sstevel@tonic-gate * 62*0Sstevel@tonic-gate */ 63*0Sstevel@tonic-gate #define IRSR_BUSY 0x20 /* set when there's a vector received */ 64*0Sstevel@tonic-gate #define IRSR_PID_MASK 0x1F /* PORTID bit mask <4:0> */ 65*0Sstevel@tonic-gate 66*0Sstevel@tonic-gate /* 67*0Sstevel@tonic-gate * Interrupt Dispatch Data Register 68*0Sstevel@tonic-gate * ASI_SDB_INTR_W or ASI_INTR_DISPATCH; ASI 0x77; VA 0x40, 0x50, 0x60 69*0Sstevel@tonic-gate */ 70*0Sstevel@tonic-gate #define IDDR_0 0x40 71*0Sstevel@tonic-gate #define IDDR_1 0x50 72*0Sstevel@tonic-gate #define IDDR_2 0x60 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate #define UIII_IDDR_0 0x40 75*0Sstevel@tonic-gate #define UIII_IDDR_1 0x48 76*0Sstevel@tonic-gate #define UIII_IDDR_2 0x50 77*0Sstevel@tonic-gate #define UIII_IDDR_3 0x58 78*0Sstevel@tonic-gate #define UIII_IDDR_4 0x60 79*0Sstevel@tonic-gate #define UIII_IDDR_5 0x68 80*0Sstevel@tonic-gate #define UIII_IDDR_6 0x80 81*0Sstevel@tonic-gate #define UIII_IDDR_7 0x88 82*0Sstevel@tonic-gate 83*0Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO) 84*0Sstevel@tonic-gate /* 85*0Sstevel@tonic-gate * Interrupt Dispatch Command Register 86*0Sstevel@tonic-gate * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 87*0Sstevel@tonic-gate * 88*0Sstevel@tonic-gate * |------------------------------------------------| 89*0Sstevel@tonic-gate * | 0 | PORTID & BUSY/NACK | 0x70 | 90*0Sstevel@tonic-gate * |---------|-----------------------|--------------| 91*0Sstevel@tonic-gate * 63 19 18 14 13 0 92*0Sstevel@tonic-gate */ 93*0Sstevel@tonic-gate #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 94*0Sstevel@tonic-gate #define IDCR_PID_SHIFT 14 95*0Sstevel@tonic-gate #define IDCR_BN_SHIFT 14 /* JBUS only */ 96*0Sstevel@tonic-gate #define IDCR_BN_MASK 0x3 /* JBUS only */ 97*0Sstevel@tonic-gate #else /* (JALAPENO || SERRANO) */ 98*0Sstevel@tonic-gate /* 99*0Sstevel@tonic-gate * Interrupt Dispatch Command Register 100*0Sstevel@tonic-gate * ASI_INTR_DISPATCH or ASI_SDB_INTR_W; ASI 0x77; VA = PORTID<<14|0x70 101*0Sstevel@tonic-gate * 102*0Sstevel@tonic-gate * |------------------------------------------------| 103*0Sstevel@tonic-gate * | 0 | BUSY/NACK | PORTID | 0x70 | 104*0Sstevel@tonic-gate * |---------|-----------|-----------|--------------| 105*0Sstevel@tonic-gate * 63 29 28 24 23 14 13 0 106*0Sstevel@tonic-gate */ 107*0Sstevel@tonic-gate #define IDCR_OFFSET 0x70 /* IDCR VA<13:0> */ 108*0Sstevel@tonic-gate #define IDCR_PID_SHIFT 14 109*0Sstevel@tonic-gate #define IDCR_BN_SHIFT 24 /* safari only */ 110*0Sstevel@tonic-gate #endif /* (JALAPENO || SERRANO) */ 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate /* 113*0Sstevel@tonic-gate * Interrupt Dispatch Status Register 114*0Sstevel@tonic-gate * ASI_INTR_DISPATCH_STATUS; ASI 0x48; VA 0x0 115*0Sstevel@tonic-gate * 116*0Sstevel@tonic-gate * |---------------------------------------------------| 117*0Sstevel@tonic-gate * | RESERVED (Read as 0) | NACK | BUSY | 118*0Sstevel@tonic-gate * |-----------------------------------|-------|-------| 119*0Sstevel@tonic-gate * 63 2 1 0 | 120*0Sstevel@tonic-gate */ 121*0Sstevel@tonic-gate #define IDSR_NACK 0x2 /* set if interrupt dispatch failed */ 122*0Sstevel@tonic-gate #define IDSR_BUSY 0x1 /* set when there's a dispatch */ 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate /* 125*0Sstevel@tonic-gate * Safari systems define IDSR as 32 busy/nack pairs 126*0Sstevel@tonic-gate */ 127*0Sstevel@tonic-gate #if defined(JALAPENO) || defined(SERRANO) 128*0Sstevel@tonic-gate #define IDSR_BN_SETS 4 129*0Sstevel@tonic-gate #define CPUID_TO_BN_PAIR(x) ((x) & (IDSR_BN_SETS-1)) 130*0Sstevel@tonic-gate #else /* (JALAPENO || SERRANO) */ 131*0Sstevel@tonic-gate #define IDSR_BN_SETS 32 132*0Sstevel@tonic-gate #endif /* (JALAPENO || SERRANO) */ 133*0Sstevel@tonic-gate #define IDSR_NACK_BIT(i) ((uint64_t)IDSR_NACK << (2 * (i))) 134*0Sstevel@tonic-gate #define IDSR_BUSY_BIT(i) ((uint64_t)IDSR_BUSY << (2 * (i))) 135*0Sstevel@tonic-gate #define IDSR_NACK_TO_BUSY(n) ((n) >> 1) 136*0Sstevel@tonic-gate #define IDSR_BUSY_TO_NACK(n) ((n) << 1) 137*0Sstevel@tonic-gate #define IDSR_NACK_IDX(bit) (((bit) - 1) / 2) 138*0Sstevel@tonic-gate #define IDSR_BUSY_IDX(bit) ((bit) / 2) 139*0Sstevel@tonic-gate 140*0Sstevel@tonic-gate /* 141*0Sstevel@tonic-gate * Interrupt Number Register 142*0Sstevel@tonic-gate * Every interrupt source has a register associated with it 143*0Sstevel@tonic-gate * 144*0Sstevel@tonic-gate * |---------------------------------------------------| 145*0Sstevel@tonic-gate * |INT_EN | PORTID |RESERVED (Read as 0)| INT_NUMBER| 146*0Sstevel@tonic-gate * | | | | IGN | INO | 147*0Sstevel@tonic-gate * |-------|----------|--------------------|-----|-----| 148*0Sstevel@tonic-gate * | 31 30 26 25 11 10 6 5 0 149*0Sstevel@tonic-gate */ 150*0Sstevel@tonic-gate #define INR_EN_SHIFT 31 151*0Sstevel@tonic-gate #define INR_PID_SHIFT 26 152*0Sstevel@tonic-gate #define INR_PID_MASK (IRSR_PID_MASK << (INR_PID_SHIFT)) 153*0Sstevel@tonic-gate #ifdef _STARFIRE 154*0Sstevel@tonic-gate /* 155*0Sstevel@tonic-gate * Starfire interrupt group number is 7 bits 156*0Sstevel@tonic-gate * Starfire's IGN (inter group #) is not the same as upaid 157*0Sstevel@tonic-gate */ 158*0Sstevel@tonic-gate #define IGN_SIZE 7 /* Interrupt Group Number bit size */ 159*0Sstevel@tonic-gate #define UPAID_TO_IGN(upaid) ((((upaid & 0x3C) >> 1) | (upaid & 0x1)) | \ 160*0Sstevel@tonic-gate (((upaid & 0x2) << 4) | \ 161*0Sstevel@tonic-gate ((upaid & 0x40) ^ 0x40))) 162*0Sstevel@tonic-gate #else 163*0Sstevel@tonic-gate /* 164*0Sstevel@tonic-gate * IGN_SIZE can be defined in a platform's makefile. If it is not defined, 165*0Sstevel@tonic-gate * use a default of 5. 166*0Sstevel@tonic-gate */ 167*0Sstevel@tonic-gate #ifndef IGN_SIZE 168*0Sstevel@tonic-gate #define IGN_SIZE 5 /* Interrupt Group Number bit size */ 169*0Sstevel@tonic-gate #endif 170*0Sstevel@tonic-gate #define UPAID_TO_IGN(upaid) (upaid) 171*0Sstevel@tonic-gate #endif /* _STARFIRE */ 172*0Sstevel@tonic-gate 173*0Sstevel@tonic-gate #define IR_CPU_CLEAR 0x4 /* clear pending register for cpu */ 174*0Sstevel@tonic-gate #define IR_MASK_OFFSET 0x4 175*0Sstevel@tonic-gate #define IR_SET_ITR 0x10 176*0Sstevel@tonic-gate #define IR_SOFT_INT(n) (0x000010000 << (n)) 177*0Sstevel@tonic-gate #define IR_SOFT_INT4 IR_SOFT_INT(4) /* r/w - software level 4 interrupt */ 178*0Sstevel@tonic-gate #define IR_CPU_SOFTINT 0x8 /* set soft interrupt for cpu */ 179*0Sstevel@tonic-gate #define IR_CLEAR_OFFSET 0x8 180*0Sstevel@tonic-gate 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate #ifdef __cplusplus 183*0Sstevel@tonic-gate } 184*0Sstevel@tonic-gate #endif 185*0Sstevel@tonic-gate 186*0Sstevel@tonic-gate #endif /* _SYS_MACHINTREG_H */ 187