1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_MACHCPUVAR_H 28*0Sstevel@tonic-gate #define _SYS_MACHCPUVAR_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #include <sys/intr.h> 33*0Sstevel@tonic-gate #include <sys/clock.h> 34*0Sstevel@tonic-gate #include <sys/machparam.h> 35*0Sstevel@tonic-gate #include <sys/machpcb.h> 36*0Sstevel@tonic-gate #include <sys/privregs.h> 37*0Sstevel@tonic-gate #include <sys/machlock.h> 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate #ifdef __cplusplus 40*0Sstevel@tonic-gate extern "C" { 41*0Sstevel@tonic-gate #endif 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate #ifndef _ASM 44*0Sstevel@tonic-gate 45*0Sstevel@tonic-gate #include <sys/obpdefs.h> 46*0Sstevel@tonic-gate #include <sys/async.h> 47*0Sstevel@tonic-gate #include <sys/fm/protocol.h> 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate /* 50*0Sstevel@tonic-gate * CPU state ptl1_panic save. 51*0Sstevel@tonic-gate */ 52*0Sstevel@tonic-gate typedef struct ptl1_trapregs { 53*0Sstevel@tonic-gate uint32_t ptl1_tl; 54*0Sstevel@tonic-gate uint32_t ptl1_tt; 55*0Sstevel@tonic-gate uint64_t ptl1_tstate; 56*0Sstevel@tonic-gate uint64_t ptl1_tpc; 57*0Sstevel@tonic-gate uint64_t ptl1_tnpc; 58*0Sstevel@tonic-gate } ptl1_trapregs_t; 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate typedef struct ptl1_regs { 61*0Sstevel@tonic-gate ptl1_trapregs_t ptl1_trap_regs[PTL1_MAXTL]; 62*0Sstevel@tonic-gate uint64_t ptl1_g1; 63*0Sstevel@tonic-gate uint64_t ptl1_g2; 64*0Sstevel@tonic-gate uint64_t ptl1_g3; 65*0Sstevel@tonic-gate uint64_t ptl1_g4; 66*0Sstevel@tonic-gate uint64_t ptl1_g5; 67*0Sstevel@tonic-gate uint64_t ptl1_g6; 68*0Sstevel@tonic-gate uint64_t ptl1_g7; 69*0Sstevel@tonic-gate uint64_t ptl1_tick; 70*0Sstevel@tonic-gate uint64_t ptl1_dmmu_sfar; 71*0Sstevel@tonic-gate uint64_t ptl1_dmmu_sfsr; 72*0Sstevel@tonic-gate uint64_t ptl1_dmmu_tag_access; 73*0Sstevel@tonic-gate uint64_t ptl1_immu_sfsr; 74*0Sstevel@tonic-gate uint64_t ptl1_immu_tag_access; 75*0Sstevel@tonic-gate struct rwindow ptl1_rwindow[MAXWIN]; 76*0Sstevel@tonic-gate uint32_t ptl1_softint; 77*0Sstevel@tonic-gate uint16_t ptl1_pstate; 78*0Sstevel@tonic-gate uint8_t ptl1_pil; 79*0Sstevel@tonic-gate uint8_t ptl1_cwp; 80*0Sstevel@tonic-gate uint8_t ptl1_wstate; 81*0Sstevel@tonic-gate uint8_t ptl1_otherwin; 82*0Sstevel@tonic-gate uint8_t ptl1_cleanwin; 83*0Sstevel@tonic-gate uint8_t ptl1_cansave; 84*0Sstevel@tonic-gate uint8_t ptl1_canrestore; 85*0Sstevel@tonic-gate } ptl1_regs_t; 86*0Sstevel@tonic-gate 87*0Sstevel@tonic-gate typedef struct ptl1_state { 88*0Sstevel@tonic-gate ptl1_regs_t ptl1_regs; 89*0Sstevel@tonic-gate uint32_t ptl1_entry_count; 90*0Sstevel@tonic-gate uintptr_t ptl1_stktop; 91*0Sstevel@tonic-gate ulong_t ptl1_stk[1]; 92*0Sstevel@tonic-gate } ptl1_state_t; 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* 95*0Sstevel@tonic-gate * Machine specific fields of the cpu struct 96*0Sstevel@tonic-gate * defined in common/sys/cpuvar.h. 97*0Sstevel@tonic-gate */ 98*0Sstevel@tonic-gate struct machcpu { 99*0Sstevel@tonic-gate struct machpcb *mpcb; 100*0Sstevel@tonic-gate uint64_t mpcb_pa; 101*0Sstevel@tonic-gate int mutex_ready; 102*0Sstevel@tonic-gate int in_prom; 103*0Sstevel@tonic-gate int tl1_hdlr; 104*0Sstevel@tonic-gate uint16_t divisor; /* Estar %tick clock ratio */ 105*0Sstevel@tonic-gate uint8_t intrcnt; /* number of back-to-back interrupts */ 106*0Sstevel@tonic-gate u_longlong_t tmp1; /* per-cpu tmps */ 107*0Sstevel@tonic-gate u_longlong_t tmp2; /* used in trap processing */ 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate struct intr_req intr_pool[INTR_PENDING_MAX]; /* intr pool */ 110*0Sstevel@tonic-gate struct intr_req *intr_head[PIL_LEVELS]; /* intr que heads */ 111*0Sstevel@tonic-gate struct intr_req *intr_tail[PIL_LEVELS]; /* intr que tails */ 112*0Sstevel@tonic-gate int intr_pool_added; /* add'l intr pool */ 113*0Sstevel@tonic-gate boolean_t poke_cpu_outstanding; 114*0Sstevel@tonic-gate /* 115*0Sstevel@tonic-gate * The cpu module allocates a private data structure for the 116*0Sstevel@tonic-gate * E$ data, which is needed for the specific cpu type. 117*0Sstevel@tonic-gate */ 118*0Sstevel@tonic-gate void *cpu_private; /* ptr to cpu private data */ 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate ptl1_state_t ptl1_state; 121*0Sstevel@tonic-gate 122*0Sstevel@tonic-gate uint64_t pil_high_start[HIGH_LEVELS]; /* high-level intrs */ 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate /* 125*0Sstevel@tonic-gate * intrstat[][] is used to keep track of ticks used at a given pil 126*0Sstevel@tonic-gate * level. intrstat[pil][0] is cumulative and exported via kstats. 127*0Sstevel@tonic-gate * intrstat[pil][1] is used in intr_get_time() and is private. 128*0Sstevel@tonic-gate * 2-dimensional array improves cache locality. 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate uint64_t intrstat[PIL_MAX+1][2]; 132*0Sstevel@tonic-gate }; 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate typedef struct machcpu machcpu_t; 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate /* 137*0Sstevel@tonic-gate * Macro to access the "cpu private" data structure. 138*0Sstevel@tonic-gate */ 139*0Sstevel@tonic-gate #define CPU_PRIVATE(cp) ((cp)->cpu_m.cpu_private) 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate /* 142*0Sstevel@tonic-gate * The OpenBoot Standalone Interface supplies the kernel with 143*0Sstevel@tonic-gate * implementation dependent parameters through the devinfo/property mechanism 144*0Sstevel@tonic-gate */ 145*0Sstevel@tonic-gate #define MAXSYSNAME 20 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate /* 148*0Sstevel@tonic-gate * Used to indicate busy/idle state of a cpu. 149*0Sstevel@tonic-gate * msram field will be set with ECACHE_CPU_MIRROR if we are on 150*0Sstevel@tonic-gate * mirrored sram module. 151*0Sstevel@tonic-gate */ 152*0Sstevel@tonic-gate #define ECACHE_CPU_IDLE 0x0 /* CPU is idle */ 153*0Sstevel@tonic-gate #define ECACHE_CPU_BUSY 0x1 /* CPU is busy */ 154*0Sstevel@tonic-gate #define ECACHE_CPU_MIRROR 0x2 /* E$ is mirrored */ 155*0Sstevel@tonic-gate #define ECACHE_CPU_NON_MIRROR 0x3 /* E$ is not mirrored */ 156*0Sstevel@tonic-gate 157*0Sstevel@tonic-gate /* 158*0Sstevel@tonic-gate * A CPU FRU FMRI string minus the unum component. 159*0Sstevel@tonic-gate */ 160*0Sstevel@tonic-gate #define CPU_FRU_FMRI FM_FMRI_SCHEME_HC":///" \ 161*0Sstevel@tonic-gate FM_FMRI_LEGACY_HC"=" 162*0Sstevel@tonic-gate 163*0Sstevel@tonic-gate struct cpu_node { 164*0Sstevel@tonic-gate char name[MAXSYSNAME]; 165*0Sstevel@tonic-gate char fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN]; 166*0Sstevel@tonic-gate int implementation; 167*0Sstevel@tonic-gate int version; 168*0Sstevel@tonic-gate int portid; 169*0Sstevel@tonic-gate dnode_t nodeid; 170*0Sstevel@tonic-gate uint64_t clock_freq; 171*0Sstevel@tonic-gate uint_t tick_nsec_scale; 172*0Sstevel@tonic-gate union { 173*0Sstevel@tonic-gate int dummy; 174*0Sstevel@tonic-gate } u_info; 175*0Sstevel@tonic-gate int ecache_size; 176*0Sstevel@tonic-gate int ecache_linesize; 177*0Sstevel@tonic-gate int ecache_associativity; 178*0Sstevel@tonic-gate int ecache_setsize; 179*0Sstevel@tonic-gate ushort_t itlb_size; 180*0Sstevel@tonic-gate ushort_t dtlb_size; 181*0Sstevel@tonic-gate int msram; 182*0Sstevel@tonic-gate uint64_t device_id; 183*0Sstevel@tonic-gate }; 184*0Sstevel@tonic-gate 185*0Sstevel@tonic-gate extern struct cpu_node cpunodes[]; 186*0Sstevel@tonic-gate 187*0Sstevel@tonic-gate #endif /* _ASM */ 188*0Sstevel@tonic-gate 189*0Sstevel@tonic-gate #ifdef __cplusplus 190*0Sstevel@tonic-gate } 191*0Sstevel@tonic-gate #endif 192*0Sstevel@tonic-gate 193*0Sstevel@tonic-gate #endif /* _SYS_MACHCPUVAR_H */ 194