1*1341Sstevel /* 2*1341Sstevel * CDDL HEADER START 3*1341Sstevel * 4*1341Sstevel * The contents of this file are subject to the terms of the 5*1341Sstevel * Common Development and Distribution License (the "License"). 6*1341Sstevel * You may not use this file except in compliance with the License. 7*1341Sstevel * 8*1341Sstevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*1341Sstevel * or http://www.opensolaris.org/os/licensing. 10*1341Sstevel * See the License for the specific language governing permissions 11*1341Sstevel * and limitations under the License. 12*1341Sstevel * 13*1341Sstevel * When distributing Covered Code, include this CDDL HEADER in each 14*1341Sstevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*1341Sstevel * If applicable, add the following below this CDDL HEADER, with the 16*1341Sstevel * fields enclosed by brackets "[]" replaced with your own identifying 17*1341Sstevel * information: Portions Copyright [yyyy] [name of copyright owner] 18*1341Sstevel * 19*1341Sstevel * CDDL HEADER END 20*1341Sstevel */ 21*1341Sstevel 22*1341Sstevel /* 23*1341Sstevel * Copyright 1998 Sun Microsystems, Inc. All rights reserved. 24*1341Sstevel * Use is subject to license terms. 25*1341Sstevel */ 26*1341Sstevel 27*1341Sstevel #ifndef _SYS_ENVCTRL_UE250_H 28*1341Sstevel #define _SYS_ENVCTRL_UE250_H 29*1341Sstevel 30*1341Sstevel #pragma ident "%Z%%M% %I% %E% SMI" 31*1341Sstevel 32*1341Sstevel #ifdef __cplusplus 33*1341Sstevel extern "C" { 34*1341Sstevel #endif 35*1341Sstevel 36*1341Sstevel /* 37*1341Sstevel * envctrl_ue250.h 38*1341Sstevel * 39*1341Sstevel * This header file contains environmental control definitions specific 40*1341Sstevel * to the UltraEnterprise-250 platform. 41*1341Sstevel */ 42*1341Sstevel 43*1341Sstevel #define ENVCTRL_UE250_OVERTEMP_TIMEOUT_USEC 60 * MICROSEC 44*1341Sstevel #define ENVCTRL_UE250_BLINK_TIMEOUT_USEC 500 * (MICROSEC / MILLISEC) 45*1341Sstevel 46*1341Sstevel /* Keyswitch Definitions */ 47*1341Sstevel #define ENVCTRL_UE250_FSP_KEYMASK 0xC0 48*1341Sstevel #define ENVCTRL_UE250_FSP_POMASK 0x20 49*1341Sstevel #define ENVCTRL_UE250_FSP_KEYLOCKED 0x00 50*1341Sstevel #define ENVCTRL_UE250_FSP_KEYOFF 0xC0 51*1341Sstevel #define ENVCTRL_UE250_FSP_KEYDIAG 0x80 52*1341Sstevel #define ENVCTRL_UE250_FSP_KEYON 0x40 53*1341Sstevel 54*1341Sstevel /* Front Status Panel Definitions */ 55*1341Sstevel #define ENVCTRL_UE250_FSP_DISK_ERR 0x01 56*1341Sstevel #define ENVCTRL_UE250_FSP_PS_ERR 0x02 57*1341Sstevel #define ENVCTRL_UE250_FSP_TEMP_ERR 0x04 58*1341Sstevel #define ENVCTRL_UE250_FSP_GEN_ERR 0x08 59*1341Sstevel #define ENVCTRL_UE250_FSP_ACTIVE 0x10 60*1341Sstevel #define ENVCTRL_UE250_FSP_POWER 0x20 61*1341Sstevel #define ENVCTRL_UE250_FSP_USRMASK \ 62*1341Sstevel (ENVCTRL_UE250_FSP_DISK_ERR | ENVCTRL_UE250_FSP_GEN_ERR) 63*1341Sstevel 64*1341Sstevel #define ENVCTRL_UE250_FSP_OFF 0x4F 65*1341Sstevel 66*1341Sstevel #define ENVCTRL_UE250_MAX_DISKS 6 67*1341Sstevel #define ENVCTRL_UE250_MAXPS 0x02 /* 0 based array */ 68*1341Sstevel 69*1341Sstevel #define ENVCTRL_UE250_PDB_TEMP_DEV 0x94 70*1341Sstevel #define ENVCTRL_UE250_CPU_TEMP_DEV 0x9E 71*1341Sstevel #define ENVCTRL_UE250_CPU0_PORT 0 72*1341Sstevel #define ENVCTRL_UE250_CPU1_PORT 1 73*1341Sstevel #define ENVCTRL_UE250_MB0_PORT 2 74*1341Sstevel #define ENVCTRL_UE250_MB1_PORT 3 75*1341Sstevel #define ENVCTRL_UE250_PDB_TEMP_PORT 0 76*1341Sstevel #define ENVCTRL_UE250_SCSI_TEMP_PORT 3 77*1341Sstevel 78*1341Sstevel #define ENVCTRL_UE250_CPU0_SENSOR 0 79*1341Sstevel #define ENVCTRL_UE250_CPU1_SENSOR 1 80*1341Sstevel #define ENVCTRL_UE250_MB0_SENSOR 2 81*1341Sstevel #define ENVCTRL_UE250_MB1_SENSOR 3 82*1341Sstevel #define ENVCTRL_UE250_PDB_SENSOR 4 83*1341Sstevel #define ENVCTRL_UE250_SCSI_SENSOR 5 84*1341Sstevel 85*1341Sstevel #define ENVCTRL_UE250_MAX_CPU_TEMP 80 86*1341Sstevel 87*1341Sstevel #define ENVCTRL_UE250_PCF8591_BASE_ADDR 0x90 88*1341Sstevel #define ENVCTRL_UE250_PCF8574A_BASE_ADDR 0x70 89*1341Sstevel #define ENVCTRL_UE250_PCF8574_BASE_ADDR 0x40 90*1341Sstevel 91*1341Sstevel #define ENVCTRL_UE250_DFLOP_INIT0 0x77 92*1341Sstevel #define ENVCTRL_UE250_DFLOP_INIT1 0x7F 93*1341Sstevel #define ENVCTRL_UE250_DEVINTR_INIT0 0xF7 94*1341Sstevel #define ENVCTRL_UE250_DEVINTR_INIT1 0xFF 95*1341Sstevel #define ENVCTRL_UE250_INTR_LATCH_CLR 0xFE 96*1341Sstevel 97*1341Sstevel #ifdef __cplusplus 98*1341Sstevel } 99*1341Sstevel #endif 100*1341Sstevel 101*1341Sstevel #endif /* _SYS_ENVCTRL_UE250_H */ 102