127Sjchu /* 227Sjchu * CDDL HEADER START 327Sjchu * 427Sjchu * The contents of this file are subject to the terms of the 51772Sjl139090 * Common Development and Distribution License (the "License"). 61772Sjl139090 * You may not use this file except in compliance with the License. 727Sjchu * 827Sjchu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 927Sjchu * or http://www.opensolaris.org/os/licensing. 1027Sjchu * See the License for the specific language governing permissions 1127Sjchu * and limitations under the License. 1227Sjchu * 1327Sjchu * When distributing Covered Code, include this CDDL HEADER in each 1427Sjchu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1527Sjchu * If applicable, add the following below this CDDL HEADER, with the 1627Sjchu * fields enclosed by brackets "[]" replaced with your own identifying 1727Sjchu * information: Portions Copyright [yyyy] [name of copyright owner] 1827Sjchu * 1927Sjchu * CDDL HEADER END 2027Sjchu */ 2127Sjchu /* 221772Sjl139090 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 2327Sjchu * Use is subject to license terms. 2427Sjchu */ 2527Sjchu 2627Sjchu #ifndef _SYS_PX_ERR_H 2727Sjchu #define _SYS_PX_ERR_H 2827Sjchu 2927Sjchu #pragma ident "%Z%%M% %I% %E% SMI" 3027Sjchu 3127Sjchu #ifdef __cplusplus 3227Sjchu extern "C" { 3327Sjchu #endif 3427Sjchu 3527Sjchu typedef enum { 3627Sjchu PX_ERR_JBC, 371772Sjl139090 PX_ERR_UBC, 3827Sjchu PX_ERR_MMU, 3927Sjchu PX_ERR_IMU, 4027Sjchu PX_ERR_TLU_UE, 4127Sjchu PX_ERR_TLU_CE, 4227Sjchu PX_ERR_TLU_OE, 4327Sjchu PX_ERR_ILU, 4427Sjchu PX_ERR_LPU_LINK, 4527Sjchu PX_ERR_LPU_PHY, 4627Sjchu PX_ERR_LPU_RX, 4727Sjchu PX_ERR_LPU_TX, 4827Sjchu PX_ERR_LPU_LTSSM, 4927Sjchu PX_ERR_LPU_GIGABLZ 5027Sjchu } px_err_id_t; 5127Sjchu 52*2509Sschwartz #define PX_ERR_ENABLE B_TRUE 53*2509Sschwartz #define PX_ERR_DISABLE B_FALSE 54*2509Sschwartz 55*2509Sschwartz void px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base); 56*2509Sschwartz void px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base); 57*2509Sschwartz void px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base, 58*2509Sschwartz boolean_t enable); 5927Sjchu 601772Sjl139090 #define PX_ERR_EN_ALL -1ull 611772Sjl139090 #define PX_ERR_MASK_NONE 0ull 621772Sjl139090 631772Sjl139090 #define LPU_INTR_ENABLE 0ull 641772Sjl139090 #define LPU_INTR_DISABLE -1ull 651772Sjl139090 661772Sjl139090 extern uint64_t px_tlu_ue_intr_mask; 671772Sjl139090 extern uint64_t px_tlu_ue_log_mask; 681772Sjl139090 extern uint64_t px_tlu_ue_count_mask; 691772Sjl139090 701772Sjl139090 extern uint64_t px_tlu_ce_intr_mask; 711772Sjl139090 extern uint64_t px_tlu_ce_log_mask; 721772Sjl139090 extern uint64_t px_tlu_ce_count_mask; 731772Sjl139090 741772Sjl139090 extern uint64_t px_tlu_oe_intr_mask; 751772Sjl139090 extern uint64_t px_tlu_oe_log_mask; 761772Sjl139090 extern uint64_t px_tlu_oe_count_mask; 771772Sjl139090 781772Sjl139090 extern uint64_t px_mmu_intr_mask; 791772Sjl139090 extern uint64_t px_mmu_log_mask; 801772Sjl139090 extern uint64_t px_mmu_count_mask; 811772Sjl139090 821772Sjl139090 extern uint64_t px_imu_intr_mask; 831772Sjl139090 extern uint64_t px_imu_log_mask; 841772Sjl139090 extern uint64_t px_imu_count_mask; 851772Sjl139090 861772Sjl139090 extern uint64_t px_ilu_intr_mask; 871772Sjl139090 extern uint64_t px_ilu_log_mask; 881772Sjl139090 extern uint64_t px_ilu_count_mask; 891772Sjl139090 9027Sjchu #ifdef __cplusplus 9127Sjchu } 9227Sjchu #endif 9327Sjchu 9427Sjchu #endif /* _SYS_PX_ERR_H */ 95