1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate /*
30*0Sstevel@tonic-gate * PCI Streaming Cache operations: initialization and configuration
31*0Sstevel@tonic-gate */
32*0Sstevel@tonic-gate
33*0Sstevel@tonic-gate #include <sys/types.h>
34*0Sstevel@tonic-gate #include <sys/kmem.h>
35*0Sstevel@tonic-gate #include <vm/seg_kmem.h>
36*0Sstevel@tonic-gate #include <sys/async.h>
37*0Sstevel@tonic-gate #include <sys/spl.h>
38*0Sstevel@tonic-gate #include <sys/sunddi.h>
39*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
40*0Sstevel@tonic-gate #include <sys/pci/pci_obj.h>
41*0Sstevel@tonic-gate #include <sys/x_call.h> /* XCALL_PIL */
42*0Sstevel@tonic-gate
43*0Sstevel@tonic-gate /*LINTLIBRARY*/
44*0Sstevel@tonic-gate
45*0Sstevel@tonic-gate void
sc_create(pci_t * pci_p)46*0Sstevel@tonic-gate sc_create(pci_t *pci_p)
47*0Sstevel@tonic-gate {
48*0Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip;
49*0Sstevel@tonic-gate sc_t *sc_p;
50*0Sstevel@tonic-gate uint64_t paddr;
51*0Sstevel@tonic-gate
52*0Sstevel@tonic-gate #ifdef lint
53*0Sstevel@tonic-gate dip = dip;
54*0Sstevel@tonic-gate #endif
55*0Sstevel@tonic-gate
56*0Sstevel@tonic-gate if (!pci_stream_buf_exists)
57*0Sstevel@tonic-gate return;
58*0Sstevel@tonic-gate
59*0Sstevel@tonic-gate /*
60*0Sstevel@tonic-gate * Allocate streaming cache state structure and link it to
61*0Sstevel@tonic-gate * the pci state structure.
62*0Sstevel@tonic-gate */
63*0Sstevel@tonic-gate sc_p = (sc_t *)kmem_zalloc(sizeof (sc_t), KM_SLEEP);
64*0Sstevel@tonic-gate pci_p->pci_sc_p = sc_p;
65*0Sstevel@tonic-gate sc_p->sc_pci_p = pci_p;
66*0Sstevel@tonic-gate
67*0Sstevel@tonic-gate pci_sc_setup(sc_p);
68*0Sstevel@tonic-gate sc_p->sc_sync_reg_pa = va_to_pa((char *)sc_p->sc_sync_reg);
69*0Sstevel@tonic-gate
70*0Sstevel@tonic-gate DEBUG3(DBG_ATTACH, dip, "sc_create: ctrl=%x, invl=%x, sync=%x\n",
71*0Sstevel@tonic-gate sc_p->sc_ctrl_reg, sc_p->sc_invl_reg,
72*0Sstevel@tonic-gate sc_p->sc_sync_reg);
73*0Sstevel@tonic-gate DEBUG2(DBG_ATTACH, dip, "sc_create: ctx_invl=%x ctx_match=%x\n",
74*0Sstevel@tonic-gate sc_p->sc_ctx_invl_reg, sc_p->sc_ctx_match_reg);
75*0Sstevel@tonic-gate DEBUG3(DBG_ATTACH, dip,
76*0Sstevel@tonic-gate "sc_create: data_diag=%x, tag_diag=%x, ltag_diag=%x\n",
77*0Sstevel@tonic-gate sc_p->sc_data_diag_acc, sc_p->sc_tag_diag_acc,
78*0Sstevel@tonic-gate sc_p->sc_ltag_diag_acc);
79*0Sstevel@tonic-gate
80*0Sstevel@tonic-gate /*
81*0Sstevel@tonic-gate * Allocate the flush/sync buffer. Make sure it's properly
82*0Sstevel@tonic-gate * aligned.
83*0Sstevel@tonic-gate */
84*0Sstevel@tonic-gate sc_p->sc_sync_flag_base =
85*0Sstevel@tonic-gate vmem_xalloc(static_alloc_arena, PCI_SYNC_FLAG_SIZE,
86*0Sstevel@tonic-gate PCI_SYNC_FLAG_SIZE, 0, 0, NULL, NULL, VM_SLEEP);
87*0Sstevel@tonic-gate sc_p->sc_sync_flag_vaddr = (uint64_t *)sc_p->sc_sync_flag_base;
88*0Sstevel@tonic-gate paddr = (uint64_t)hat_getpfnum(kas.a_hat,
89*0Sstevel@tonic-gate (caddr_t)sc_p->sc_sync_flag_vaddr);
90*0Sstevel@tonic-gate paddr <<= MMU_PAGESHIFT;
91*0Sstevel@tonic-gate paddr += (uint64_t)
92*0Sstevel@tonic-gate ((uintptr_t)sc_p->sc_sync_flag_vaddr & ~MMU_PAGEMASK);
93*0Sstevel@tonic-gate sc_p->sc_sync_flag_pa = paddr;
94*0Sstevel@tonic-gate DEBUG2(DBG_ATTACH, dip, "sc_create: sync buffer - vaddr=%x paddr=%x\n",
95*0Sstevel@tonic-gate sc_p->sc_sync_flag_vaddr, sc_p->sc_sync_flag_pa);
96*0Sstevel@tonic-gate
97*0Sstevel@tonic-gate /*
98*0Sstevel@tonic-gate * Create a mutex to go along with it. While the mutex is held,
99*0Sstevel@tonic-gate * all interrupts should be blocked. This will prevent driver
100*0Sstevel@tonic-gate * interrupt routines from attempting to acquire the mutex while
101*0Sstevel@tonic-gate * held by a lower priority interrupt routine. Note also that
102*0Sstevel@tonic-gate * we now block cross calls as well, to prevent issues with
103*0Sstevel@tonic-gate * relocation.
104*0Sstevel@tonic-gate */
105*0Sstevel@tonic-gate mutex_init(&sc_p->sc_sync_mutex, NULL, MUTEX_DRIVER,
106*0Sstevel@tonic-gate (void *)ipltospl(XCALL_PIL));
107*0Sstevel@tonic-gate
108*0Sstevel@tonic-gate sc_configure(sc_p);
109*0Sstevel@tonic-gate }
110*0Sstevel@tonic-gate
111*0Sstevel@tonic-gate void
sc_destroy(pci_t * pci_p)112*0Sstevel@tonic-gate sc_destroy(pci_t *pci_p)
113*0Sstevel@tonic-gate {
114*0Sstevel@tonic-gate sc_t *sc_p;
115*0Sstevel@tonic-gate
116*0Sstevel@tonic-gate if (!pci_stream_buf_exists)
117*0Sstevel@tonic-gate return;
118*0Sstevel@tonic-gate
119*0Sstevel@tonic-gate sc_p = pci_p->pci_sc_p;
120*0Sstevel@tonic-gate
121*0Sstevel@tonic-gate DEBUG0(DBG_DETACH, pci_p->pci_dip, "sc_destroy:\n");
122*0Sstevel@tonic-gate
123*0Sstevel@tonic-gate vmem_xfree(static_alloc_arena, sc_p->sc_sync_flag_base,
124*0Sstevel@tonic-gate PCI_SYNC_FLAG_SIZE);
125*0Sstevel@tonic-gate
126*0Sstevel@tonic-gate /*
127*0Sstevel@tonic-gate * Free the streaming cache state structure.
128*0Sstevel@tonic-gate */
129*0Sstevel@tonic-gate kmem_free(sc_p, sizeof (sc_t));
130*0Sstevel@tonic-gate pci_p->pci_sc_p = NULL;
131*0Sstevel@tonic-gate }
132*0Sstevel@tonic-gate
133*0Sstevel@tonic-gate void
sc_configure(sc_t * sc_p)134*0Sstevel@tonic-gate sc_configure(sc_t *sc_p)
135*0Sstevel@tonic-gate {
136*0Sstevel@tonic-gate int i, instance;
137*0Sstevel@tonic-gate uint64_t l;
138*0Sstevel@tonic-gate dev_info_t *dip;
139*0Sstevel@tonic-gate
140*0Sstevel@tonic-gate if (!sc_p)
141*0Sstevel@tonic-gate return;
142*0Sstevel@tonic-gate
143*0Sstevel@tonic-gate dip = sc_p->sc_pci_p->pci_dip;
144*0Sstevel@tonic-gate
145*0Sstevel@tonic-gate /*
146*0Sstevel@tonic-gate * Invalidate all streaming cache entries via the diagnostic
147*0Sstevel@tonic-gate * access registers.
148*0Sstevel@tonic-gate */
149*0Sstevel@tonic-gate DEBUG0(DBG_ATTACH, dip, "sc_configure:\n");
150*0Sstevel@tonic-gate *sc_p->sc_ctrl_reg |= COMMON_SC_CTRL_DIAG_ENABLE;
151*0Sstevel@tonic-gate for (i = 0; i < PCI_SBUF_ENTRIES; i++) {
152*0Sstevel@tonic-gate sc_p->sc_tag_diag_acc[i] = 0x0ull;
153*0Sstevel@tonic-gate sc_p->sc_ltag_diag_acc[i] = 0x0ull;
154*0Sstevel@tonic-gate }
155*0Sstevel@tonic-gate
156*0Sstevel@tonic-gate /*
157*0Sstevel@tonic-gate * Configure the streaming cache:
158*0Sstevel@tonic-gate */
159*0Sstevel@tonic-gate l = 0;
160*0Sstevel@tonic-gate instance = ddi_get_instance(dip);
161*0Sstevel@tonic-gate if (pci_stream_buf_enable & (1 << instance))
162*0Sstevel@tonic-gate l |= COMMON_SC_CTRL_ENABLE;
163*0Sstevel@tonic-gate if (pci_rerun_disable & (1 << instance))
164*0Sstevel@tonic-gate l |= COMMON_SC_CTRL_RR__DISABLE;
165*0Sstevel@tonic-gate if (pci_lock_sbuf & (1 << instance))
166*0Sstevel@tonic-gate l |= COMMON_SC_CTRL_LRU_LE;
167*0Sstevel@tonic-gate
168*0Sstevel@tonic-gate /*
169*0Sstevel@tonic-gate * Get any SC configuration changes specific to the chip.
170*0Sstevel@tonic-gate */
171*0Sstevel@tonic-gate l |= pci_sc_configure(sc_p->sc_pci_p);
172*0Sstevel@tonic-gate
173*0Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip,
174*0Sstevel@tonic-gate "sc_configure: writing %x to sc csr\n", l);
175*0Sstevel@tonic-gate *sc_p->sc_ctrl_reg = l;
176*0Sstevel@tonic-gate }
177