152Sdf157793 /* 252Sdf157793 * CDDL HEADER START 352Sdf157793 * 452Sdf157793 * The contents of this file are subject to the terms of the 52877Sanovick * Common Development and Distribution License (the "License"). 6*5973Szk194757 * You may not use this file except in compliance with the License. 752Sdf157793 * 852Sdf157793 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 952Sdf157793 * or http://www.opensolaris.org/os/licensing. 1052Sdf157793 * See the License for the specific language governing permissions 1152Sdf157793 * and limitations under the License. 1252Sdf157793 * 1352Sdf157793 * When distributing Covered Code, include this CDDL HEADER in each 1452Sdf157793 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1552Sdf157793 * If applicable, add the following below this CDDL HEADER, with the 1652Sdf157793 * fields enclosed by brackets "[]" replaced with your own identifying 1752Sdf157793 * information: Portions Copyright [yyyy] [name of copyright owner] 1852Sdf157793 * 1952Sdf157793 * CDDL HEADER END 2052Sdf157793 */ 2152Sdf157793 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ 2252Sdf157793 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ 2352Sdf157793 /* All Rights Reserved */ 2452Sdf157793 2552Sdf157793 /* 26*5973Szk194757 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2752Sdf157793 * Use is subject to license terms. 2852Sdf157793 */ 2952Sdf157793 3052Sdf157793 #ifndef _SYS_SUDEV_H 3152Sdf157793 #define _SYS_SUDEV_H 3252Sdf157793 3352Sdf157793 #pragma ident "%Z%%M% %I% %E% SMI" 3452Sdf157793 3552Sdf157793 #ifdef __cplusplus 3652Sdf157793 extern "C" { 3752Sdf157793 #endif 3852Sdf157793 3952Sdf157793 #include <sys/tty.h> 4052Sdf157793 #include <sys/ksynch.h> 4152Sdf157793 #include <sys/dditypes.h> 4252Sdf157793 #include <sys/types.h> 4352Sdf157793 #include <sys/kstat.h> 4452Sdf157793 4552Sdf157793 /* 4652Sdf157793 * Definitions for INS8250 / 16550 chips 4752Sdf157793 */ 4852Sdf157793 4952Sdf157793 /* defined as offsets from the data register */ 5052Sdf157793 #define DAT 0 /* receive/transmit data */ 5152Sdf157793 #define ICR 1 /* interrupt control register */ 5252Sdf157793 #define ISR 2 /* interrupt status register */ 5352Sdf157793 #define LCR 3 /* line control register */ 5452Sdf157793 #define MCR 4 /* modem control register */ 5552Sdf157793 #define LSR 5 /* line status register */ 5652Sdf157793 #define MSR 6 /* modem status register */ 572877Sanovick #define SPR 7 /* scratchpad register for ST16C554D */ 5852Sdf157793 #define DLL 0 /* divisor latch (lsb) */ 5952Sdf157793 #define DLH 1 /* divisor latch (msb) */ 6052Sdf157793 #define FIFOR ISR /* FIFO register for 16550 */ 6152Sdf157793 #define OUTB(offset, value) ddi_put8(asy->asy_handle, \ 6252Sdf157793 asy->asy_ioaddr+offset, value) 6352Sdf157793 #define INB(offset) ddi_get8(asy->asy_handle, asy->asy_ioaddr+offset) 6452Sdf157793 6552Sdf157793 /* 6652Sdf157793 * INTEL 8210-A/B & 16450/16550 Registers Structure. 6752Sdf157793 */ 6852Sdf157793 6952Sdf157793 /* Line Control Register */ 7052Sdf157793 #define WLS0 0x01 /* word length select bit 0 */ 7152Sdf157793 #define WLS1 0x02 /* word length select bit 2 */ 7252Sdf157793 #define STB 0x04 /* number of stop bits */ 7352Sdf157793 #define PEN 0x08 /* parity enable */ 7452Sdf157793 #define EPS 0x10 /* even parity select */ 7552Sdf157793 #define SETBREAK 0x40 /* break key */ 7652Sdf157793 #define DLAB 0x80 /* divisor latch access bit */ 7752Sdf157793 #define RXLEN 0x03 /* # of data bits per received/xmitted char */ 7852Sdf157793 #define STOP1 0x00 7952Sdf157793 #define STOP2 0x04 8052Sdf157793 #define PAREN 0x08 8152Sdf157793 #define PAREVN 0x10 8252Sdf157793 #define PARMARK 0x20 8352Sdf157793 #define SNDBRK 0x40 8452Sdf157793 8552Sdf157793 8652Sdf157793 #define BITS5 0x00 /* 5 bits per char */ 8752Sdf157793 #define BITS6 0x01 /* 6 bits per char */ 8852Sdf157793 #define BITS7 0x02 /* 7 bits per char */ 8952Sdf157793 #define BITS8 0x03 /* 8 bits per char */ 9052Sdf157793 9152Sdf157793 /* baud rate definitions */ 9252Sdf157793 #define ASY110 1047 /* 110 baud rate for serial console */ 9352Sdf157793 #define ASY150 768 /* 150 baud rate for serial console */ 9452Sdf157793 #define ASY300 384 /* 300 baud rate for serial console */ 9552Sdf157793 #define ASY600 192 /* 600 baud rate for serial console */ 9652Sdf157793 #define ASY1200 96 /* 1200 baud rate for serial console */ 9752Sdf157793 #define ASY2400 48 /* 2400 baud rate for serial console */ 9852Sdf157793 #define ASY4800 24 /* 4800 baud rate for serial console */ 9952Sdf157793 #define ASY9600 12 /* 9600 baud rate for serial console */ 10052Sdf157793 10152Sdf157793 /* Line Status Register */ 10252Sdf157793 #define RCA 0x01 /* data ready */ 10352Sdf157793 #define OVRRUN 0x02 /* overrun error */ 10452Sdf157793 #define PARERR 0x04 /* parity error */ 10552Sdf157793 #define FRMERR 0x08 /* framing error */ 10652Sdf157793 #define BRKDET 0x10 /* a break has arrived */ 10752Sdf157793 #define XHRE 0x20 /* tx hold reg is now empty */ 10852Sdf157793 #define XSRE 0x40 /* tx shift reg is now empty */ 10952Sdf157793 #define RFBE 0x80 /* rx FIFO Buffer error */ 11052Sdf157793 11152Sdf157793 /* Interrupt Id Regisger */ 11252Sdf157793 #define MSTATUS 0x00 /* modem status changed */ 11352Sdf157793 #define NOINTERRUPT 0x01 /* no interrupt pending */ 11452Sdf157793 #define TxRDY 0x02 /* Transmitter Holding Register Empty */ 11552Sdf157793 #define RxRDY 0x04 /* Receiver Data Available */ 11652Sdf157793 #define FFTMOUT 0x0c /* FIFO timeout - 16550AF */ 11752Sdf157793 #define RSTATUS 0x06 /* Receiver Line Status */ 11852Sdf157793 11952Sdf157793 /* Interrupt Enable Register */ 12052Sdf157793 #define RIEN 0x01 /* Received Data Ready */ 12152Sdf157793 #define TIEN 0x02 /* Tx Hold Register Empty */ 12252Sdf157793 #define SIEN 0x04 /* Receiver Line Status */ 12352Sdf157793 #define MIEN 0x08 /* Modem Status */ 12452Sdf157793 12552Sdf157793 /* Modem Control Register */ 12652Sdf157793 #define DTR 0x01 /* Data Terminal Ready */ 12752Sdf157793 #define RTS 0x02 /* Request To Send */ 12852Sdf157793 #define OUT1 0x04 /* Aux output - not used */ 12952Sdf157793 #define OUT2 0x08 /* dis/enable int per INO on ALI1535D+ */ 13052Sdf157793 #define ASY_LOOP 0x10 /* loopback for diagnostics */ 13152Sdf157793 13252Sdf157793 /* Modem Status Register */ 13352Sdf157793 #define DCTS 0x01 /* Delta Clear To Send */ 13452Sdf157793 #define DDSR 0x02 /* Delta Data Set Ready */ 13552Sdf157793 #define DRI 0x04 /* Trail Edge Ring Indicator */ 13652Sdf157793 #define DDCD 0x08 /* Delta Data Carrier Detect */ 13752Sdf157793 #define CTS 0x10 /* Clear To Send */ 13852Sdf157793 #define DSR 0x20 /* Data Set Ready */ 13952Sdf157793 #define RI 0x40 /* Ring Indicator */ 14052Sdf157793 #define DCD 0x80 /* Data Carrier Detect */ 14152Sdf157793 14252Sdf157793 #define DELTAS(x) ((x)&(DCTS|DDSR|DRI|DDCD)) 14352Sdf157793 #define STATES(x) ((x)(CTS|DSR|RI|DCD)) 14452Sdf157793 14552Sdf157793 /* flags for FCR (FIFO Control register) */ 14652Sdf157793 #define FIFO_OFF 0x00 /* fifo disabled */ 14752Sdf157793 #define FIFO_ON 0x01 /* fifo enabled */ 14852Sdf157793 #define FIFOEN 0x8f /* fifo enabled, w/ 8 byte trigger */ 14952Sdf157793 #define FIFORCLR 0x8b /* Clear receiver FIFO only */ 15052Sdf157793 15152Sdf157793 #define FIFORXFLSH 0x02 /* flush receiver FIFO */ 15252Sdf157793 #define FIFOTXFLSH 0x04 /* flush transmitter FIFO */ 15352Sdf157793 #define FIFODMA 0x08 /* DMA mode 1 */ 15452Sdf157793 #define FIFO_TRIG_1 0x00 /* 1 byte trigger level */ 15552Sdf157793 #define FIFO_TRIG_4 0x40 /* 4 byte trigger level */ 15652Sdf157793 #define FIFO_TRIG_8 0x80 /* 8 byte trigger level */ 15752Sdf157793 #define FIFO_TRIG_14 0xC0 /* 14 byte trigger level */ 15852Sdf157793 15952Sdf157793 /* 16052Sdf157793 * Defines for ioctl calls (VP/ix) 16152Sdf157793 */ 16252Sdf157793 16352Sdf157793 #define AIOC ('A'<<8) 16452Sdf157793 #define AIOCINTTYPE (AIOC|60) /* set interrupt type */ 16552Sdf157793 #define AIOCDOSMODE (AIOC|61) /* set DOS mode */ 16652Sdf157793 #define AIOCNONDOSMODE (AIOC|62) /* reset DOS mode */ 16752Sdf157793 #define AIOCSERIALOUT (AIOC|63) /* serial device data write */ 16852Sdf157793 #define AIOCSERIALIN (AIOC|64) /* serial device data read */ 16952Sdf157793 #define AIOCSETSS (AIOC|65) /* set start/stop chars */ 17052Sdf157793 #define AIOCINFO (AIOC|66) /* tell usr what device we are */ 17152Sdf157793 17252Sdf157793 /* Ioctl alternate names used by VP/ix */ 17352Sdf157793 #define VPC_SERIAL_DOS AIOCDOSMODE 17452Sdf157793 #define VPC_SERIAL_NONDOS AIOCNONDOSMODE 17552Sdf157793 #define VPC_SERIAL_INFO AIOCINFO 17652Sdf157793 #define VPC_SERIAL_OUT AIOCSERIALOUT 17752Sdf157793 #define VPC_SERIAL_IN AIOCSERIALIN 17852Sdf157793 17952Sdf157793 /* Serial in/out requests */ 18052Sdf157793 #define SO_DIVLLSB 1 18152Sdf157793 #define SO_DIVLMSB 2 18252Sdf157793 #define SO_LCR 3 18352Sdf157793 #define SO_MCR 4 18452Sdf157793 #define SI_MSR 1 18552Sdf157793 #define SIO_MASK(elem) (1<<((elem)-1)) 18652Sdf157793 18752Sdf157793 #define OVERRUN 040000 18852Sdf157793 #define FRERROR 020000 18952Sdf157793 #define PERROR 010000 19052Sdf157793 #define S_ERRORS (PERROR|OVERRUN|FRERROR) 19152Sdf157793 19252Sdf157793 /* 19352Sdf157793 * Ring buffer and async line management definitions. 19452Sdf157793 */ 19552Sdf157793 #define RINGBITS 16 /* # of bits in ring ptrs */ 19652Sdf157793 #define RINGSIZE (1<<RINGBITS) /* size of ring */ 19752Sdf157793 #define RINGMASK (RINGSIZE-1) 19852Sdf157793 #define RINGFRAC 12 /* fraction of ring to force flush */ 19952Sdf157793 20052Sdf157793 #define RING_INIT(ap) ((ap)->async_rput = (ap)->async_rget = 0) 20152Sdf157793 #define RING_CNT(ap) (((ap)->async_rput - (ap)->async_rget) & RINGMASK) 20252Sdf157793 #define RING_FRAC(ap) ((int)RING_CNT(ap) >= (int)(RINGSIZE/RINGFRAC)) 20352Sdf157793 #define RING_POK(ap, n) ((int)RING_CNT(ap) < (int)(RINGSIZE-(n))) 20452Sdf157793 #define RING_PUT(ap, c) \ 20552Sdf157793 ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = (uchar_t)(c)) 20652Sdf157793 #define RING_UNPUT(ap) ((ap)->async_rput--) 20752Sdf157793 #define RING_GOK(ap, n) ((int)RING_CNT(ap) >= (int)(n)) 20852Sdf157793 #define RING_GET(ap) ((ap)->async_ring[(ap)->async_rget++ & RINGMASK]) 20952Sdf157793 #define RING_EAT(ap, n) ((ap)->async_rget += (n)) 21052Sdf157793 #define RING_MARK(ap, c, s) \ 21152Sdf157793 ((ap)->async_ring[(ap)->async_rput++ & RINGMASK] = ((uchar_t)(c)|(s))) 21252Sdf157793 #define RING_UNMARK(ap) \ 21352Sdf157793 ((ap)->async_ring[((ap)->async_rget) & RINGMASK] &= ~S_ERRORS) 21452Sdf157793 #define RING_ERR(ap, c) \ 21552Sdf157793 ((ap)->async_ring[((ap)->async_rget) & RINGMASK] & (c)) 21652Sdf157793 21752Sdf157793 /* 21852Sdf157793 * Serial kstats structure and macro to increment an individual kstat 21952Sdf157793 */ 22052Sdf157793 struct serial_kstats { 22152Sdf157793 kstat_named_t ringover; /* ring buffer overflow */ 22252Sdf157793 kstat_named_t siloover; /* silo overflow */ 22352Sdf157793 }; 22452Sdf157793 22552Sdf157793 #define INC64_KSTAT(asy, stat) (asy)->kstats.stat.value.ui64++; 22652Sdf157793 22752Sdf157793 /* 22852Sdf157793 * Hardware channel common data. One structure per port. 22952Sdf157793 * Each of the fields in this structure is required to be protected by a 23052Sdf157793 * mutex lock at the highest priority at which it can be altered. 23152Sdf157793 * The asy_flags, and asy_next fields can be altered by interrupt 23252Sdf157793 * handling code that must be protected by the mutex whose handle is 23352Sdf157793 * stored in asy_excl_hi. All others can be protected by the asy_excl 23452Sdf157793 * mutex, which is lower priority and adaptive. 23552Sdf157793 */ 23652Sdf157793 struct asycom { 23752Sdf157793 int asy_flags; /* random flags */ 23852Sdf157793 /* protected by asy_excl_hi lock */ 23952Sdf157793 uint_t asy_hwtype; /* HW type: ASY82510, etc. */ 24052Sdf157793 uint_t asy_use_fifo; /* HW FIFO use it or not ?? */ 24152Sdf157793 uint_t asy_fifo_buf; /* With FIFO = 16, otherwise = 1 */ 24252Sdf157793 uchar_t *asy_ioaddr; /* i/o address of ASY port */ 24352Sdf157793 uint_t asy_vect; /* IRQ number */ 24452Sdf157793 boolean_t suspended; /* TRUE if driver suspended */ 24552Sdf157793 caddr_t asy_priv; /* protocol private data */ 24652Sdf157793 dev_info_t *asy_dip; /* dev_info */ 24752Sdf157793 long asy_unit; /* which port */ 24852Sdf157793 ddi_iblock_cookie_t asy_iblock; 24952Sdf157793 kmutex_t *asy_excl; /* asy adaptive mutex */ 25052Sdf157793 kmutex_t *asy_excl_hi; /* asy spinlock mutex */ 25152Sdf157793 ddi_acc_handle_t asy_handle; /* ddi_get/put handle */ 25252Sdf157793 ushort_t asy_rsc_console; /* RSC console port */ 25352Sdf157793 ushort_t asy_rsc_control; /* RSC control port */ 25452Sdf157793 ushort_t asy_lom_console; /* LOM console port */ 25552Sdf157793 uint_t asy_xmit_count; /* Count the no of xmits in one intr */ 25652Sdf157793 uint_t asy_out_of_band_xmit; /* Out of band xmission */ 25752Sdf157793 uint_t asy_rx_count; /* No. of bytes rx'eved in one intr */ 25852Sdf157793 uchar_t asy_device_type; /* Currently used for this device */ 25952Sdf157793 uchar_t asy_trig_level; /* Receive FIFO trig level */ 26052Sdf157793 kmutex_t *asy_soft_lock; /* soft lock for gaurding softpend. */ 26152Sdf157793 int asysoftpend; /* Flag indicating soft int pending. */ 26252Sdf157793 ddi_softintr_t asy_softintr_id; 26352Sdf157793 ddi_iblock_cookie_t asy_soft_iblock; 26452Sdf157793 int asy_baud_divisor_factor; /* for different chips */ 26552Sdf157793 int asy_ocflags; /* old cflags used in asy_program() */ 26652Sdf157793 uint_t asy_cached_msr; /* a cache for the MSR register */ 26752Sdf157793 int asy_speed_cap; /* maximum baud rate */ 26852Sdf157793 kstat_t *sukstat; /* ptr to serial kstats */ 26952Sdf157793 struct serial_kstats kstats; /* serial kstats structure */ 27052Sdf157793 boolean_t inperim; /* in streams q perimeter */ 271*5973Szk194757 cons_polledio_t polledio; /* polled IO functios */ 272*5973Szk194757 uchar_t polled_icr; /* the value of ICR on start of poll */ 273*5973Szk194757 boolean_t polled_enter; /* if asy_polled_enter was called */ 27452Sdf157793 }; 27552Sdf157793 27652Sdf157793 /* 27752Sdf157793 * Asychronous protocol private data structure for ASY. 27852Sdf157793 * Each of the fields in the structure is required to be protected by 27952Sdf157793 * the lower priority lock except the fields that are set only at 28052Sdf157793 * base level but cleared (with out lock) at interrupt level. 28152Sdf157793 */ 28252Sdf157793 struct asyncline { 28352Sdf157793 int async_flags; /* random flags */ 28452Sdf157793 kcondvar_t async_flags_cv; /* condition variable for flags */ 28552Sdf157793 dev_t async_dev; /* device major/minor numbers */ 28652Sdf157793 mblk_t *async_xmitblk; /* transmit: active msg block */ 28752Sdf157793 struct asycom *async_common; /* device common data */ 28852Sdf157793 tty_common_t async_ttycommon; /* tty driver common data */ 28952Sdf157793 bufcall_id_t async_wbufcid; /* id for pending write-side bufcall */ 29052Sdf157793 timeout_id_t async_polltid; /* softint poll timeout id */ 29152Sdf157793 29252Sdf157793 /* 29352Sdf157793 * The following fields are protected by the asy_excl_hi lock. 29452Sdf157793 * Some, such as async_flowc, are set only at the base level and 29552Sdf157793 * cleared (without the lock) only by the interrupt level. 29652Sdf157793 */ 29752Sdf157793 uchar_t *async_optr; /* output pointer */ 29852Sdf157793 int async_ocnt; /* output count */ 29952Sdf157793 uint_t async_rput; /* producing pointer for input */ 30052Sdf157793 uint_t async_rget; /* consuming pointer for input */ 30152Sdf157793 uchar_t async_flowc; /* flow control char to send */ 30252Sdf157793 30352Sdf157793 /* 30452Sdf157793 * Each character stuffed into the ring has two bytes associated 30552Sdf157793 * with it. The first byte is used to indicate special conditions 30652Sdf157793 * and the second byte is the actual data. The ring buffer 30752Sdf157793 * needs to be defined as ushort_t to accomodate this. 30852Sdf157793 */ 30952Sdf157793 ushort_t async_ring[RINGSIZE]; 31052Sdf157793 31152Sdf157793 short async_break; /* break count */ 31252Sdf157793 31352Sdf157793 union { 31452Sdf157793 struct { 31552Sdf157793 uchar_t _hw; /* overrun (hw) */ 31652Sdf157793 uchar_t _sw; /* overrun (sw) */ 31752Sdf157793 } _a; 31852Sdf157793 ushort_t uover_overrun; 31952Sdf157793 } async_uover; 32052Sdf157793 #define async_overrun async_uover._a.uover_overrun 32152Sdf157793 #define async_hw_overrun async_uover._a._hw 32252Sdf157793 #define async_sw_overrun async_uover._a._sw 32352Sdf157793 short async_ext; /* modem status change count */ 32452Sdf157793 short async_work; /* work to do flag */ 32552Sdf157793 uchar_t async_queue_full; /* Streams Queue Full */ 32652Sdf157793 uchar_t async_ringbuf_overflow; /* when ring buffer overflows */ 32752Sdf157793 timeout_id_t async_timer; /* close drain progress timer */ 32852Sdf157793 }; 32952Sdf157793 33052Sdf157793 /* definitions for async_flags field */ 33152Sdf157793 #define ASYNC_EXCL_OPEN 0x10000000 /* exclusive open */ 33252Sdf157793 #define ASYNC_WOPEN 0x00000001 /* waiting for open to complete */ 33352Sdf157793 #define ASYNC_ISOPEN 0x00000002 /* open is complete */ 33452Sdf157793 #define ASYNC_OUT 0x00000004 /* line being used for dialout */ 33552Sdf157793 #define ASYNC_CARR_ON 0x00000008 /* carrier on last time we looked */ 33652Sdf157793 #define ASYNC_STOPPED 0x00000010 /* output is stopped */ 33752Sdf157793 #define ASYNC_DELAY 0x00000020 /* waiting for delay to finish */ 33852Sdf157793 #define ASYNC_BREAK 0x00000040 /* waiting for break to finish */ 33952Sdf157793 #define ASYNC_BUSY 0x00000080 /* waiting for transmission to finish */ 34052Sdf157793 #define ASYNC_DRAINING 0x00000100 /* waiting for output to drain */ 34152Sdf157793 #define ASYNC_SERVICEIMM 0x00000200 /* queue soft interrupt as soon as */ 34252Sdf157793 #define ASYNC_HW_IN_FLOW 0x00000400 /* input flow control in effect */ 34352Sdf157793 #define ASYNC_HW_OUT_FLW 0x00000800 /* output flow control in effect */ 34452Sdf157793 #define ASYNC_PROGRESS 0x00001000 /* made progress on output effort */ 34552Sdf157793 #define ASYNC_CLOSING 0x00002000 /* closing the stream */ 34652Sdf157793 34752Sdf157793 /* asy_hwtype definitions */ 34852Sdf157793 #define ASY82510 0x1 34952Sdf157793 #define ASY16550AF 0x2 35052Sdf157793 #define ASY8250 0x3 /* 8250 or 16450 or 16550 */ 3512877Sanovick #define ASY16C554D 0x4 /* ST16C554D */ 35252Sdf157793 35352Sdf157793 /* definitions for asy_flags field */ 35452Sdf157793 #define ASY_NEEDSOFT 0x00000001 35552Sdf157793 #define ASY_DOINGSOFT 0x00000002 35652Sdf157793 #define ASY_PPS 0x00000004 35752Sdf157793 #define ASY_PPS_EDGE 0x00000008 35852Sdf157793 #define ASY_IGNORE_CD 0x00000040 35952Sdf157793 36052Sdf157793 /* 36152Sdf157793 * Different devices this driver supports and what it is used to drive 36252Sdf157793 * currently 36352Sdf157793 */ 36452Sdf157793 #define ASY_KEYBOARD 0x01 36552Sdf157793 #define ASY_MOUSE 0x02 36652Sdf157793 #define ASY_SERIAL 0x03 36752Sdf157793 36852Sdf157793 /* 36952Sdf157793 * RSC_DEVICE defines the bit in the minor device number that specifies 37052Sdf157793 * the tty line is to be used for console/controlling a RSC device. 37152Sdf157793 */ 37252Sdf157793 #define RSC_DEVICE (1 << (NBITSMINOR32 - 4)) 37352Sdf157793 37452Sdf157793 /* 37552Sdf157793 * OUTLINE defines the high-order flag bit in the minor device number that 37652Sdf157793 * controls use of a tty line for dialin and dialout simultaneously. 37752Sdf157793 */ 37852Sdf157793 #define OUTLINE (1 << (NBITSMINOR32 - 1)) 37952Sdf157793 #define UNIT(x) (getminor(x) & ~(OUTLINE | RSC_DEVICE)) 38052Sdf157793 38152Sdf157793 /* suggested number of soft state instances */ 38252Sdf157793 #define SU_INITIAL_SOFT_ITEMS 0x02 38352Sdf157793 38452Sdf157793 /* 38552Sdf157793 * ASYSETSOFT macro to pend a soft interrupt if one isn't already pending. 38652Sdf157793 */ 38752Sdf157793 38852Sdf157793 #define ASYSETSOFT(asy) { \ 38952Sdf157793 if (mutex_tryenter(asy->asy_soft_lock)) { \ 39052Sdf157793 asy->asy_flags |= ASY_NEEDSOFT; \ 39152Sdf157793 if (!asy->asysoftpend) { \ 39252Sdf157793 asy->asysoftpend = 1; \ 39352Sdf157793 mutex_exit(asy->asy_soft_lock);\ 39452Sdf157793 ddi_trigger_softintr(asy->asy_softintr_id);\ 39552Sdf157793 } else \ 39652Sdf157793 mutex_exit(asy->asy_soft_lock);\ 39752Sdf157793 } \ 39852Sdf157793 } 39952Sdf157793 40052Sdf157793 #ifdef __cplusplus 40152Sdf157793 } 40252Sdf157793 #endif 40352Sdf157793 40452Sdf157793 #endif /* _SYS_SUDEV_H */ 405