1*1709Smlf /* 2*1709Smlf * CDDL HEADER START 3*1709Smlf * 4*1709Smlf * The contents of this file are subject to the terms of the 5*1709Smlf * Common Development and Distribution License (the "License"). 6*1709Smlf * You may not use this file except in compliance with the License. 7*1709Smlf * 8*1709Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*1709Smlf * or http://www.opensolaris.org/os/licensing. 10*1709Smlf * See the License for the specific language governing permissions 11*1709Smlf * and limitations under the License. 12*1709Smlf * 13*1709Smlf * When distributing Covered Code, include this CDDL HEADER in each 14*1709Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*1709Smlf * If applicable, add the following below this CDDL HEADER, with the 16*1709Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17*1709Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18*1709Smlf * 19*1709Smlf * CDDL HEADER END 20*1709Smlf */ 21*1709Smlf 22*1709Smlf /* 23*1709Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*1709Smlf * Use is subject to license terms. 25*1709Smlf */ 26*1709Smlf 27*1709Smlf #ifndef _PCIIDE_H 28*1709Smlf #define _PCIIDE_H 29*1709Smlf 30*1709Smlf #pragma ident "%Z%%M% %I% %E% SMI" 31*1709Smlf 32*1709Smlf #ifdef __cplusplus 33*1709Smlf extern "C" { 34*1709Smlf #endif 35*1709Smlf 36*1709Smlf 37*1709Smlf /* 38*1709Smlf * Bus Mastering devices have a PCI class-code of 0x010180 to 0x0101ff 39*1709Smlf */ 40*1709Smlf #define PCIIDE_BM_CAP_MASK 0x80 41*1709Smlf #define PCIIDE_BM_CLASS ((PCI_CLASS_MASS << 16) | (PCI_MASS_IDE << 8) | 0x80) 42*1709Smlf #define PCIIDE_BM_CLASS_MASK 0xffffff80 43*1709Smlf 44*1709Smlf 45*1709Smlf #define PCIIDE_BMICX_REG 0 /* Bus Master IDE Command Register */ 46*1709Smlf 47*1709Smlf #define PCIIDE_BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 48*1709Smlf #define PCIIDE_BMICX_SSBM_E 0x01 /* 1=Start (Enable) */ 49*1709Smlf /* 0=Start (Disable) */ 50*1709Smlf 51*1709Smlf /* 52*1709Smlf * NOTE: "read" and "write" are the actions of the DMA 53*1709Smlf * engine on the PCI bus. Not the DMA engine's action on the ATA 54*1709Smlf * BUS. Therefore for a ATA READ command, program the DMA engine to 55*1709Smlf * "write to memory" mode (and vice versa). 56*1709Smlf */ 57*1709Smlf #define PCIIDE_BMICX_RWCON 0x08 /* Read/Write Control */ 58*1709Smlf #define PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 59*1709Smlf #define PCIIDE_BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 60*1709Smlf 61*1709Smlf /* preserve these bits during updates */ 62*1709Smlf #define PCIIDE_BMICX_MASK (~(PCIIDE_BMICX_SSBM | PCIIDE_BMICX_RWCON)) 63*1709Smlf 64*1709Smlf 65*1709Smlf 66*1709Smlf #define PCIIDE_BMISX_REG 2 /* Bus Master IDE Status Register */ 67*1709Smlf 68*1709Smlf #define PCIIDE_BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 69*1709Smlf #define PCIIDE_BMISX_IDERR 0x02 /* IDE DMA Error */ 70*1709Smlf #define PCIIDE_BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 71*1709Smlf #define PCIIDE_BMISX_DMA0CAP 0x20 /* Drive 0 DMA Capable */ 72*1709Smlf #define PCIIDE_BMISX_DMA1CAP 0x40 /* Drive 1 DMA Capable */ 73*1709Smlf #define PCIIDE_BMISX_SIMPLEX 0x80 /* Simplex only */ 74*1709Smlf 75*1709Smlf /* preserve these bits during updates */ 76*1709Smlf #define PCIIDE_BMISX_MASK 0xf8 77*1709Smlf 78*1709Smlf #define PCIIDE_BMIDTPX_REG 4 /* Bus Master IDE Desc. Table Ptr */ 79*1709Smlf #define PCIIDE_BMIDTPX_MASK 0x00000003 /* must be zeros */ 80*1709Smlf 81*1709Smlf 82*1709Smlf typedef struct PhysicalRegionDescriptorTableEntry { 83*1709Smlf uint_t p_address; /* physical address */ 84*1709Smlf uint_t p_count; /* byte count, EOT in high order bit */ 85*1709Smlf } prde_t; 86*1709Smlf 87*1709Smlf /* 88*1709Smlf * Some specs say the p_address must 32-bit aligned, and some claim 89*1709Smlf * 16-bit alignment. Use 32-bit alignment just to be safe. 90*1709Smlf */ 91*1709Smlf #ifdef __not_yet__ 92*1709Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (short) -1)) 93*1709Smlf #else 94*1709Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (int) -1)) 95*1709Smlf #endif 96*1709Smlf 97*1709Smlf #define PCIIDE_PRDE_CNT_MASK ((uint_t)0x0001) /* must be even */ 98*1709Smlf #define PCIIDE_PRDE_CNT_MAX ((uint_t)0x10000) /* 0 == 64k */ 99*1709Smlf #define PCIIDE_PRDE_EOT ((uint_t)0x80000000) 100*1709Smlf 101*1709Smlf #ifdef __cplusplus 102*1709Smlf } 103*1709Smlf #endif 104*1709Smlf 105*1709Smlf #endif /* _PCIIDE_H */ 106