1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 23*0Sstevel@tonic-gate /* All Rights Reserved */ 24*0Sstevel@tonic-gate 25*0Sstevel@tonic-gate 26*0Sstevel@tonic-gate #ifndef _SYS_TERMIOX_H 27*0Sstevel@tonic-gate #define _SYS_TERMIOX_H 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" /* SVr4.0 1.4 */ 30*0Sstevel@tonic-gate 31*0Sstevel@tonic-gate #ifdef __cplusplus 32*0Sstevel@tonic-gate extern "C" { 33*0Sstevel@tonic-gate #endif 34*0Sstevel@tonic-gate 35*0Sstevel@tonic-gate /* This structure provides an extended terminal interface. */ 36*0Sstevel@tonic-gate /* Features of this interface are optional and may not be */ 37*0Sstevel@tonic-gate /* implemented on all machines. */ 38*0Sstevel@tonic-gate 39*0Sstevel@tonic-gate 40*0Sstevel@tonic-gate #define NFF 5 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate /* hardware flow control modes */ 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate #define RTSXOFF 0000001 /* Enable RTS hardware flow control on input */ 45*0Sstevel@tonic-gate #define CTSXON 0000002 /* Enable CTS hardware flow control on output */ 46*0Sstevel@tonic-gate #define DTRXOFF 0000004 /* Enable DTR hardware flow control on input */ 47*0Sstevel@tonic-gate #define CDXON 0000010 /* Enable CD hardware flow control on output */ 48*0Sstevel@tonic-gate #define ISXOFF 0000020 /* Enable isochronous hardware flow control on input */ 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate /* clock modes */ 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate #define XMTCLK 0000007 /* Transmit Clock Source: */ 53*0Sstevel@tonic-gate #define XCIBRG 0000000 /* Get transmit clock from */ 54*0Sstevel@tonic-gate /* internal baud rate generator */ 55*0Sstevel@tonic-gate #define XCTSET 0000001 /* Get transmit clock from */ 56*0Sstevel@tonic-gate /* transmitter signal element */ 57*0Sstevel@tonic-gate /* timing (DCE source) lead, */ 58*0Sstevel@tonic-gate /* CCITT V.24 circuit 114, */ 59*0Sstevel@tonic-gate /* EIA-232-D pin 15 */ 60*0Sstevel@tonic-gate #define XCRSET 0000002 /* Get transmit clock from */ 61*0Sstevel@tonic-gate /* receiver signal element */ 62*0Sstevel@tonic-gate /* timing (DCE source) lead, */ 63*0Sstevel@tonic-gate /* CCITT V.24 circuit 115, */ 64*0Sstevel@tonic-gate /* EIA-232-D pin 17 */ 65*0Sstevel@tonic-gate 66*0Sstevel@tonic-gate #define RCVCLK 0000070 /* Receive Clock Source: */ 67*0Sstevel@tonic-gate #define RCIBRG 0000000 /* get receive clock from internal */ 68*0Sstevel@tonic-gate /* baud rate generator */ 69*0Sstevel@tonic-gate #define RCTSET 0000010 /* Get receive clock from */ 70*0Sstevel@tonic-gate /* transmitter signal element */ 71*0Sstevel@tonic-gate /* timing (DCE source) lead, */ 72*0Sstevel@tonic-gate /* CCITT V.24 circuit 114, */ 73*0Sstevel@tonic-gate /* EIA-232-D pin 15 */ 74*0Sstevel@tonic-gate #define RCRSET 0000020 /* Get receive clock from */ 75*0Sstevel@tonic-gate /* receiver signal element */ 76*0Sstevel@tonic-gate /* timing (DCE source) lead, */ 77*0Sstevel@tonic-gate /* CCITT V.24 circuit 115, */ 78*0Sstevel@tonic-gate /* EIA-232-D pin 17 */ 79*0Sstevel@tonic-gate 80*0Sstevel@tonic-gate #define TSETCLK 0000700 /* Transmitter Signal Element */ 81*0Sstevel@tonic-gate /* timing (DTE source) lead, */ 82*0Sstevel@tonic-gate /* CCITT V.24 circuit 113, */ 83*0Sstevel@tonic-gate /* EIA-232-D pin 24, clock source: */ 84*0Sstevel@tonic-gate #define TSETCOFF 0000000 /* TSET clock not provided */ 85*0Sstevel@tonic-gate #define TSETCRBRG 0000100 /* Output receive baud rate generator */ 86*0Sstevel@tonic-gate /* on circuit 113 */ 87*0Sstevel@tonic-gate #define TSETCTBRG 0000200 /* Output transmit baud rate generator */ 88*0Sstevel@tonic-gate /* on circuit 113 */ 89*0Sstevel@tonic-gate #define TSETCTSET 0000300 /* Output transmitter signal element */ 90*0Sstevel@tonic-gate /* timing (DCE source) on circuit 113 */ 91*0Sstevel@tonic-gate #define TSETCRSET 0000400 /* Output receiver signal element */ 92*0Sstevel@tonic-gate /* timing (DCE source) on circuit 113 */ 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate #define RSETCLK 0007000 /* Receiver Signal Element */ 95*0Sstevel@tonic-gate /* timing (DTE source) lead, */ 96*0Sstevel@tonic-gate /* CCITT V.24 circuit 128, */ 97*0Sstevel@tonic-gate /* no EIA-232-D pin, clock source: */ 98*0Sstevel@tonic-gate #define RSETCOFF 0000000 /* RSET clock not provided */ 99*0Sstevel@tonic-gate #define RSETCRBRG 0001000 /* Output receive baud rate generator */ 100*0Sstevel@tonic-gate /* on circuit 128 */ 101*0Sstevel@tonic-gate #define RSETCTBRG 0002000 /* Output transmit baud rate generator */ 102*0Sstevel@tonic-gate /* on circuit 128 */ 103*0Sstevel@tonic-gate #define RSETCTSET 0003000 /* Output transmitter signal element */ 104*0Sstevel@tonic-gate /* timing (DCE source) on circuit 128 */ 105*0Sstevel@tonic-gate #define RSETCRSET 0004000 /* Output receiver signal element */ 106*0Sstevel@tonic-gate /* timing (DCE source) on circuit 128 */ 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate struct termiox { 110*0Sstevel@tonic-gate unsigned short x_hflag; /* hardware flow control modes */ 111*0Sstevel@tonic-gate unsigned short x_cflag; /* clock modes */ 112*0Sstevel@tonic-gate unsigned short x_rflag[NFF]; /* reserved modes */ 113*0Sstevel@tonic-gate unsigned short x_sflag; /* spare modes */ 114*0Sstevel@tonic-gate }; 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate #define XIOC ('X'<<8) 117*0Sstevel@tonic-gate #define TCGETX (XIOC|1) 118*0Sstevel@tonic-gate #define TCSETX (XIOC|2) 119*0Sstevel@tonic-gate #define TCSETXW (XIOC|3) 120*0Sstevel@tonic-gate #define TCSETXF (XIOC|4) 121*0Sstevel@tonic-gate 122*0Sstevel@tonic-gate #ifdef __cplusplus 123*0Sstevel@tonic-gate } 124*0Sstevel@tonic-gate #endif 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate #endif /* _SYS_TERMIOX_H */ 127