18275SEric Cheng /* 28275SEric Cheng * CDDL HEADER START 38275SEric Cheng * 48275SEric Cheng * The contents of this file are subject to the terms of the 58275SEric Cheng * Common Development and Distribution License (the "License"). 68275SEric Cheng * You may not use this file except in compliance with the License. 78275SEric Cheng * 88275SEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 98275SEric Cheng * or http://www.opensolaris.org/os/licensing. 108275SEric Cheng * See the License for the specific language governing permissions 118275SEric Cheng * and limitations under the License. 128275SEric Cheng * 138275SEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 148275SEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 158275SEric Cheng * If applicable, add the following below this CDDL HEADER, with the 168275SEric Cheng * fields enclosed by brackets "[]" replaced with your own identifying 178275SEric Cheng * information: Portions Copyright [yyyy] [name of copyright owner] 188275SEric Cheng * 198275SEric Cheng * CDDL HEADER END 208275SEric Cheng */ 218275SEric Cheng 228275SEric Cheng /* 23*11878SVenu.Iyer@Sun.COM * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 248275SEric Cheng * Use is subject to license terms. 258275SEric Cheng */ 268275SEric Cheng 278275SEric Cheng #ifndef _MAC_FLOW_H 288275SEric Cheng #define _MAC_FLOW_H 298275SEric Cheng 308275SEric Cheng /* 318275SEric Cheng * Main structure describing a flow of packets, for classification use 328275SEric Cheng */ 338275SEric Cheng 348275SEric Cheng #ifdef __cplusplus 358275SEric Cheng extern "C" { 368275SEric Cheng #endif 378275SEric Cheng 388275SEric Cheng #include <sys/types.h> 398275SEric Cheng #include <netinet/in.h> /* for IPPROTO_* constants */ 408275SEric Cheng #include <sys/ethernet.h> 418275SEric Cheng 42*11878SVenu.Iyer@Sun.COM #define MAX_RINGS_PER_GROUP 128 43*11878SVenu.Iyer@Sun.COM 448558SGirish.Moodalbail@Sun.COM /* 458558SGirish.Moodalbail@Sun.COM * MAXFLOWNAMELEN defines the longest possible permitted flow name, 468558SGirish.Moodalbail@Sun.COM * including the terminating NUL. 478558SGirish.Moodalbail@Sun.COM */ 488558SGirish.Moodalbail@Sun.COM #define MAXFLOWNAMELEN 128 498275SEric Cheng 508275SEric Cheng /* need to use MAXMACADDRLEN from dld.h instead of this one */ 518275SEric Cheng #define MAXMACADDR 20 528275SEric Cheng 538275SEric Cheng /* Bit-mask for the selectors carried in the flow descriptor */ 548275SEric Cheng typedef uint64_t flow_mask_t; 558275SEric Cheng 568275SEric Cheng #define FLOW_LINK_DST 0x00000001 /* Destination MAC addr */ 578275SEric Cheng #define FLOW_LINK_SRC 0x00000002 /* Source MAC address */ 588275SEric Cheng #define FLOW_LINK_VID 0x00000004 /* VLAN ID */ 598275SEric Cheng #define FLOW_LINK_SAP 0x00000008 /* SAP value */ 608275SEric Cheng 618275SEric Cheng #define FLOW_IP_VERSION 0x00000010 /* V4 or V6 */ 628275SEric Cheng #define FLOW_IP_PROTOCOL 0x00000020 /* Protocol type */ 638275SEric Cheng #define FLOW_IP_LOCAL 0x00000040 /* Local address */ 648275SEric Cheng #define FLOW_IP_REMOTE 0x00000080 /* Remote address */ 658275SEric Cheng #define FLOW_IP_DSFIELD 0x00000100 /* DSfield value */ 668275SEric Cheng 678275SEric Cheng #define FLOW_ULP_PORT_LOCAL 0x00001000 /* ULP local port */ 688275SEric Cheng #define FLOW_ULP_PORT_REMOTE 0x00002000 /* ULP remote port */ 698275SEric Cheng 708275SEric Cheng #if _LONG_LONG_ALIGNMENT == 8 && _LONG_LONG_ALIGNMENT_32 == 4 718275SEric Cheng #pragma pack(4) 728275SEric Cheng #endif 738275SEric Cheng 748275SEric Cheng typedef struct flow_desc_s { 758275SEric Cheng flow_mask_t fd_mask; 768275SEric Cheng uint32_t fd_mac_len; 778275SEric Cheng uint8_t fd_dst_mac[MAXMACADDR]; 788275SEric Cheng uint8_t fd_src_mac[MAXMACADDR]; 798275SEric Cheng uint16_t fd_vid; 808275SEric Cheng uint32_t fd_sap; 818275SEric Cheng uint8_t fd_ipversion; 828275SEric Cheng uint8_t fd_protocol; 838275SEric Cheng in6_addr_t fd_local_addr; 848275SEric Cheng in6_addr_t fd_local_netmask; 858275SEric Cheng in6_addr_t fd_remote_addr; 868275SEric Cheng in6_addr_t fd_remote_netmask; 878275SEric Cheng in_port_t fd_local_port; 888275SEric Cheng in_port_t fd_remote_port; 898275SEric Cheng uint8_t fd_dsfield; 908275SEric Cheng uint8_t fd_dsfield_mask; 918275SEric Cheng } flow_desc_t; 928275SEric Cheng 938275SEric Cheng #define MRP_NCPUS 128 948275SEric Cheng 958275SEric Cheng /* 968275SEric Cheng * In MCM_CPUS mode, cpu bindings is user specified. In MCM_FANOUT mode, 978275SEric Cheng * user only specifies a fanout count. 98*11878SVenu.Iyer@Sun.COM * mc_rx_fanout_cnt gives the number of CPUs used for fanout soft rings. 99*11878SVenu.Iyer@Sun.COM * mc_rx_fanout_cpus[] array stores the CPUs used for fanout soft rings. 1008275SEric Cheng */ 1018275SEric Cheng typedef enum { 1028275SEric Cheng MCM_FANOUT = 1, 1038275SEric Cheng MCM_CPUS 1048275SEric Cheng } mac_cpu_mode_t; 1058275SEric Cheng 106*11878SVenu.Iyer@Sun.COM /* 107*11878SVenu.Iyer@Sun.COM * Structure to store the value of the CPUs to be used to re-target 108*11878SVenu.Iyer@Sun.COM * Tx interrupt. 109*11878SVenu.Iyer@Sun.COM */ 110*11878SVenu.Iyer@Sun.COM typedef struct mac_tx_intr_cpus_s { 111*11878SVenu.Iyer@Sun.COM /* cpu value to re-target intr to */ 112*11878SVenu.Iyer@Sun.COM int32_t mtc_intr_cpu[MRP_NCPUS]; 113*11878SVenu.Iyer@Sun.COM /* re-targeted CPU or -1 if failed */ 114*11878SVenu.Iyer@Sun.COM int32_t mtc_retargeted_cpu[MRP_NCPUS]; 115*11878SVenu.Iyer@Sun.COM } mac_tx_intr_cpu_t; 116*11878SVenu.Iyer@Sun.COM 1178275SEric Cheng typedef struct mac_cpus_props_s { 1188275SEric Cheng uint32_t mc_ncpus; /* num of cpus */ 1198275SEric Cheng uint32_t mc_cpus[MRP_NCPUS]; /* cpu list */ 120*11878SVenu.Iyer@Sun.COM uint32_t mc_rx_fanout_cnt; /* soft ring cpu cnt */ 121*11878SVenu.Iyer@Sun.COM uint32_t mc_rx_fanout_cpus[MRP_NCPUS]; /* SR cpu list */ 122*11878SVenu.Iyer@Sun.COM uint32_t mc_rx_pollid; /* poll thr binding */ 123*11878SVenu.Iyer@Sun.COM uint32_t mc_rx_workerid; /* worker thr binding */ 1248275SEric Cheng /* 1258275SEric Cheng * interrupt cpu: mrp_intr_cpu less than 0 implies platform limitation 1268275SEric Cheng * in retargetting the interrupt assignment. 1278275SEric Cheng */ 128*11878SVenu.Iyer@Sun.COM int32_t mc_rx_intr_cpu; 129*11878SVenu.Iyer@Sun.COM int32_t mc_tx_fanout_cpus[MRP_NCPUS]; 130*11878SVenu.Iyer@Sun.COM mac_tx_intr_cpu_t mc_tx_intr_cpus; 13110734SEric Cheng mac_cpu_mode_t mc_fanout_mode; /* fanout mode */ 1328275SEric Cheng } mac_cpus_t; 1338275SEric Cheng 134*11878SVenu.Iyer@Sun.COM #define mc_tx_intr_cpu mc_tx_intr_cpus.mtc_intr_cpu 135*11878SVenu.Iyer@Sun.COM #define mc_tx_retargeted_cpu mc_tx_intr_cpus.mtc_retargeted_cpu 136*11878SVenu.Iyer@Sun.COM 1378275SEric Cheng /* Priority values */ 1388275SEric Cheng typedef enum { 1398275SEric Cheng MPL_LOW, 1408275SEric Cheng MPL_MEDIUM, 1418275SEric Cheng MPL_HIGH, 1428275SEric Cheng MPL_RESET 1438275SEric Cheng } mac_priority_level_t; 1448275SEric Cheng 14510734SEric Cheng /* Protection types */ 14610734SEric Cheng #define MPT_MACNOSPOOF 0x00000001 147*11878SVenu.Iyer@Sun.COM #define MPT_RESTRICTED 0x00000002 148*11878SVenu.Iyer@Sun.COM #define MPT_IPNOSPOOF 0x00000004 149*11878SVenu.Iyer@Sun.COM #define MPT_DHCPNOSPOOF 0x00000008 150*11878SVenu.Iyer@Sun.COM #define MPT_ALL 0x0000000f 15110734SEric Cheng #define MPT_RESET 0xffffffff 152*11878SVenu.Iyer@Sun.COM #define MPT_MAXCNT 32 153*11878SVenu.Iyer@Sun.COM #define MPT_MAXIPADDR MPT_MAXCNT 154*11878SVenu.Iyer@Sun.COM #define MPT_MAXCID MPT_MAXCNT 155*11878SVenu.Iyer@Sun.COM #define MPT_MAXCIDLEN 256 156*11878SVenu.Iyer@Sun.COM 157*11878SVenu.Iyer@Sun.COM typedef struct mac_ipaddr_s { 158*11878SVenu.Iyer@Sun.COM uint32_t ip_version; 159*11878SVenu.Iyer@Sun.COM in6_addr_t ip_addr; 160*11878SVenu.Iyer@Sun.COM } mac_ipaddr_t; 161*11878SVenu.Iyer@Sun.COM 162*11878SVenu.Iyer@Sun.COM typedef enum { 163*11878SVenu.Iyer@Sun.COM CIDFORM_TYPED = 1, 164*11878SVenu.Iyer@Sun.COM CIDFORM_HEX, 165*11878SVenu.Iyer@Sun.COM CIDFORM_STR 166*11878SVenu.Iyer@Sun.COM } mac_dhcpcid_form_t; 167*11878SVenu.Iyer@Sun.COM 168*11878SVenu.Iyer@Sun.COM typedef struct mac_dhcpcid_s { 169*11878SVenu.Iyer@Sun.COM uchar_t dc_id[MPT_MAXCIDLEN]; 170*11878SVenu.Iyer@Sun.COM uint32_t dc_len; 171*11878SVenu.Iyer@Sun.COM mac_dhcpcid_form_t dc_form; 172*11878SVenu.Iyer@Sun.COM } mac_dhcpcid_t; 17310734SEric Cheng 17410734SEric Cheng typedef struct mac_protect_s { 17510734SEric Cheng uint32_t mp_types; 17610734SEric Cheng uint32_t mp_ipaddrcnt; 177*11878SVenu.Iyer@Sun.COM mac_ipaddr_t mp_ipaddrs[MPT_MAXIPADDR]; 178*11878SVenu.Iyer@Sun.COM uint32_t mp_cidcnt; 179*11878SVenu.Iyer@Sun.COM mac_dhcpcid_t mp_cids[MPT_MAXCID]; 18010734SEric Cheng } mac_protect_t; 18110734SEric Cheng 1828275SEric Cheng /* The default priority for links */ 1838275SEric Cheng #define MPL_LINK_DEFAULT MPL_HIGH 1848275SEric Cheng 1858275SEric Cheng /* The default priority for flows */ 1868275SEric Cheng #define MPL_SUBFLOW_DEFAULT MPL_MEDIUM 1878275SEric Cheng 1888275SEric Cheng #define MRP_MAXBW 0x00000001 /* Limit set */ 1898275SEric Cheng #define MRP_CPUS 0x00000002 /* CPU/fanout set */ 1908275SEric Cheng #define MRP_CPUS_USERSPEC 0x00000004 /* CPU/fanout from user */ 1918275SEric Cheng #define MRP_PRIORITY 0x00000008 /* Priority set */ 19210734SEric Cheng #define MRP_PROTECT 0x00000010 /* Protection set */ 193*11878SVenu.Iyer@Sun.COM #define MRP_RX_RINGS 0x00000020 /* Rx rings */ 194*11878SVenu.Iyer@Sun.COM #define MRP_TX_RINGS 0x00000040 /* Tx rings */ 195*11878SVenu.Iyer@Sun.COM #define MRP_RXRINGS_UNSPEC 0x00000080 /* unspecified rings */ 196*11878SVenu.Iyer@Sun.COM #define MRP_TXRINGS_UNSPEC 0x00000100 /* unspecified rings */ 197*11878SVenu.Iyer@Sun.COM #define MRP_RINGS_RESET 0x00000200 /* resetting rings */ 198*11878SVenu.Iyer@Sun.COM #define MRP_POOL 0x00000400 /* CPU pool */ 1998275SEric Cheng 2008275SEric Cheng #define MRP_THROTTLE MRP_MAXBW 2018275SEric Cheng 2028275SEric Cheng /* 3 levels - low, medium, high */ 2038275SEric Cheng #define MRP_PRIORITY_LEVELS 3 2048275SEric Cheng 2058275SEric Cheng /* Special value denoting no bandwidth control */ 2068275SEric Cheng #define MRP_MAXBW_RESETVAL -1ULL 2078275SEric Cheng 2088275SEric Cheng /* 2098275SEric Cheng * Until sub-megabit limit is implemented, 2108275SEric Cheng * reject values lower than 1 MTU per tick or 1.2Mbps 2118275SEric Cheng */ 2128275SEric Cheng #define MRP_MAXBW_MINVAL 1200000 2138275SEric Cheng 2148275SEric Cheng typedef struct mac_resource_props_s { 2158275SEric Cheng /* 2168275SEric Cheng * Bit-mask for the network resource control types types 2178275SEric Cheng */ 2188275SEric Cheng uint32_t mrp_mask; 2198275SEric Cheng uint64_t mrp_maxbw; /* bandwidth limit in bps */ 2208275SEric Cheng mac_priority_level_t mrp_priority; /* relative flow priority */ 2218275SEric Cheng mac_cpus_t mrp_cpus; 22210734SEric Cheng mac_protect_t mrp_protect; 223*11878SVenu.Iyer@Sun.COM uint32_t mrp_nrxrings; 224*11878SVenu.Iyer@Sun.COM uint32_t mrp_ntxrings; 225*11878SVenu.Iyer@Sun.COM char mrp_pool[MAXPATHLEN]; /* CPU pool */ 2268275SEric Cheng } mac_resource_props_t; 2278275SEric Cheng 228*11878SVenu.Iyer@Sun.COM #define mrp_ncpus mrp_cpus.mc_ncpus 229*11878SVenu.Iyer@Sun.COM #define mrp_cpu mrp_cpus.mc_cpus 230*11878SVenu.Iyer@Sun.COM #define mrp_rx_fanout_cnt mrp_cpus.mc_rx_fanout_cnt 231*11878SVenu.Iyer@Sun.COM #define mrp_rx_pollid mrp_cpus.mc_rx_pollid 232*11878SVenu.Iyer@Sun.COM #define mrp_rx_workerid mrp_cpus.mc_rx_workerid 233*11878SVenu.Iyer@Sun.COM #define mrp_rx_intr_cpu mrp_cpus.mc_rx_intr_cpu 234*11878SVenu.Iyer@Sun.COM #define mrp_fanout_mode mrp_cpus.mc_fanout_mode 2358275SEric Cheng 2368275SEric Cheng #define MAC_COPY_CPUS(mrp, fmrp) { \ 2378275SEric Cheng int ncpus; \ 2388275SEric Cheng (fmrp)->mrp_ncpus = (mrp)->mrp_ncpus; \ 239*11878SVenu.Iyer@Sun.COM (fmrp)->mrp_rx_fanout_cnt = (mrp)->mrp_rx_fanout_cnt; \ 240*11878SVenu.Iyer@Sun.COM (fmrp)->mrp_rx_intr_cpu = (mrp)->mrp_rx_intr_cpu; \ 2418275SEric Cheng (fmrp)->mrp_fanout_mode = (mrp)->mrp_fanout_mode; \ 2428275SEric Cheng if ((mrp)->mrp_ncpus == 0) { \ 2438275SEric Cheng (fmrp)->mrp_mask &= ~MRP_CPUS; \ 2448275SEric Cheng (fmrp)->mrp_mask &= ~MRP_CPUS_USERSPEC; \ 2458275SEric Cheng } else { \ 2468275SEric Cheng for (ncpus = 0; ncpus < (fmrp)->mrp_ncpus; ncpus++) \ 2478275SEric Cheng (fmrp)->mrp_cpu[ncpus] = (mrp)->mrp_cpu[ncpus];\ 2488275SEric Cheng (fmrp)->mrp_mask |= MRP_CPUS; \ 2498275SEric Cheng if ((mrp)->mrp_mask & MRP_CPUS_USERSPEC) \ 2508275SEric Cheng (fmrp)->mrp_mask |= MRP_CPUS_USERSPEC; \ 2518275SEric Cheng } \ 2528275SEric Cheng } 2538275SEric Cheng 2548275SEric Cheng #if _LONG_LONG_ALIGNMENT == 8 && _LONG_LONG_ALIGNMENT_32 == 4 2558275SEric Cheng #pragma pack() 2568275SEric Cheng #endif 2578275SEric Cheng 2588275SEric Cheng #ifdef __cplusplus 2598275SEric Cheng } 2608275SEric Cheng #endif 2618275SEric Cheng 2628275SEric Cheng #endif /* _MAC_FLOW_H */ 263