1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #pragma D depends_on module unix 30*0Sstevel@tonic-gate #pragma D depends_on provider sched 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate struct cpuinfo { 33*0Sstevel@tonic-gate processorid_t cpu_id; /* CPU identifier */ 34*0Sstevel@tonic-gate psetid_t cpu_pset; /* processor set identifier */ 35*0Sstevel@tonic-gate chipid_t cpu_chip; /* chip identifier */ 36*0Sstevel@tonic-gate lgrp_id_t cpu_lgrp; /* locality group identifer */ 37*0Sstevel@tonic-gate processor_info_t cpu_info; /* CPU information */ 38*0Sstevel@tonic-gate }; 39*0Sstevel@tonic-gate 40*0Sstevel@tonic-gate typedef struct cpuinfo cpuinfo_t; 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate translator cpuinfo_t < cpu_t *C > { 43*0Sstevel@tonic-gate cpu_id = C->cpu_id; 44*0Sstevel@tonic-gate cpu_pset = C->cpu_part->cp_id; 45*0Sstevel@tonic-gate cpu_chip = C->cpu_chip->chip_id; 46*0Sstevel@tonic-gate cpu_lgrp = C->cpu_chip->chip_lgrp->lgrp_id; 47*0Sstevel@tonic-gate cpu_info = (processor_info_t)C->cpu_type_info; 48*0Sstevel@tonic-gate }; 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate translator cpuinfo_t < disp_t *D > { 51*0Sstevel@tonic-gate cpu_id = D->disp_cpu == NULL ? -1 : 52*0Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_id; 53*0Sstevel@tonic-gate cpu_pset = D->disp_cpu == NULL ? -1 : 54*0Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_pset; 55*0Sstevel@tonic-gate cpu_chip = D->disp_cpu == NULL ? -1 : 56*0Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_chip; 57*0Sstevel@tonic-gate cpu_lgrp = D->disp_cpu == NULL ? -1 : 58*0Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_lgrp; 59*0Sstevel@tonic-gate cpu_info = D->disp_cpu == NULL ? 60*0Sstevel@tonic-gate *((processor_info_t *)dtrace`dtrace_zero) : 61*0Sstevel@tonic-gate (processor_info_t)xlate <cpuinfo_t> (D->disp_cpu).cpu_info; 62*0Sstevel@tonic-gate }; 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate inline cpuinfo_t *curcpu = xlate <cpuinfo_t *> (curthread->t_cpu); 65*0Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common curcpu 66*0Sstevel@tonic-gate #pragma D binding "1.0" curcpu 67*0Sstevel@tonic-gate 68*0Sstevel@tonic-gate inline processorid_t cpu = curcpu->cpu_id; 69*0Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common cpu 70*0Sstevel@tonic-gate #pragma D binding "1.0" cpu 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate inline psetid_t pset = curcpu->cpu_pset; 73*0Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common pset 74*0Sstevel@tonic-gate #pragma D binding "1.0" pset 75*0Sstevel@tonic-gate 76*0Sstevel@tonic-gate inline chipid_t chip = curcpu->cpu_chip; 77*0Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common chip 78*0Sstevel@tonic-gate #pragma D binding "1.0" chip 79*0Sstevel@tonic-gate 80*0Sstevel@tonic-gate inline lgrp_id_t lgrp = curcpu->cpu_lgrp; 81*0Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common lgrp 82*0Sstevel@tonic-gate #pragma D binding "1.0" lgrp 83*0Sstevel@tonic-gate 84