10Sstevel@tonic-gate /* 20Sstevel@tonic-gate * CDDL HEADER START 30Sstevel@tonic-gate * 40Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*1892Sesaxe * Common Development and Distribution License (the "License"). 6*1892Sesaxe * You may not use this file except in compliance with the License. 70Sstevel@tonic-gate * 80Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 100Sstevel@tonic-gate * See the License for the specific language governing permissions 110Sstevel@tonic-gate * and limitations under the License. 120Sstevel@tonic-gate * 130Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 140Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 160Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 170Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 180Sstevel@tonic-gate * 190Sstevel@tonic-gate * CDDL HEADER END 200Sstevel@tonic-gate */ 210Sstevel@tonic-gate /* 22*1892Sesaxe * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 230Sstevel@tonic-gate * Use is subject to license terms. 240Sstevel@tonic-gate */ 250Sstevel@tonic-gate 260Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 270Sstevel@tonic-gate 280Sstevel@tonic-gate #pragma D depends_on module unix 290Sstevel@tonic-gate #pragma D depends_on provider sched 300Sstevel@tonic-gate 310Sstevel@tonic-gate struct cpuinfo { 320Sstevel@tonic-gate processorid_t cpu_id; /* CPU identifier */ 330Sstevel@tonic-gate psetid_t cpu_pset; /* processor set identifier */ 340Sstevel@tonic-gate chipid_t cpu_chip; /* chip identifier */ 350Sstevel@tonic-gate lgrp_id_t cpu_lgrp; /* locality group identifer */ 360Sstevel@tonic-gate processor_info_t cpu_info; /* CPU information */ 370Sstevel@tonic-gate }; 380Sstevel@tonic-gate 390Sstevel@tonic-gate typedef struct cpuinfo cpuinfo_t; 400Sstevel@tonic-gate 410Sstevel@tonic-gate translator cpuinfo_t < cpu_t *C > { 420Sstevel@tonic-gate cpu_id = C->cpu_id; 430Sstevel@tonic-gate cpu_pset = C->cpu_part->cp_id; 44*1892Sesaxe cpu_chip = C->cpu_physid->cpu_chipid; 45*1892Sesaxe cpu_lgrp = C->cpu_lpl->lpl_lgrpid; 460Sstevel@tonic-gate cpu_info = (processor_info_t)C->cpu_type_info; 470Sstevel@tonic-gate }; 480Sstevel@tonic-gate 490Sstevel@tonic-gate translator cpuinfo_t < disp_t *D > { 500Sstevel@tonic-gate cpu_id = D->disp_cpu == NULL ? -1 : 510Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_id; 520Sstevel@tonic-gate cpu_pset = D->disp_cpu == NULL ? -1 : 530Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_pset; 540Sstevel@tonic-gate cpu_chip = D->disp_cpu == NULL ? -1 : 550Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_chip; 560Sstevel@tonic-gate cpu_lgrp = D->disp_cpu == NULL ? -1 : 570Sstevel@tonic-gate xlate <cpuinfo_t> (D->disp_cpu).cpu_lgrp; 580Sstevel@tonic-gate cpu_info = D->disp_cpu == NULL ? 590Sstevel@tonic-gate *((processor_info_t *)dtrace`dtrace_zero) : 600Sstevel@tonic-gate (processor_info_t)xlate <cpuinfo_t> (D->disp_cpu).cpu_info; 610Sstevel@tonic-gate }; 620Sstevel@tonic-gate 630Sstevel@tonic-gate inline cpuinfo_t *curcpu = xlate <cpuinfo_t *> (curthread->t_cpu); 640Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common curcpu 650Sstevel@tonic-gate #pragma D binding "1.0" curcpu 660Sstevel@tonic-gate 670Sstevel@tonic-gate inline processorid_t cpu = curcpu->cpu_id; 680Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common cpu 690Sstevel@tonic-gate #pragma D binding "1.0" cpu 700Sstevel@tonic-gate 710Sstevel@tonic-gate inline psetid_t pset = curcpu->cpu_pset; 720Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common pset 730Sstevel@tonic-gate #pragma D binding "1.0" pset 740Sstevel@tonic-gate 750Sstevel@tonic-gate inline chipid_t chip = curcpu->cpu_chip; 760Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common chip 770Sstevel@tonic-gate #pragma D binding "1.0" chip 780Sstevel@tonic-gate 790Sstevel@tonic-gate inline lgrp_id_t lgrp = curcpu->cpu_lgrp; 800Sstevel@tonic-gate #pragma D attributes Stable/Stable/Common lgrp 810Sstevel@tonic-gate #pragma D binding "1.0" lgrp 820Sstevel@tonic-gate 83