1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * DTrace Parsing Control Block 31*0Sstevel@tonic-gate * 32*0Sstevel@tonic-gate * A DTrace Parsing Control Block (PCB) contains all of the state that is used 33*0Sstevel@tonic-gate * by a single pass of the D compiler, other than the global variables used by 34*0Sstevel@tonic-gate * lex and yacc. The routines in this file are used to set up and tear down 35*0Sstevel@tonic-gate * PCBs, which are kept on a stack pointed to by the libdtrace global 'yypcb'. 36*0Sstevel@tonic-gate * The main engine of the compiler, dt_compile(), is located in dt_cc.c and is 37*0Sstevel@tonic-gate * responsible for calling these routines to begin and end a compilation pass. 38*0Sstevel@tonic-gate * 39*0Sstevel@tonic-gate * Sun's lex/yacc are not MT-safe or re-entrant, but we permit limited nested 40*0Sstevel@tonic-gate * use of dt_compile() once the entire parse tree has been constructed but has 41*0Sstevel@tonic-gate * not yet executed the "cooking" pass (see dt_cc.c for more information). The 42*0Sstevel@tonic-gate * PCB design also makes it easier to debug (since all global state is kept in 43*0Sstevel@tonic-gate * one place) and could permit us to make the D compiler MT-safe or re-entrant 44*0Sstevel@tonic-gate * in the future by adding locks to libdtrace or switching to Flex and Bison. 45*0Sstevel@tonic-gate */ 46*0Sstevel@tonic-gate 47*0Sstevel@tonic-gate #include <strings.h> 48*0Sstevel@tonic-gate #include <stdlib.h> 49*0Sstevel@tonic-gate #include <assert.h> 50*0Sstevel@tonic-gate 51*0Sstevel@tonic-gate #include <dt_impl.h> 52*0Sstevel@tonic-gate #include <dt_provider.h> 53*0Sstevel@tonic-gate #include <dt_pcb.h> 54*0Sstevel@tonic-gate 55*0Sstevel@tonic-gate /* 56*0Sstevel@tonic-gate * Initialize the specified PCB by zeroing it and filling in a few default 57*0Sstevel@tonic-gate * members, and then pushing it on to the top of the PCB stack and setting 58*0Sstevel@tonic-gate * yypcb to point to it. Increment the current handle's generation count. 59*0Sstevel@tonic-gate */ 60*0Sstevel@tonic-gate void 61*0Sstevel@tonic-gate dt_pcb_push(dtrace_hdl_t *dtp, dt_pcb_t *pcb) 62*0Sstevel@tonic-gate { 63*0Sstevel@tonic-gate /* 64*0Sstevel@tonic-gate * Since lex/yacc are not re-entrant and we don't implement state save, 65*0Sstevel@tonic-gate * assert that if another PCB is active, it is from the same handle and 66*0Sstevel@tonic-gate * has completed execution of yyparse(). If the first assertion fires, 67*0Sstevel@tonic-gate * the caller is calling libdtrace without proper MT locking. If the 68*0Sstevel@tonic-gate * second assertion fires, dt_compile() is being called recursively 69*0Sstevel@tonic-gate * from an illegal location in libdtrace, or a dt_pcb_pop() is missing. 70*0Sstevel@tonic-gate */ 71*0Sstevel@tonic-gate if (yypcb != NULL) { 72*0Sstevel@tonic-gate assert(yypcb->pcb_hdl == dtp); 73*0Sstevel@tonic-gate assert(yypcb->pcb_yystate == YYS_DONE); 74*0Sstevel@tonic-gate } 75*0Sstevel@tonic-gate 76*0Sstevel@tonic-gate bzero(pcb, sizeof (dt_pcb_t)); 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate dt_scope_create(&pcb->pcb_dstack); 79*0Sstevel@tonic-gate dt_idstack_push(&pcb->pcb_globals, dtp->dt_globals); 80*0Sstevel@tonic-gate dt_irlist_create(&pcb->pcb_ir); 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate pcb->pcb_hdl = dtp; 83*0Sstevel@tonic-gate pcb->pcb_prev = dtp->dt_pcb; 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate dtp->dt_pcb = pcb; 86*0Sstevel@tonic-gate dtp->dt_gen++; 87*0Sstevel@tonic-gate 88*0Sstevel@tonic-gate yyinit(pcb); 89*0Sstevel@tonic-gate } 90*0Sstevel@tonic-gate 91*0Sstevel@tonic-gate static int 92*0Sstevel@tonic-gate dt_pcb_pop_ident(dt_idhash_t *dhp, dt_ident_t *idp, void *arg) 93*0Sstevel@tonic-gate { 94*0Sstevel@tonic-gate dtrace_hdl_t *dtp = arg; 95*0Sstevel@tonic-gate 96*0Sstevel@tonic-gate if (idp->di_gen == dtp->dt_gen) 97*0Sstevel@tonic-gate dt_idhash_delete(dhp, idp); 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate return (0); 100*0Sstevel@tonic-gate } 101*0Sstevel@tonic-gate 102*0Sstevel@tonic-gate /* 103*0Sstevel@tonic-gate * Pop the topmost PCB from the PCB stack and destroy any data structures that 104*0Sstevel@tonic-gate * are associated with it. If 'err' is non-zero, destroy any intermediate 105*0Sstevel@tonic-gate * state that is left behind as part of a compilation that has failed. 106*0Sstevel@tonic-gate */ 107*0Sstevel@tonic-gate void 108*0Sstevel@tonic-gate dt_pcb_pop(dtrace_hdl_t *dtp, int err) 109*0Sstevel@tonic-gate { 110*0Sstevel@tonic-gate dt_pcb_t *pcb = yypcb; 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate assert(pcb != NULL); 113*0Sstevel@tonic-gate assert(pcb == dtp->dt_pcb); 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate while (pcb->pcb_dstack.ds_next != NULL) 116*0Sstevel@tonic-gate (void) dt_scope_pop(); 117*0Sstevel@tonic-gate 118*0Sstevel@tonic-gate dt_scope_destroy(&pcb->pcb_dstack); 119*0Sstevel@tonic-gate dt_irlist_destroy(&pcb->pcb_ir); 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate dt_node_link_free(&pcb->pcb_list); 122*0Sstevel@tonic-gate dt_node_link_free(&pcb->pcb_hold); 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate if (err != 0) { 125*0Sstevel@tonic-gate dt_xlator_t *dxp, *nxp; 126*0Sstevel@tonic-gate dt_provider_t *pvp, *nvp; 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate if (pcb->pcb_pred != NULL) 129*0Sstevel@tonic-gate dtrace_difo_release(pcb->pcb_pred); 130*0Sstevel@tonic-gate if (pcb->pcb_prog != NULL) 131*0Sstevel@tonic-gate dtrace_program_destroy(dtp, pcb->pcb_prog); 132*0Sstevel@tonic-gate if (pcb->pcb_stmt != NULL) 133*0Sstevel@tonic-gate dtrace_stmt_destroy(pcb->pcb_stmt); 134*0Sstevel@tonic-gate if (pcb->pcb_ecbdesc != NULL) 135*0Sstevel@tonic-gate dtrace_ecbdesc_release(pcb->pcb_ecbdesc); 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate for (dxp = dt_list_next(&dtp->dt_xlators); dxp; dxp = nxp) { 138*0Sstevel@tonic-gate nxp = dt_list_next(dxp); 139*0Sstevel@tonic-gate if (dxp->dx_gen == dtp->dt_gen) 140*0Sstevel@tonic-gate dt_xlator_destroy(dtp, dxp); 141*0Sstevel@tonic-gate } 142*0Sstevel@tonic-gate 143*0Sstevel@tonic-gate for (pvp = dt_list_next(&dtp->dt_provlist); pvp; pvp = nvp) { 144*0Sstevel@tonic-gate nvp = dt_list_next(pvp); 145*0Sstevel@tonic-gate if (pvp->pv_gen == dtp->dt_gen) 146*0Sstevel@tonic-gate dt_provider_destroy(dtp, pvp); 147*0Sstevel@tonic-gate } 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate (void) dt_idhash_iter(dtp->dt_aggs, dt_pcb_pop_ident, dtp); 150*0Sstevel@tonic-gate dt_idhash_update(dtp->dt_aggs); 151*0Sstevel@tonic-gate 152*0Sstevel@tonic-gate (void) dt_idhash_iter(dtp->dt_globals, dt_pcb_pop_ident, dtp); 153*0Sstevel@tonic-gate dt_idhash_update(dtp->dt_globals); 154*0Sstevel@tonic-gate 155*0Sstevel@tonic-gate (void) dt_idhash_iter(dtp->dt_tls, dt_pcb_pop_ident, dtp); 156*0Sstevel@tonic-gate dt_idhash_update(dtp->dt_tls); 157*0Sstevel@tonic-gate 158*0Sstevel@tonic-gate (void) ctf_discard(dtp->dt_cdefs->dm_ctfp); 159*0Sstevel@tonic-gate (void) ctf_discard(dtp->dt_ddefs->dm_ctfp); 160*0Sstevel@tonic-gate } 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate if (pcb->pcb_pragmas != NULL) 163*0Sstevel@tonic-gate dt_idhash_destroy(pcb->pcb_pragmas); 164*0Sstevel@tonic-gate if (pcb->pcb_locals != NULL) 165*0Sstevel@tonic-gate dt_idhash_destroy(pcb->pcb_locals); 166*0Sstevel@tonic-gate if (pcb->pcb_idents != NULL) 167*0Sstevel@tonic-gate dt_idhash_destroy(pcb->pcb_idents); 168*0Sstevel@tonic-gate if (pcb->pcb_inttab != NULL) 169*0Sstevel@tonic-gate dt_inttab_destroy(pcb->pcb_inttab); 170*0Sstevel@tonic-gate if (pcb->pcb_strtab != NULL) 171*0Sstevel@tonic-gate dt_strtab_destroy(pcb->pcb_strtab); 172*0Sstevel@tonic-gate if (pcb->pcb_regs != NULL) 173*0Sstevel@tonic-gate dt_regset_destroy(pcb->pcb_regs); 174*0Sstevel@tonic-gate if (pcb->pcb_difo != NULL) 175*0Sstevel@tonic-gate dtrace_difo_release(pcb->pcb_difo); 176*0Sstevel@tonic-gate 177*0Sstevel@tonic-gate free(pcb->pcb_filetag); 178*0Sstevel@tonic-gate free(pcb->pcb_sflagv); 179*0Sstevel@tonic-gate 180*0Sstevel@tonic-gate dtp->dt_pcb = pcb->pcb_prev; 181*0Sstevel@tonic-gate bzero(pcb, sizeof (dt_pcb_t)); 182*0Sstevel@tonic-gate yyinit(dtp->dt_pcb); 183*0Sstevel@tonic-gate } 184