xref: /onnv-gate/usr/src/lib/libdtrace/common/dt_pcb.c (revision 265:a968e4ece133)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
50Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
60Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
70Sstevel@tonic-gate  * with the License.
80Sstevel@tonic-gate  *
90Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
100Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
110Sstevel@tonic-gate  * See the License for the specific language governing permissions
120Sstevel@tonic-gate  * and limitations under the License.
130Sstevel@tonic-gate  *
140Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
150Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
160Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
170Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
180Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
190Sstevel@tonic-gate  *
200Sstevel@tonic-gate  * CDDL HEADER END
210Sstevel@tonic-gate  */
220Sstevel@tonic-gate /*
230Sstevel@tonic-gate  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
240Sstevel@tonic-gate  * Use is subject to license terms.
250Sstevel@tonic-gate  */
260Sstevel@tonic-gate 
270Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
280Sstevel@tonic-gate 
290Sstevel@tonic-gate /*
300Sstevel@tonic-gate  * DTrace Parsing Control Block
310Sstevel@tonic-gate  *
320Sstevel@tonic-gate  * A DTrace Parsing Control Block (PCB) contains all of the state that is used
330Sstevel@tonic-gate  * by a single pass of the D compiler, other than the global variables used by
340Sstevel@tonic-gate  * lex and yacc.  The routines in this file are used to set up and tear down
350Sstevel@tonic-gate  * PCBs, which are kept on a stack pointed to by the libdtrace global 'yypcb'.
360Sstevel@tonic-gate  * The main engine of the compiler, dt_compile(), is located in dt_cc.c and is
370Sstevel@tonic-gate  * responsible for calling these routines to begin and end a compilation pass.
380Sstevel@tonic-gate  *
390Sstevel@tonic-gate  * Sun's lex/yacc are not MT-safe or re-entrant, but we permit limited nested
400Sstevel@tonic-gate  * use of dt_compile() once the entire parse tree has been constructed but has
410Sstevel@tonic-gate  * not yet executed the "cooking" pass (see dt_cc.c for more information).  The
420Sstevel@tonic-gate  * PCB design also makes it easier to debug (since all global state is kept in
430Sstevel@tonic-gate  * one place) and could permit us to make the D compiler MT-safe or re-entrant
440Sstevel@tonic-gate  * in the future by adding locks to libdtrace or switching to Flex and Bison.
450Sstevel@tonic-gate  */
460Sstevel@tonic-gate 
470Sstevel@tonic-gate #include <strings.h>
480Sstevel@tonic-gate #include <stdlib.h>
490Sstevel@tonic-gate #include <assert.h>
500Sstevel@tonic-gate 
510Sstevel@tonic-gate #include <dt_impl.h>
52*265Smws #include <dt_program.h>
530Sstevel@tonic-gate #include <dt_provider.h>
540Sstevel@tonic-gate #include <dt_pcb.h>
550Sstevel@tonic-gate 
560Sstevel@tonic-gate /*
570Sstevel@tonic-gate  * Initialize the specified PCB by zeroing it and filling in a few default
580Sstevel@tonic-gate  * members, and then pushing it on to the top of the PCB stack and setting
590Sstevel@tonic-gate  * yypcb to point to it.  Increment the current handle's generation count.
600Sstevel@tonic-gate  */
610Sstevel@tonic-gate void
dt_pcb_push(dtrace_hdl_t * dtp,dt_pcb_t * pcb)620Sstevel@tonic-gate dt_pcb_push(dtrace_hdl_t *dtp, dt_pcb_t *pcb)
630Sstevel@tonic-gate {
640Sstevel@tonic-gate 	/*
650Sstevel@tonic-gate 	 * Since lex/yacc are not re-entrant and we don't implement state save,
660Sstevel@tonic-gate 	 * assert that if another PCB is active, it is from the same handle and
670Sstevel@tonic-gate 	 * has completed execution of yyparse().  If the first assertion fires,
680Sstevel@tonic-gate 	 * the caller is calling libdtrace without proper MT locking.  If the
690Sstevel@tonic-gate 	 * second assertion fires, dt_compile() is being called recursively
700Sstevel@tonic-gate 	 * from an illegal location in libdtrace, or a dt_pcb_pop() is missing.
710Sstevel@tonic-gate 	 */
720Sstevel@tonic-gate 	if (yypcb != NULL) {
730Sstevel@tonic-gate 		assert(yypcb->pcb_hdl == dtp);
740Sstevel@tonic-gate 		assert(yypcb->pcb_yystate == YYS_DONE);
750Sstevel@tonic-gate 	}
760Sstevel@tonic-gate 
770Sstevel@tonic-gate 	bzero(pcb, sizeof (dt_pcb_t));
780Sstevel@tonic-gate 
790Sstevel@tonic-gate 	dt_scope_create(&pcb->pcb_dstack);
800Sstevel@tonic-gate 	dt_idstack_push(&pcb->pcb_globals, dtp->dt_globals);
810Sstevel@tonic-gate 	dt_irlist_create(&pcb->pcb_ir);
820Sstevel@tonic-gate 
830Sstevel@tonic-gate 	pcb->pcb_hdl = dtp;
840Sstevel@tonic-gate 	pcb->pcb_prev = dtp->dt_pcb;
850Sstevel@tonic-gate 
860Sstevel@tonic-gate 	dtp->dt_pcb = pcb;
870Sstevel@tonic-gate 	dtp->dt_gen++;
880Sstevel@tonic-gate 
890Sstevel@tonic-gate 	yyinit(pcb);
900Sstevel@tonic-gate }
910Sstevel@tonic-gate 
920Sstevel@tonic-gate static int
dt_pcb_pop_ident(dt_idhash_t * dhp,dt_ident_t * idp,void * arg)930Sstevel@tonic-gate dt_pcb_pop_ident(dt_idhash_t *dhp, dt_ident_t *idp, void *arg)
940Sstevel@tonic-gate {
950Sstevel@tonic-gate 	dtrace_hdl_t *dtp = arg;
960Sstevel@tonic-gate 
970Sstevel@tonic-gate 	if (idp->di_gen == dtp->dt_gen)
980Sstevel@tonic-gate 		dt_idhash_delete(dhp, idp);
990Sstevel@tonic-gate 
1000Sstevel@tonic-gate 	return (0);
1010Sstevel@tonic-gate }
1020Sstevel@tonic-gate 
1030Sstevel@tonic-gate /*
1040Sstevel@tonic-gate  * Pop the topmost PCB from the PCB stack and destroy any data structures that
1050Sstevel@tonic-gate  * are associated with it.  If 'err' is non-zero, destroy any intermediate
1060Sstevel@tonic-gate  * state that is left behind as part of a compilation that has failed.
1070Sstevel@tonic-gate  */
1080Sstevel@tonic-gate void
dt_pcb_pop(dtrace_hdl_t * dtp,int err)1090Sstevel@tonic-gate dt_pcb_pop(dtrace_hdl_t *dtp, int err)
1100Sstevel@tonic-gate {
1110Sstevel@tonic-gate 	dt_pcb_t *pcb = yypcb;
112*265Smws 	uint_t i;
1130Sstevel@tonic-gate 
1140Sstevel@tonic-gate 	assert(pcb != NULL);
1150Sstevel@tonic-gate 	assert(pcb == dtp->dt_pcb);
1160Sstevel@tonic-gate 
1170Sstevel@tonic-gate 	while (pcb->pcb_dstack.ds_next != NULL)
1180Sstevel@tonic-gate 		(void) dt_scope_pop();
1190Sstevel@tonic-gate 
1200Sstevel@tonic-gate 	dt_scope_destroy(&pcb->pcb_dstack);
1210Sstevel@tonic-gate 	dt_irlist_destroy(&pcb->pcb_ir);
1220Sstevel@tonic-gate 
1230Sstevel@tonic-gate 	dt_node_link_free(&pcb->pcb_list);
1240Sstevel@tonic-gate 	dt_node_link_free(&pcb->pcb_hold);
1250Sstevel@tonic-gate 
1260Sstevel@tonic-gate 	if (err != 0) {
1270Sstevel@tonic-gate 		dt_xlator_t *dxp, *nxp;
1280Sstevel@tonic-gate 		dt_provider_t *pvp, *nvp;
1290Sstevel@tonic-gate 
1300Sstevel@tonic-gate 		if (pcb->pcb_prog != NULL)
131*265Smws 			dt_program_destroy(dtp, pcb->pcb_prog);
1320Sstevel@tonic-gate 		if (pcb->pcb_stmt != NULL)
133*265Smws 			dtrace_stmt_destroy(dtp, pcb->pcb_stmt);
1340Sstevel@tonic-gate 		if (pcb->pcb_ecbdesc != NULL)
135*265Smws 			dt_ecbdesc_release(dtp, pcb->pcb_ecbdesc);
1360Sstevel@tonic-gate 
1370Sstevel@tonic-gate 		for (dxp = dt_list_next(&dtp->dt_xlators); dxp; dxp = nxp) {
1380Sstevel@tonic-gate 			nxp = dt_list_next(dxp);
1390Sstevel@tonic-gate 			if (dxp->dx_gen == dtp->dt_gen)
1400Sstevel@tonic-gate 				dt_xlator_destroy(dtp, dxp);
1410Sstevel@tonic-gate 		}
1420Sstevel@tonic-gate 
1430Sstevel@tonic-gate 		for (pvp = dt_list_next(&dtp->dt_provlist); pvp; pvp = nvp) {
1440Sstevel@tonic-gate 			nvp = dt_list_next(pvp);
1450Sstevel@tonic-gate 			if (pvp->pv_gen == dtp->dt_gen)
1460Sstevel@tonic-gate 				dt_provider_destroy(dtp, pvp);
1470Sstevel@tonic-gate 		}
1480Sstevel@tonic-gate 
1490Sstevel@tonic-gate 		(void) dt_idhash_iter(dtp->dt_aggs, dt_pcb_pop_ident, dtp);
1500Sstevel@tonic-gate 		dt_idhash_update(dtp->dt_aggs);
1510Sstevel@tonic-gate 
1520Sstevel@tonic-gate 		(void) dt_idhash_iter(dtp->dt_globals, dt_pcb_pop_ident, dtp);
1530Sstevel@tonic-gate 		dt_idhash_update(dtp->dt_globals);
1540Sstevel@tonic-gate 
1550Sstevel@tonic-gate 		(void) dt_idhash_iter(dtp->dt_tls, dt_pcb_pop_ident, dtp);
1560Sstevel@tonic-gate 		dt_idhash_update(dtp->dt_tls);
1570Sstevel@tonic-gate 
1580Sstevel@tonic-gate 		(void) ctf_discard(dtp->dt_cdefs->dm_ctfp);
1590Sstevel@tonic-gate 		(void) ctf_discard(dtp->dt_ddefs->dm_ctfp);
1600Sstevel@tonic-gate 	}
1610Sstevel@tonic-gate 
1620Sstevel@tonic-gate 	if (pcb->pcb_pragmas != NULL)
1630Sstevel@tonic-gate 		dt_idhash_destroy(pcb->pcb_pragmas);
1640Sstevel@tonic-gate 	if (pcb->pcb_locals != NULL)
1650Sstevel@tonic-gate 		dt_idhash_destroy(pcb->pcb_locals);
1660Sstevel@tonic-gate 	if (pcb->pcb_idents != NULL)
1670Sstevel@tonic-gate 		dt_idhash_destroy(pcb->pcb_idents);
1680Sstevel@tonic-gate 	if (pcb->pcb_inttab != NULL)
1690Sstevel@tonic-gate 		dt_inttab_destroy(pcb->pcb_inttab);
1700Sstevel@tonic-gate 	if (pcb->pcb_strtab != NULL)
1710Sstevel@tonic-gate 		dt_strtab_destroy(pcb->pcb_strtab);
1720Sstevel@tonic-gate 	if (pcb->pcb_regs != NULL)
1730Sstevel@tonic-gate 		dt_regset_destroy(pcb->pcb_regs);
174*265Smws 
175*265Smws 	for (i = 0; i < pcb->pcb_asxreflen; i++)
176*265Smws 		dt_free(dtp, pcb->pcb_asxrefs[i]);
177*265Smws 
178*265Smws 	dt_free(dtp, pcb->pcb_asxrefs);
179*265Smws 	dt_difo_free(dtp, pcb->pcb_difo);
1800Sstevel@tonic-gate 
1810Sstevel@tonic-gate 	free(pcb->pcb_filetag);
1820Sstevel@tonic-gate 	free(pcb->pcb_sflagv);
1830Sstevel@tonic-gate 
1840Sstevel@tonic-gate 	dtp->dt_pcb = pcb->pcb_prev;
1850Sstevel@tonic-gate 	bzero(pcb, sizeof (dt_pcb_t));
1860Sstevel@tonic-gate 	yyinit(dtp->dt_pcb);
1870Sstevel@tonic-gate }
188