1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SUN4_MMU_H 28*0Sstevel@tonic-gate #define _SUN4_MMU_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * Sun-4 memory management unit. 38*0Sstevel@tonic-gate * All sun-4 implementations use 32 bits of address. 39*0Sstevel@tonic-gate * A particular implementation may implement a smaller MMU. 40*0Sstevel@tonic-gate * If so, the missing addresses are in the "middle" of the 41*0Sstevel@tonic-gate * 32 bit address space. All accesses in this range behave 42*0Sstevel@tonic-gate * as if there was an invalid page map entry correspronding 43*0Sstevel@tonic-gate * to the address. 44*0Sstevel@tonic-gate * 45*0Sstevel@tonic-gate * There are two types of MMUs a 2 level MMU and a 3 level MMU. 46*0Sstevel@tonic-gate * Three level MMUs do not have holes. 47*0Sstevel@tonic-gate */ 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate /* 50*0Sstevel@tonic-gate * Hardware context and segment information 51*0Sstevel@tonic-gate * Mnemonic decoding: 52*0Sstevel@tonic-gate * PMENT - Page Map ENTry 53*0Sstevel@tonic-gate * PMGRP - Group of PMENTs (aka "segment") 54*0Sstevel@tonic-gate * SMENT - Segment Map ENTry - 3 level MMU only 55*0Sstevel@tonic-gate * SMGRP - Group of SMENTs (aka "region") - 3 level MMU only 56*0Sstevel@tonic-gate */ 57*0Sstevel@tonic-gate /* fixed SUN4 constants */ 58*0Sstevel@tonic-gate #define NPMENTPERPMGRP 32 59*0Sstevel@tonic-gate #define NPMENTPERPMGRPSHIFT 5 /* log2(NPMENTPERPMGRP) */ 60*0Sstevel@tonic-gate #define PMGRPSIZE (NPMENTPERPMGRP * PAGESIZE) 61*0Sstevel@tonic-gate #define PMGRPOFFSET (PMGRPSIZE - 1) 62*0Sstevel@tonic-gate #define PMGRPSHIFT (PAGESHIFT + NPMENTPERPMGRPSHIFT) 63*0Sstevel@tonic-gate #define PMGRPMASK (~PMGRPOFFSET) 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate #define NSMENTPERSMGRP 64 66*0Sstevel@tonic-gate #define NSMENTPERSMGRPSHIFT 6 /* log2(NSMENTPERSMGRP) */ 67*0Sstevel@tonic-gate #define SMGRPSIZE (NSMENTPERSMGRP * PMGRPSIZE) 68*0Sstevel@tonic-gate #define SMGRPOFFSET (SMGRPSIZE - 1) 69*0Sstevel@tonic-gate #define SMGRPSHIFT (PMGRPSHIFT + NSMENTPERSMGRPSHIFT) 70*0Sstevel@tonic-gate #define SMGRPMASK (~SMGRPOFFSET) 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate #define NSMGRPPERCTX 256 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate /* 75*0Sstevel@tonic-gate * Useful defines for hat constants, 76*0Sstevel@tonic-gate * Every implementation seems to have its own set 77*0Sstevel@tonic-gate * they are set at boot time by setcputype() 78*0Sstevel@tonic-gate */ 79*0Sstevel@tonic-gate #define NCTXS nctxs 80*0Sstevel@tonic-gate #define NPMGRPS npmgrps 81*0Sstevel@tonic-gate #define NSMGRPS nsmgrps 82*0Sstevel@tonic-gate 83*0Sstevel@tonic-gate /* 84*0Sstevel@tonic-gate * Variables set at boot time to reflect cpu type. 85*0Sstevel@tonic-gate */ 86*0Sstevel@tonic-gate #ifndef LOCORE 87*0Sstevel@tonic-gate #include <sys/types.h> 88*0Sstevel@tonic-gate 89*0Sstevel@tonic-gate extern uint_t nctxs; /* number of implemented contexts */ 90*0Sstevel@tonic-gate extern uint_t npmgrps; /* number of pmgrps in page map */ 91*0Sstevel@tonic-gate #ifdef MMU_3LEVEL 92*0Sstevel@tonic-gate extern uint_t nsmgrps; /* number of smgrps in segment map (3 level) */ 93*0Sstevel@tonic-gate #endif /* MMU_3LEVEL */ 94*0Sstevel@tonic-gate extern uint_t segmask; /* mask for segment number */ 95*0Sstevel@tonic-gate extern addr_t hole_start; /* addr of start of MMU "hole" */ 96*0Sstevel@tonic-gate extern addr_t hole_end; /* addr of end of MMU "hole" */ 97*0Sstevel@tonic-gate extern uint_t shm_alignment; /* VAC address consistency modulus */ 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate #ifdef MMU_3LEVEL 100*0Sstevel@tonic-gate extern int mmu_3level; /* indicates 3 level MMU can exist */ 101*0Sstevel@tonic-gate #endif /* MMU_3LEVEL */ 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate #define PMGRP_INVALID (NPMGRPS - 1) 104*0Sstevel@tonic-gate #define SMGRP_INVALID (NSMGRPS - 1) 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate /* 107*0Sstevel@tonic-gate * Macro to determine whether an address is within the range of the MMU. 108*0Sstevel@tonic-gate */ 109*0Sstevel@tonic-gate #ifdef MMU_3LEVEL 110*0Sstevel@tonic-gate #define good_addr(a) \ 111*0Sstevel@tonic-gate (mmu_3level || (addr_t)(a) < hole_start || (addr_t)(a) >= hole_end) 112*0Sstevel@tonic-gate #else 113*0Sstevel@tonic-gate #define good_addr(a) \ 114*0Sstevel@tonic-gate ((addr_t)(a) < hole_start || (addr_t)(a) >= hole_end) 115*0Sstevel@tonic-gate #endif /* MMU_3LEVEL */ 116*0Sstevel@tonic-gate #endif /* !LOCORE */ 117*0Sstevel@tonic-gate 118*0Sstevel@tonic-gate /* 119*0Sstevel@tonic-gate * Address space identifiers. 120*0Sstevel@tonic-gate */ 121*0Sstevel@tonic-gate #define ASI_CTL 0x2 /* control space */ 122*0Sstevel@tonic-gate #define ASI_SM 0x3 /* segment map */ 123*0Sstevel@tonic-gate #define ASI_PM 0x4 /* page map */ 124*0Sstevel@tonic-gate #define ASI_BC 0x5 /* block copy */ 125*0Sstevel@tonic-gate #define ASI_RM 0x6 /* region map */ 126*0Sstevel@tonic-gate #define ASI_FCR 0x7 /* flush cache region */ 127*0Sstevel@tonic-gate #define ASI_UP 0x8 /* user program */ 128*0Sstevel@tonic-gate #define ASI_SP 0x9 /* supervisor program */ 129*0Sstevel@tonic-gate #define ASI_UD 0xA /* user data */ 130*0Sstevel@tonic-gate #define ASI_SD 0xB /* supervisor data */ 131*0Sstevel@tonic-gate #define ASI_FCS 0xC /* flush cache segment */ 132*0Sstevel@tonic-gate #define ASI_FCP 0xD /* flush cache page */ 133*0Sstevel@tonic-gate #define ASI_FCC 0xE /* flush cache context */ 134*0Sstevel@tonic-gate #define ASI_FCU 0xF /* flush cache user, sunray */ 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate #define ASI_CD 0xF /* cache data, sunrise */ 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate /* 139*0Sstevel@tonic-gate * ASI_CTL addresses 140*0Sstevel@tonic-gate */ 141*0Sstevel@tonic-gate #define ID_PROM 0x00000000 142*0Sstevel@tonic-gate #define CONTEXT_REG 0x30000000 143*0Sstevel@tonic-gate #define SYSTEM_ENABLE 0x40000000 144*0Sstevel@tonic-gate #define BUS_ERROR_REG 0x60000000 145*0Sstevel@tonic-gate #define DIAGNOSTIC_REG 0x70000000 146*0Sstevel@tonic-gate #define CACHE_TAGS 0x80000000 147*0Sstevel@tonic-gate #define CACHE_DATA 0x90000000 /* cache data, sunray */ 148*0Sstevel@tonic-gate #define VME_INT_VEC 0xE0000000 149*0Sstevel@tonic-gate #define UART_BYPASS 0xF0000000 150*0Sstevel@tonic-gate 151*0Sstevel@tonic-gate #define IDPROMSIZE 0x20 /* size of id prom in bytes */ 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate /* 154*0Sstevel@tonic-gate * Constants for cache operations. 155*0Sstevel@tonic-gate * XXX - should be deleted but the standalones (boot) use them. 156*0Sstevel@tonic-gate */ 157*0Sstevel@tonic-gate #define VAC_SIZE 0x20000 /* 128K */ 158*0Sstevel@tonic-gate #define VAC_LINESIZE_SUNRISE 16 /* 16 bytes per line */ 159*0Sstevel@tonic-gate #define VAC_LINESIZE_SUNRAY 32 /* 32 bytes per line */ 160*0Sstevel@tonic-gate #define NPMGRPPERCTX_110 4096 161*0Sstevel@tonic-gate #define NPMGRPPERCTX_260 4096 162*0Sstevel@tonic-gate #define NPMGRPPERCTX_330 4096 163*0Sstevel@tonic-gate #define NPMGRPS_110 256 164*0Sstevel@tonic-gate #define NPMGRPS_260 512 165*0Sstevel@tonic-gate #define NPMGRPS_330 256 166*0Sstevel@tonic-gate #define NPMGRPS_470 1024 167*0Sstevel@tonic-gate 168*0Sstevel@tonic-gate /* 169*0Sstevel@tonic-gate * Various I/O space related constants 170*0Sstevel@tonic-gate */ 171*0Sstevel@tonic-gate #define VME16_BASE 0xFFFF0000 172*0Sstevel@tonic-gate #define VME16_SIZE (1<<16) 173*0Sstevel@tonic-gate #define VME16_MASK (VME16_SIZE-1) 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate #define VME24_BASE 0xFF000000 176*0Sstevel@tonic-gate #define VME24_SIZE (1<<24) 177*0Sstevel@tonic-gate #define VME24_MASK (VME24_SIZE-1) 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate /* 180*0Sstevel@tonic-gate * Virtual address where dvma starts. 181*0Sstevel@tonic-gate */ 182*0Sstevel@tonic-gate #define DVMABASE (0-(1024*1024)) 183*0Sstevel@tonic-gate 184*0Sstevel@tonic-gate /* 185*0Sstevel@tonic-gate * Context for kernel. On a Sun-4 the kernel is in every address space, 186*0Sstevel@tonic-gate * but KCONTEXT is magic in that there is never any user context there. 187*0Sstevel@tonic-gate */ 188*0Sstevel@tonic-gate #define KCONTEXT 0 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate /* 191*0Sstevel@tonic-gate * MDEVBASE is a virtual segment reserved for mapping misc. obio devices. 192*0Sstevel@tonic-gate * The base address and the number of devices mapped should not cause the 193*0Sstevel@tonic-gate * device mappings to cross a segment boundary. We use the segment 194*0Sstevel@tonic-gate * immediately before SYSBASE 195*0Sstevel@tonic-gate */ 196*0Sstevel@tonic-gate #define MDEVBASE (SYSBASE - PMGRPSIZE) 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate /* 199*0Sstevel@tonic-gate * SEGTEMP & SEGTEMP2 are virtual segments reserved for temporary operations. 200*0Sstevel@tonic-gate * We use the segments immediately before the start of debugger area. 201*0Sstevel@tonic-gate */ 202*0Sstevel@tonic-gate #define SEGTEMP ((addr_t)(DEBUGSTART - (2 * PMGRPSIZE))) 203*0Sstevel@tonic-gate #define SEGTEMP2 ((addr_t)(DEBUGSTART - PMGRPSIZE)) 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate /* 206*0Sstevel@tonic-gate * REGTEMP is only during intialization, we use the 207*0Sstevel@tonic-gate * REGION immediately before KERNELBASE, it is invalidated 208*0Sstevel@tonic-gate * after use 209*0Sstevel@tonic-gate */ 210*0Sstevel@tonic-gate #define REGTEMP ((KERNELBASE-SMGRPSIZE)&SMGRPMASK) 211*0Sstevel@tonic-gate 212*0Sstevel@tonic-gate #if defined(KERNEL) && !defined(LOCORE) 213*0Sstevel@tonic-gate 214*0Sstevel@tonic-gate #ifdef VAC 215*0Sstevel@tonic-gate void vac_dontcache(); 216*0Sstevel@tonic-gate /* 217*0Sstevel@tonic-gate * cache related constants set at boot time 218*0Sstevel@tonic-gate */ 219*0Sstevel@tonic-gate extern int vac_size; /* size of cache in bytes */ 220*0Sstevel@tonic-gate extern int vac_linesize; /* cache linesize */ 221*0Sstevel@tonic-gate extern int vac_nlines; /* number of lines in cache */ 222*0Sstevel@tonic-gate extern int vac_pglines; /* number of cache lines in a page */ 223*0Sstevel@tonic-gate #endif /* VAC */ 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate /* 226*0Sstevel@tonic-gate * Low level mmu-specific functions 227*0Sstevel@tonic-gate */ 228*0Sstevel@tonic-gate struct ctx *mmu_getctx(); 229*0Sstevel@tonic-gate void mmu_setctx(/* ctx */); 230*0Sstevel@tonic-gate void mmu_setpmg(/* base, pmg */); 231*0Sstevel@tonic-gate void mmu_settpmg(/* base, pmg */); 232*0Sstevel@tonic-gate struct pmgrp *mmu_getpmg(/* base */); 233*0Sstevel@tonic-gate void mmu_setpte(/* base, pte */); 234*0Sstevel@tonic-gate void mmu_getpte(/* base, ppte */); 235*0Sstevel@tonic-gate void mmu_getkpte(/* base, ppte */); 236*0Sstevel@tonic-gate void mmu_pmginval(/* pmg */); 237*0Sstevel@tonic-gate #ifdef MMU_3LEVEL 238*0Sstevel@tonic-gate struct smgrp *mmu_getsmg(/* base */); 239*0Sstevel@tonic-gate void mmu_setsmg(/* base, smg */); 240*0Sstevel@tonic-gate void mmu_settsmg(/* base, smg */); 241*0Sstevel@tonic-gate void mmu_smginval(/* smg */); 242*0Sstevel@tonic-gate #endif /* MMU_3LEVEL */ 243*0Sstevel@tonic-gate 244*0Sstevel@tonic-gate /* 245*0Sstevel@tonic-gate * Cache specific routines - ifdef'ed out if there is no chance 246*0Sstevel@tonic-gate * of running on a machine with a virtual address cache. 247*0Sstevel@tonic-gate */ 248*0Sstevel@tonic-gate #ifdef VAC 249*0Sstevel@tonic-gate void vac_init(); 250*0Sstevel@tonic-gate void vac_tagsinit(); 251*0Sstevel@tonic-gate void vac_flushall(); 252*0Sstevel@tonic-gate void vac_ctxflush(); 253*0Sstevel@tonic-gate #ifdef MMU_3LEVEL 254*0Sstevel@tonic-gate void vac_usrflush(); 255*0Sstevel@tonic-gate void vac_rgnflush(/* base */); 256*0Sstevel@tonic-gate #endif /* MMU_3LEVEL */ 257*0Sstevel@tonic-gate void vac_segflush(/* base */); 258*0Sstevel@tonic-gate void vac_pageflush(/* base */); 259*0Sstevel@tonic-gate void vac_flush(/* base, len */); 260*0Sstevel@tonic-gate int bp_alloc(/* map, bp, size */); 261*0Sstevel@tonic-gate #else /* VAC */ 262*0Sstevel@tonic-gate #define vac_init() 263*0Sstevel@tonic-gate #define vac_tagsinit() 264*0Sstevel@tonic-gate #define vac_flushall() 265*0Sstevel@tonic-gate #define vac_usrflush() 266*0Sstevel@tonic-gate #define vac_ctxflush() 267*0Sstevel@tonic-gate #define vac_rgnflush(base) 268*0Sstevel@tonic-gate #define vac_segflush(base) 269*0Sstevel@tonic-gate #define vac_pageflush(base) 270*0Sstevel@tonic-gate #define vac_flush(base, len) 271*0Sstevel@tonic-gate #define bp_alloc(map, bp, size) (int)rmalloc((map), (long)(size)) 272*0Sstevel@tonic-gate #endif /* VAC */ 273*0Sstevel@tonic-gate 274*0Sstevel@tonic-gate int valid_va_range(/* basep, lenp, minlen, dir */); 275*0Sstevel@tonic-gate 276*0Sstevel@tonic-gate #endif /* defined(KERNEL) && !defined(LOCORE) */ 277*0Sstevel@tonic-gate 278*0Sstevel@tonic-gate #ifdef __cplusplus 279*0Sstevel@tonic-gate } 280*0Sstevel@tonic-gate #endif 281*0Sstevel@tonic-gate 282*0Sstevel@tonic-gate #endif /* !_SUN4_MMU_H */ 283