12587Spjha /* 22587Spjha * CDDL HEADER START 32587Spjha * 42587Spjha * The contents of this file are subject to the terms of the 52587Spjha * Common Development and Distribution License (the "License"). 62587Spjha * You may not use this file except in compliance with the License. 72587Spjha * 82587Spjha * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 92587Spjha * or http://www.opensolaris.org/os/licensing. 102587Spjha * See the License for the specific language governing permissions 112587Spjha * and limitations under the License. 122587Spjha * 132587Spjha * When distributing Covered Code, include this CDDL HEADER in each 142587Spjha * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 152587Spjha * If applicable, add the following below this CDDL HEADER, with the 162587Spjha * fields enclosed by brackets "[]" replaced with your own identifying 172587Spjha * information: Portions Copyright [yyyy] [name of copyright owner] 182587Spjha * 192587Spjha * CDDL HEADER END 202587Spjha */ 212587Spjha /* 22*7302Sgdamore@opensolaris.org * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 232587Spjha * Use is subject to license terms. 242587Spjha */ 252587Spjha 262587Spjha /* private devlink info interfaces */ 272587Spjha 282587Spjha #ifndef _CFG_LINK_H 292587Spjha #define _CFG_LINK_H 302587Spjha 312587Spjha #include <devfsadm.h> 322587Spjha 332587Spjha #ifdef __cplusplus 342587Spjha extern "C" { 352587Spjha #endif 362587Spjha 372587Spjha #define SCSI_CFG_LINK_RE "^cfg/c[0-9]+$" 382587Spjha #define SBD_CFG_LINK_RE "^cfg/((((N[0-9]+[.])?(SB|IB))?[0-9]+)|[abcd])$" 392587Spjha #define USB_CFG_LINK_RE "^cfg/((usb[0-9]+)/([0-9]+)([.]([0-9])+)*)$" 402587Spjha #define PCI_CFG_LINK_RE "^cfg/[:alnum:]$" 412587Spjha #define IB_CFG_LINK_RE "^cfg/(hca[0-9A-F]+)$" 422587Spjha #define SATA_CFG_LINK_RE "^cfg/((sata[0-9]+)/([0-9]+)([.]([0-9])+)*)$" 43*7302Sgdamore@opensolaris.org #define SDCARD_CFG_LINK_RE "^cfg/sdcard[0-9]+/[0-9]+$" 442955Spjha #define PCI_CFG_PATH_LINK_RE \ 452955Spjha "^cfg/(.*(pci[0-9]|pcie[0-9]|Slot[0-9]|\\<pci\\>|\\<pcie\\>).*)$" 462587Spjha 472587Spjha #define CFG_DIRNAME "cfg" 482587Spjha 492587Spjha #define PROPVAL_PCIEX "pciex" 502587Spjha #define DEVTYPE_PCIE "pcie" 512587Spjha #define IOB_PRE "iob" 522587Spjha #define AP_PATH_SEP ":" 532587Spjha #define AP_PATH_IOB_SEP "." 543485Spjha #define IEEE_SUN_ID 0x080020 552587Spjha #define APNODE_DEFNAME 0x1 562955Spjha #define PCIDEV_NIL ((minor_t)-1) 572587Spjha 582587Spjha /* converts size in bits to a mask covering those bit positions */ 592587Spjha #define SIZE2MASK(s) ((1 << (s)) - 1) 602587Spjha #define SIZE2MASK64(s) ((1LL << (s)) - 1LL) 612587Spjha 622587Spjha /* 632587Spjha * macros for the ieee1275 "reg" property 642587Spjha * naming format and semantics: 652587Spjha * 662587Spjha * REG_<cell>_SIZE_<field> = bit size of <field> in <cell> 672587Spjha * REG_<cell>_OFF_<field> = starting bit position of <field> in <cell> 682587Spjha * 692587Spjha * REG_<cell>_<field>(r) = returns the value of <field> in <cell> using: 702587Spjha * (((r) >> REG_<cell>_OFF_<field>) & SIZE2MASK(REG_<cell>_SIZE_<field>)) 712587Spjha */ 722587Spjha #define REG_PHYSHI_SIZE_PCIDEV 5 732587Spjha #define REG_PHYSHI_OFF_PCIDEV 11 742587Spjha #define REG_PHYSHI_PCIDEV(r) \ 752587Spjha (((r) >> REG_PHYSHI_OFF_PCIDEV) & SIZE2MASK(REG_PHYSHI_SIZE_PCIDEV)) 762587Spjha 772587Spjha /* rp = ptr to 5-tuple int array */ 782587Spjha #define REG_PHYSHI_INDEX 0 792587Spjha #define REG_PHYSHI(rp) ((rp)[REG_PHYSHI_INDEX]) 802587Spjha 812587Spjha #define REG_PCIDEV(rp) (REG_PHYSHI_PCIDEV(REG_PHYSHI(rp))) 822587Spjha 832587Spjha 842587Spjha #define DEV "/dev" 852587Spjha #define DEV_LEN 4 862587Spjha #define DEVICES "/devices" 872587Spjha #define DEVICES_LEN 8 882587Spjha 892587Spjha #ifdef __cplusplus 902587Spjha } 912587Spjha #endif 922587Spjha 932587Spjha #endif /* _CFG_LINK_H */ 94