1 /* $NetBSD: kern_softint.c,v 1.38 2011/09/27 01:02:38 jym Exp $ */ 2 3 /*- 4 * Copyright (c) 2007, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Andrew Doran. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Generic software interrupt framework. 34 * 35 * Overview 36 * 37 * The soft interrupt framework provides a mechanism to schedule a 38 * low priority callback that runs with thread context. It allows 39 * for dynamic registration of software interrupts, and for fair 40 * queueing and prioritization of those interrupts. The callbacks 41 * can be scheduled to run from nearly any point in the kernel: by 42 * code running with thread context, by code running from a 43 * hardware interrupt handler, and at any interrupt priority 44 * level. 45 * 46 * Priority levels 47 * 48 * Since soft interrupt dispatch can be tied to the underlying 49 * architecture's interrupt dispatch code, it can be limited 50 * both by the capabilities of the hardware and the capabilities 51 * of the interrupt dispatch code itself. The number of priority 52 * levels is restricted to four. In order of priority (lowest to 53 * highest) the levels are: clock, bio, net, serial. 54 * 55 * The names are symbolic and in isolation do not have any direct 56 * connection with a particular kind of device activity: they are 57 * only meant as a guide. 58 * 59 * The four priority levels map directly to scheduler priority 60 * levels, and where the architecture implements 'fast' software 61 * interrupts, they also map onto interrupt priorities. The 62 * interrupt priorities are intended to be hidden from machine 63 * independent code, which should use thread-safe mechanisms to 64 * synchronize with software interrupts (for example: mutexes). 65 * 66 * Capabilities 67 * 68 * Software interrupts run with limited machine context. In 69 * particular, they do not posess any address space context. They 70 * should not try to operate on user space addresses, or to use 71 * virtual memory facilities other than those noted as interrupt 72 * safe. 73 * 74 * Unlike hardware interrupts, software interrupts do have thread 75 * context. They may block on synchronization objects, sleep, and 76 * resume execution at a later time. 77 * 78 * Since software interrupts are a limited resource and run with 79 * higher priority than most other LWPs in the system, all 80 * block-and-resume activity by a software interrupt must be kept 81 * short to allow futher processing at that level to continue. By 82 * extension, code running with process context must take care to 83 * ensure that any lock that may be taken from a software interrupt 84 * can not be held for more than a short period of time. 85 * 86 * The kernel does not allow software interrupts to use facilities 87 * or perform actions that may block for a significant amount of 88 * time. This means that it's not valid for a software interrupt 89 * to sleep on condition variables or wait for resources to become 90 * available (for example, memory). 91 * 92 * Per-CPU operation 93 * 94 * If a soft interrupt is triggered on a CPU, it can only be 95 * dispatched on the same CPU. Each LWP dedicated to handling a 96 * soft interrupt is bound to its home CPU, so if the LWP blocks 97 * and needs to run again, it can only run there. Nearly all data 98 * structures used to manage software interrupts are per-CPU. 99 * 100 * The per-CPU requirement is intended to reduce "ping-pong" of 101 * cache lines between CPUs: lines occupied by data structures 102 * used to manage the soft interrupts, and lines occupied by data 103 * items being passed down to the soft interrupt. As a positive 104 * side effect, this also means that the soft interrupt dispatch 105 * code does not need to to use spinlocks to synchronize. 106 * 107 * Generic implementation 108 * 109 * A generic, low performance implementation is provided that 110 * works across all architectures, with no machine-dependent 111 * modifications needed. This implementation uses the scheduler, 112 * and so has a number of restrictions: 113 * 114 * 1) The software interrupts are not currently preemptive, so 115 * must wait for the currently executing LWP to yield the CPU. 116 * This can introduce latency. 117 * 118 * 2) An expensive context switch is required for a software 119 * interrupt to be handled. 120 * 121 * 'Fast' software interrupts 122 * 123 * If an architectures defines __HAVE_FAST_SOFTINTS, it implements 124 * the fast mechanism. Threads running either in the kernel or in 125 * userspace will be interrupted, but will not be preempted. When 126 * the soft interrupt completes execution, the interrupted LWP 127 * is resumed. Interrupt dispatch code must provide the minimum 128 * level of context necessary for the soft interrupt to block and 129 * be resumed at a later time. The machine-dependent dispatch 130 * path looks something like the following: 131 * 132 * softintr() 133 * { 134 * go to IPL_HIGH if necessary for switch; 135 * save any necessary registers in a format that can be 136 * restored by cpu_switchto if the softint blocks; 137 * arrange for cpu_switchto() to restore into the 138 * trampoline function; 139 * identify LWP to handle this interrupt; 140 * switch to the LWP's stack; 141 * switch register stacks, if necessary; 142 * assign new value of curlwp; 143 * call MI softint_dispatch, passing old curlwp and IPL 144 * to execute interrupt at; 145 * switch back to old stack; 146 * switch back to old register stack, if necessary; 147 * restore curlwp; 148 * return to interrupted LWP; 149 * } 150 * 151 * If the soft interrupt blocks, a trampoline function is returned 152 * to in the context of the interrupted LWP, as arranged for by 153 * softint(): 154 * 155 * softint_ret() 156 * { 157 * unlock soft interrupt LWP; 158 * resume interrupt processing, likely returning to 159 * interrupted LWP or dispatching another, different 160 * interrupt; 161 * } 162 * 163 * Once the soft interrupt has fired (and even if it has blocked), 164 * no further soft interrupts at that level will be triggered by 165 * MI code until the soft interrupt handler has ceased execution. 166 * If a soft interrupt handler blocks and is resumed, it resumes 167 * execution as a normal LWP (kthread) and gains VM context. Only 168 * when it has completed and is ready to fire again will it 169 * interrupt other threads. 170 * 171 * Future directions 172 * 173 * Provide a cheap way to direct software interrupts to remote 174 * CPUs. Provide a way to enqueue work items into the handler 175 * record, removing additional spl calls (see subr_workqueue.c). 176 */ 177 178 #include <sys/cdefs.h> 179 __KERNEL_RCSID(0, "$NetBSD: kern_softint.c,v 1.38 2011/09/27 01:02:38 jym Exp $"); 180 181 #include <sys/param.h> 182 #include <sys/proc.h> 183 #include <sys/intr.h> 184 #include <sys/mutex.h> 185 #include <sys/kthread.h> 186 #include <sys/evcnt.h> 187 #include <sys/cpu.h> 188 #include <sys/xcall.h> 189 190 #include <net/netisr.h> 191 192 #include <uvm/uvm_extern.h> 193 194 /* This could overlap with signal info in struct lwp. */ 195 typedef struct softint { 196 SIMPLEQ_HEAD(, softhand) si_q; 197 struct lwp *si_lwp; 198 struct cpu_info *si_cpu; 199 uintptr_t si_machdep; 200 struct evcnt si_evcnt; 201 struct evcnt si_evcnt_block; 202 int si_active; 203 char si_name[8]; 204 char si_name_block[8+6]; 205 } softint_t; 206 207 typedef struct softhand { 208 SIMPLEQ_ENTRY(softhand) sh_q; 209 void (*sh_func)(void *); 210 void *sh_arg; 211 softint_t *sh_isr; 212 u_int sh_flags; 213 } softhand_t; 214 215 typedef struct softcpu { 216 struct cpu_info *sc_cpu; 217 softint_t sc_int[SOFTINT_COUNT]; 218 softhand_t sc_hand[1]; 219 } softcpu_t; 220 221 static void softint_thread(void *); 222 223 u_int softint_bytes = 8192; 224 u_int softint_timing; 225 static u_int softint_max; 226 static kmutex_t softint_lock; 227 static void *softint_netisrs[NETISR_MAX]; 228 229 /* 230 * softint_init_isr: 231 * 232 * Initialize a single interrupt level for a single CPU. 233 */ 234 static void 235 softint_init_isr(softcpu_t *sc, const char *desc, pri_t pri, u_int level) 236 { 237 struct cpu_info *ci; 238 softint_t *si; 239 int error; 240 241 si = &sc->sc_int[level]; 242 ci = sc->sc_cpu; 243 si->si_cpu = ci; 244 245 SIMPLEQ_INIT(&si->si_q); 246 247 error = kthread_create(pri, KTHREAD_MPSAFE | KTHREAD_INTR | 248 KTHREAD_IDLE, ci, softint_thread, si, &si->si_lwp, 249 "soft%s/%u", desc, ci->ci_index); 250 if (error != 0) 251 panic("softint_init_isr: error %d", error); 252 253 snprintf(si->si_name, sizeof(si->si_name), "%s/%u", desc, 254 ci->ci_index); 255 evcnt_attach_dynamic(&si->si_evcnt, EVCNT_TYPE_MISC, NULL, 256 "softint", si->si_name); 257 snprintf(si->si_name_block, sizeof(si->si_name_block), "%s block/%u", 258 desc, ci->ci_index); 259 evcnt_attach_dynamic(&si->si_evcnt_block, EVCNT_TYPE_MISC, NULL, 260 "softint", si->si_name_block); 261 262 si->si_lwp->l_private = si; 263 softint_init_md(si->si_lwp, level, &si->si_machdep); 264 } 265 266 /* 267 * softint_init: 268 * 269 * Initialize per-CPU data structures. Called from mi_cpu_attach(). 270 */ 271 void 272 softint_init(struct cpu_info *ci) 273 { 274 static struct cpu_info *first; 275 softcpu_t *sc, *scfirst; 276 softhand_t *sh, *shmax; 277 278 if (first == NULL) { 279 /* Boot CPU. */ 280 first = ci; 281 mutex_init(&softint_lock, MUTEX_DEFAULT, IPL_NONE); 282 softint_bytes = round_page(softint_bytes); 283 softint_max = (softint_bytes - sizeof(softcpu_t)) / 284 sizeof(softhand_t); 285 } 286 287 /* Use uvm_km(9) for persistent, page-aligned allocation. */ 288 sc = (softcpu_t *)uvm_km_alloc(kernel_map, softint_bytes, 0, 289 UVM_KMF_WIRED | UVM_KMF_ZERO); 290 if (sc == NULL) 291 panic("softint_init_cpu: cannot allocate memory"); 292 293 ci->ci_data.cpu_softcpu = sc; 294 ci->ci_data.cpu_softints = 0; 295 sc->sc_cpu = ci; 296 297 softint_init_isr(sc, "net", PRI_SOFTNET, SOFTINT_NET); 298 softint_init_isr(sc, "bio", PRI_SOFTBIO, SOFTINT_BIO); 299 softint_init_isr(sc, "clk", PRI_SOFTCLOCK, SOFTINT_CLOCK); 300 softint_init_isr(sc, "ser", PRI_SOFTSERIAL, SOFTINT_SERIAL); 301 302 if (first != ci) { 303 mutex_enter(&softint_lock); 304 scfirst = first->ci_data.cpu_softcpu; 305 sh = sc->sc_hand; 306 memcpy(sh, scfirst->sc_hand, sizeof(*sh) * softint_max); 307 /* Update pointers for this CPU. */ 308 for (shmax = sh + softint_max; sh < shmax; sh++) { 309 if (sh->sh_func == NULL) 310 continue; 311 sh->sh_isr = 312 &sc->sc_int[sh->sh_flags & SOFTINT_LVLMASK]; 313 } 314 mutex_exit(&softint_lock); 315 } else { 316 /* 317 * Establish handlers for legacy net interrupts. 318 * XXX Needs to go away. 319 */ 320 #define DONETISR(n, f) \ 321 softint_netisrs[(n)] = softint_establish(SOFTINT_NET|SOFTINT_MPSAFE,\ 322 (void (*)(void *))(f), NULL) 323 #include <net/netisr_dispatch.h> 324 } 325 } 326 327 /* 328 * softint_establish: 329 * 330 * Register a software interrupt handler. 331 */ 332 void * 333 softint_establish(u_int flags, void (*func)(void *), void *arg) 334 { 335 CPU_INFO_ITERATOR cii; 336 struct cpu_info *ci; 337 softcpu_t *sc; 338 softhand_t *sh; 339 u_int level, index; 340 341 level = (flags & SOFTINT_LVLMASK); 342 KASSERT(level < SOFTINT_COUNT); 343 KASSERT((flags & SOFTINT_IMPMASK) == 0); 344 345 mutex_enter(&softint_lock); 346 347 /* Find a free slot. */ 348 sc = curcpu()->ci_data.cpu_softcpu; 349 for (index = 1; index < softint_max; index++) { 350 if (sc->sc_hand[index].sh_func == NULL) 351 break; 352 } 353 if (index == softint_max) { 354 mutex_exit(&softint_lock); 355 printf("WARNING: softint_establish: table full, " 356 "increase softint_bytes\n"); 357 return NULL; 358 } 359 360 /* Set up the handler on each CPU. */ 361 if (ncpu < 2) { 362 /* XXX hack for machines with no CPU_INFO_FOREACH() early on */ 363 sc = curcpu()->ci_data.cpu_softcpu; 364 sh = &sc->sc_hand[index]; 365 sh->sh_isr = &sc->sc_int[level]; 366 sh->sh_func = func; 367 sh->sh_arg = arg; 368 sh->sh_flags = flags; 369 } else for (CPU_INFO_FOREACH(cii, ci)) { 370 sc = ci->ci_data.cpu_softcpu; 371 sh = &sc->sc_hand[index]; 372 sh->sh_isr = &sc->sc_int[level]; 373 sh->sh_func = func; 374 sh->sh_arg = arg; 375 sh->sh_flags = flags; 376 } 377 378 mutex_exit(&softint_lock); 379 380 return (void *)((uint8_t *)&sc->sc_hand[index] - (uint8_t *)sc); 381 } 382 383 /* 384 * softint_disestablish: 385 * 386 * Unregister a software interrupt handler. The soft interrupt could 387 * still be active at this point, but the caller commits not to try 388 * and trigger it again once this call is made. The caller must not 389 * hold any locks that could be taken from soft interrupt context, 390 * because we will wait for the softint to complete if it's still 391 * running. 392 */ 393 void 394 softint_disestablish(void *arg) 395 { 396 CPU_INFO_ITERATOR cii; 397 struct cpu_info *ci; 398 softcpu_t *sc; 399 softhand_t *sh; 400 uintptr_t offset; 401 uint64_t where; 402 u_int flags; 403 404 offset = (uintptr_t)arg; 405 KASSERT(offset != 0 && offset < softint_bytes); 406 407 /* 408 * Run a cross call so we see up to date values of sh_flags from 409 * all CPUs. Once softint_disestablish() is called, the caller 410 * commits to not trigger the interrupt and set SOFTINT_ACTIVE on 411 * it again. So, we are only looking for handler records with 412 * SOFTINT_ACTIVE already set. 413 */ 414 where = xc_broadcast(0, (xcfunc_t)nullop, NULL, NULL); 415 xc_wait(where); 416 417 for (;;) { 418 /* Collect flag values from each CPU. */ 419 flags = 0; 420 for (CPU_INFO_FOREACH(cii, ci)) { 421 sc = ci->ci_data.cpu_softcpu; 422 sh = (softhand_t *)((uint8_t *)sc + offset); 423 KASSERT(sh->sh_func != NULL); 424 flags |= sh->sh_flags; 425 } 426 /* Inactive on all CPUs? */ 427 if ((flags & SOFTINT_ACTIVE) == 0) { 428 break; 429 } 430 /* Oops, still active. Wait for it to clear. */ 431 (void)kpause("softdis", false, 1, NULL); 432 } 433 434 /* Clear the handler on each CPU. */ 435 mutex_enter(&softint_lock); 436 for (CPU_INFO_FOREACH(cii, ci)) { 437 sc = ci->ci_data.cpu_softcpu; 438 sh = (softhand_t *)((uint8_t *)sc + offset); 439 KASSERT(sh->sh_func != NULL); 440 sh->sh_func = NULL; 441 } 442 mutex_exit(&softint_lock); 443 } 444 445 /* 446 * softint_schedule: 447 * 448 * Trigger a software interrupt. Must be called from a hardware 449 * interrupt handler, or with preemption disabled (since we are 450 * using the value of curcpu()). 451 */ 452 void 453 softint_schedule(void *arg) 454 { 455 softhand_t *sh; 456 softint_t *si; 457 uintptr_t offset; 458 int s; 459 460 KASSERT(kpreempt_disabled()); 461 462 /* Find the handler record for this CPU. */ 463 offset = (uintptr_t)arg; 464 KASSERT(offset != 0 && offset < softint_bytes); 465 sh = (softhand_t *)((uint8_t *)curcpu()->ci_data.cpu_softcpu + offset); 466 467 /* If it's already pending there's nothing to do. */ 468 if ((sh->sh_flags & SOFTINT_PENDING) != 0) { 469 return; 470 } 471 472 /* 473 * Enqueue the handler into the LWP's pending list. 474 * If the LWP is completely idle, then make it run. 475 */ 476 s = splhigh(); 477 if ((sh->sh_flags & SOFTINT_PENDING) == 0) { 478 si = sh->sh_isr; 479 sh->sh_flags |= SOFTINT_PENDING; 480 SIMPLEQ_INSERT_TAIL(&si->si_q, sh, sh_q); 481 if (si->si_active == 0) { 482 si->si_active = 1; 483 softint_trigger(si->si_machdep); 484 } 485 } 486 splx(s); 487 } 488 489 /* 490 * softint_execute: 491 * 492 * Invoke handlers for the specified soft interrupt. 493 * Must be entered at splhigh. Will drop the priority 494 * to the level specified, but returns back at splhigh. 495 */ 496 static inline void 497 softint_execute(softint_t *si, lwp_t *l, int s) 498 { 499 softhand_t *sh; 500 bool havelock; 501 502 #ifdef __HAVE_FAST_SOFTINTS 503 KASSERT(si->si_lwp == curlwp); 504 #else 505 /* May be running in user context. */ 506 #endif 507 KASSERT(si->si_cpu == curcpu()); 508 KASSERT(si->si_lwp->l_wchan == NULL); 509 KASSERT(si->si_active); 510 511 havelock = false; 512 513 /* 514 * Note: due to priority inheritance we may have interrupted a 515 * higher priority LWP. Since the soft interrupt must be quick 516 * and is non-preemptable, we don't bother yielding. 517 */ 518 519 while (!SIMPLEQ_EMPTY(&si->si_q)) { 520 /* 521 * Pick the longest waiting handler to run. We block 522 * interrupts but do not lock in order to do this, as 523 * we are protecting against the local CPU only. 524 */ 525 sh = SIMPLEQ_FIRST(&si->si_q); 526 SIMPLEQ_REMOVE_HEAD(&si->si_q, sh_q); 527 KASSERT((sh->sh_flags & SOFTINT_PENDING) != 0); 528 KASSERT((sh->sh_flags & SOFTINT_ACTIVE) == 0); 529 sh->sh_flags ^= (SOFTINT_PENDING | SOFTINT_ACTIVE); 530 splx(s); 531 532 /* Run the handler. */ 533 if (sh->sh_flags & SOFTINT_MPSAFE) { 534 if (havelock) { 535 KERNEL_UNLOCK_ONE(l); 536 havelock = false; 537 } 538 } else if (!havelock) { 539 KERNEL_LOCK(1, l); 540 havelock = true; 541 } 542 (*sh->sh_func)(sh->sh_arg); 543 544 /* Diagnostic: check that spin-locks have not leaked. */ 545 KASSERTMSG(curcpu()->ci_mtx_count == 0, 546 "%s: ci_mtx_count (%d) != 0, sh_func %p\n", 547 __func__, curcpu()->ci_mtx_count, sh->sh_func); 548 549 (void)splhigh(); 550 KASSERT((sh->sh_flags & SOFTINT_ACTIVE) != 0); 551 sh->sh_flags ^= SOFTINT_ACTIVE; 552 } 553 554 if (havelock) { 555 KERNEL_UNLOCK_ONE(l); 556 } 557 558 /* 559 * Unlocked, but only for statistics. 560 * Should be per-CPU to prevent cache ping-pong. 561 */ 562 curcpu()->ci_data.cpu_nsoft++; 563 564 KASSERT(si->si_cpu == curcpu()); 565 KASSERT(si->si_lwp->l_wchan == NULL); 566 KASSERT(si->si_active); 567 si->si_evcnt.ev_count++; 568 si->si_active = 0; 569 } 570 571 /* 572 * softint_block: 573 * 574 * Update statistics when the soft interrupt blocks. 575 */ 576 void 577 softint_block(lwp_t *l) 578 { 579 softint_t *si = l->l_private; 580 581 KASSERT((l->l_pflag & LP_INTR) != 0); 582 si->si_evcnt_block.ev_count++; 583 } 584 585 /* 586 * schednetisr: 587 * 588 * Trigger a legacy network interrupt. XXX Needs to go away. 589 */ 590 void 591 schednetisr(int isr) 592 { 593 594 softint_schedule(softint_netisrs[isr]); 595 } 596 597 #ifndef __HAVE_FAST_SOFTINTS 598 599 #ifdef __HAVE_PREEMPTION 600 #error __HAVE_PREEMPTION requires __HAVE_FAST_SOFTINTS 601 #endif 602 603 /* 604 * softint_init_md: 605 * 606 * Slow path: perform machine-dependent initialization. 607 */ 608 void 609 softint_init_md(lwp_t *l, u_int level, uintptr_t *machdep) 610 { 611 softint_t *si; 612 613 *machdep = (1 << level); 614 si = l->l_private; 615 616 lwp_lock(l); 617 lwp_unlock_to(l, l->l_cpu->ci_schedstate.spc_mutex); 618 lwp_lock(l); 619 /* Cheat and make the KASSERT in softint_thread() happy. */ 620 si->si_active = 1; 621 l->l_stat = LSRUN; 622 sched_enqueue(l, false); 623 lwp_unlock(l); 624 } 625 626 /* 627 * softint_trigger: 628 * 629 * Slow path: cause a soft interrupt handler to begin executing. 630 * Called at IPL_HIGH. 631 */ 632 void 633 softint_trigger(uintptr_t machdep) 634 { 635 struct cpu_info *ci; 636 lwp_t *l; 637 638 l = curlwp; 639 ci = l->l_cpu; 640 ci->ci_data.cpu_softints |= machdep; 641 if (l == ci->ci_data.cpu_idlelwp) { 642 cpu_need_resched(ci, 0); 643 } else { 644 /* MI equivalent of aston() */ 645 cpu_signotify(l); 646 } 647 } 648 649 /* 650 * softint_thread: 651 * 652 * Slow path: MI software interrupt dispatch. 653 */ 654 void 655 softint_thread(void *cookie) 656 { 657 softint_t *si; 658 lwp_t *l; 659 int s; 660 661 l = curlwp; 662 si = l->l_private; 663 664 for (;;) { 665 /* 666 * Clear pending status and run it. We must drop the 667 * spl before mi_switch(), since IPL_HIGH may be higher 668 * than IPL_SCHED (and it is not safe to switch at a 669 * higher level). 670 */ 671 s = splhigh(); 672 l->l_cpu->ci_data.cpu_softints &= ~si->si_machdep; 673 softint_execute(si, l, s); 674 splx(s); 675 676 lwp_lock(l); 677 l->l_stat = LSIDL; 678 mi_switch(l); 679 } 680 } 681 682 /* 683 * softint_picklwp: 684 * 685 * Slow path: called from mi_switch() to pick the highest priority 686 * soft interrupt LWP that needs to run. 687 */ 688 lwp_t * 689 softint_picklwp(void) 690 { 691 struct cpu_info *ci; 692 u_int mask; 693 softint_t *si; 694 lwp_t *l; 695 696 ci = curcpu(); 697 si = ((softcpu_t *)ci->ci_data.cpu_softcpu)->sc_int; 698 mask = ci->ci_data.cpu_softints; 699 700 if ((mask & (1 << SOFTINT_SERIAL)) != 0) { 701 l = si[SOFTINT_SERIAL].si_lwp; 702 } else if ((mask & (1 << SOFTINT_NET)) != 0) { 703 l = si[SOFTINT_NET].si_lwp; 704 } else if ((mask & (1 << SOFTINT_BIO)) != 0) { 705 l = si[SOFTINT_BIO].si_lwp; 706 } else if ((mask & (1 << SOFTINT_CLOCK)) != 0) { 707 l = si[SOFTINT_CLOCK].si_lwp; 708 } else { 709 panic("softint_picklwp"); 710 } 711 712 return l; 713 } 714 715 /* 716 * softint_overlay: 717 * 718 * Slow path: called from lwp_userret() to run a soft interrupt 719 * within the context of a user thread. 720 */ 721 void 722 softint_overlay(void) 723 { 724 struct cpu_info *ci; 725 u_int softints, oflag; 726 softint_t *si; 727 pri_t obase; 728 lwp_t *l; 729 int s; 730 731 l = curlwp; 732 KASSERT((l->l_pflag & LP_INTR) == 0); 733 734 /* 735 * Arrange to elevate priority if the LWP blocks. Also, bind LWP 736 * to the CPU. Note: disable kernel preemption before doing that. 737 */ 738 s = splhigh(); 739 ci = l->l_cpu; 740 si = ((softcpu_t *)ci->ci_data.cpu_softcpu)->sc_int; 741 742 obase = l->l_kpribase; 743 l->l_kpribase = PRI_KERNEL_RT; 744 oflag = l->l_pflag; 745 l->l_pflag = oflag | LP_INTR | LP_BOUND; 746 747 while ((softints = ci->ci_data.cpu_softints) != 0) { 748 if ((softints & (1 << SOFTINT_SERIAL)) != 0) { 749 ci->ci_data.cpu_softints &= ~(1 << SOFTINT_SERIAL); 750 softint_execute(&si[SOFTINT_SERIAL], l, s); 751 continue; 752 } 753 if ((softints & (1 << SOFTINT_NET)) != 0) { 754 ci->ci_data.cpu_softints &= ~(1 << SOFTINT_NET); 755 softint_execute(&si[SOFTINT_NET], l, s); 756 continue; 757 } 758 if ((softints & (1 << SOFTINT_BIO)) != 0) { 759 ci->ci_data.cpu_softints &= ~(1 << SOFTINT_BIO); 760 softint_execute(&si[SOFTINT_BIO], l, s); 761 continue; 762 } 763 if ((softints & (1 << SOFTINT_CLOCK)) != 0) { 764 ci->ci_data.cpu_softints &= ~(1 << SOFTINT_CLOCK); 765 softint_execute(&si[SOFTINT_CLOCK], l, s); 766 continue; 767 } 768 } 769 l->l_pflag = oflag; 770 l->l_kpribase = obase; 771 splx(s); 772 } 773 774 #else /* !__HAVE_FAST_SOFTINTS */ 775 776 /* 777 * softint_thread: 778 * 779 * Fast path: the LWP is switched to without restoring any state, 780 * so we should not arrive here - there is a direct handoff between 781 * the interrupt stub and softint_dispatch(). 782 */ 783 void 784 softint_thread(void *cookie) 785 { 786 787 panic("softint_thread"); 788 } 789 790 /* 791 * softint_dispatch: 792 * 793 * Fast path: entry point from machine-dependent code. 794 */ 795 void 796 softint_dispatch(lwp_t *pinned, int s) 797 { 798 struct bintime now; 799 softint_t *si; 800 u_int timing; 801 lwp_t *l; 802 803 KASSERT((pinned->l_pflag & LP_RUNNING) != 0); 804 l = curlwp; 805 si = l->l_private; 806 807 /* 808 * Note the interrupted LWP, and mark the current LWP as running 809 * before proceeding. Although this must as a rule be done with 810 * the LWP locked, at this point no external agents will want to 811 * modify the interrupt LWP's state. 812 */ 813 timing = (softint_timing ? LP_TIMEINTR : 0); 814 l->l_switchto = pinned; 815 l->l_stat = LSONPROC; 816 l->l_pflag |= (LP_RUNNING | timing); 817 818 /* 819 * Dispatch the interrupt. If softints are being timed, charge 820 * for it. 821 */ 822 if (timing) 823 binuptime(&l->l_stime); 824 softint_execute(si, l, s); 825 if (timing) { 826 binuptime(&now); 827 updatertime(l, &now); 828 l->l_pflag &= ~LP_TIMEINTR; 829 } 830 831 /* 832 * If we blocked while handling the interrupt, the pinned LWP is 833 * gone so switch to the idle LWP. It will select a new LWP to 834 * run. 835 * 836 * We must drop the priority level as switching at IPL_HIGH could 837 * deadlock the system. We have already set si->si_active = 0, 838 * which means another interrupt at this level can be triggered. 839 * That's not be a problem: we are lowering to level 's' which will 840 * prevent softint_dispatch() from being reentered at level 's', 841 * until the priority is finally dropped to IPL_NONE on entry to 842 * the LWP chosen by lwp_exit_switchaway(). 843 */ 844 l->l_stat = LSIDL; 845 if (l->l_switchto == NULL) { 846 splx(s); 847 pmap_deactivate(l); 848 lwp_exit_switchaway(l); 849 /* NOTREACHED */ 850 } 851 l->l_switchto = NULL; 852 l->l_pflag &= ~LP_RUNNING; 853 } 854 855 #endif /* !__HAVE_FAST_SOFTINTS */ 856